diff --git a/hw/unit_tests/cache/cachesim.cpp b/hw/unit_tests/cache/cachesim.cpp
index e4f6bfdb..c105e02e 100644
--- a/hw/unit_tests/cache/cachesim.cpp
+++ b/hw/unit_tests/cache/cachesim.cpp
@@ -58,7 +58,7 @@ void CacheSim::reset() {
 }
 
 void CacheSim::step() {
-  std::cout << timestamp << ": [sim] step()" << std::endl;
+  //std::cout << timestamp << ": [sim] step()" << std::endl;
   //toggle clock
   cache_->clk = 0;
   this->eval();
@@ -95,6 +95,7 @@ void CacheSim::run(){
       if(!cache_->core_req_valid && !cache_->core_rsp_valid){
         valid--; 
       }
+      this->display_hit_miss();
   }
 }
 
@@ -261,7 +262,7 @@ void CacheSim::get_core_rsp(unsigned int (&rsp)[4]){
 }
 
 void CacheSim::get_core_req(){
-  std::cout << cache_->genblk5_BRA_0_KET_->bank->is_fill_in_pipe<< std::endl; 
+  //std::cout << cache_->genblk5_BRA_0_KET_->bank->is_fill_in_pipe<< std::endl; 
   char check = cache_->core_req_valid;
   std::cout << std::hex << "core_req_valid: " << check << std::endl;
   std::cout << std::hex << "core_req_data[0]: " << cache_->core_req_data[0] << std::endl;
@@ -287,3 +288,7 @@ void CacheSim::get_dram_rsp(){
   std::cout << std::hex << "dram_rsp_ready: " << cache_->dram_rsp_ready << std::endl;
 }
 
+void CacheSim::display_hit_miss(){
+  std::cout << std::hex << "Misses: " << cache_->misses << std::endl; 
+}
+
diff --git a/hw/unit_tests/cache/cachesim.h b/hw/unit_tests/cache/cachesim.h
index 84af025a..51e1de81 100644
--- a/hw/unit_tests/cache/cachesim.h
+++ b/hw/unit_tests/cache/cachesim.h
@@ -62,6 +62,7 @@ public:
   bool get_core_req_ready();
   bool get_core_rsp_ready();
   void get_dram_rsp();
+  void display_hit_miss(); 
 
 
 private:  
diff --git a/hw/unit_tests/cache/testbench.cpp b/hw/unit_tests/cache/testbench.cpp
index bf4cd602..4f6073bf 100644
--- a/hw/unit_tests/cache/testbench.cpp
+++ b/hw/unit_tests/cache/testbench.cpp
@@ -81,7 +81,9 @@ int HIT_1(CacheSim *sim){
 }
 
 int MISS_1(CacheSim *sim){
-  unsigned int addr[4] = {0x12222222, 0xabbbbbbb, 0xcddddddd, 0xe4444444};
+  unsigned int addr1[4] = {0x12222222, 0xabbbbbbb, 0xcddddddd, 0xe4444444};
+  unsigned int addr2[4] = {0x12244444, 0xabb0bbbb, 0xcddd0ddd, 0xe0444444};
+  unsigned int addr3[4] = {0x12888888, 0xa0bbbbbb, 0xcddddd0d, 0xe4444440};
   unsigned int data[4] = {0xffffffff, 0x11111111, 0x22222222, 0x33333333};
   unsigned int rsp[4] = {0,0,0,0};
   char responded = 0;
@@ -90,25 +92,46 @@ int MISS_1(CacheSim *sim){
   write->valid = 0xf;
   write->rw = 0xf;
   write->byteen = 0xffff;
-  write->addr = addr; 
+  write->addr = addr1; 
   write->data = data;
   write->tag = 0xff;
 
   //read req
-  core_req_t* read = new core_req_t;
-  read->valid = 0xf;
-  read->rw = 0;
-  read->byteen = 0xffff;
-  read->addr = addr;
-  read->data = addr; 
-  read->tag = 0xff;
+  core_req_t* read1 = new core_req_t;
+  read1->valid = 0xf;
+  read1->rw = 0;
+  read1->byteen = 0xffff;
+  read1->addr = addr1;
+  read1->data = data; 
+  read1->tag = 0xff;
+
+  //read req
+  core_req_t* read2 = new core_req_t;
+  read2->valid = 0xf;
+  read2->rw = 0;
+  read2->byteen = 0xffff;
+  read2->addr = addr2;
+  read2->data = data; 
+  read2->tag = 0xff;
+
+  //read req
+  core_req_t* read3 = new core_req_t;
+  read3->valid = 0xf;
+  read3->rw = 0;
+  read3->byteen = 0xffff;
+  read3->addr = addr3;
+  read3->data = data; 
+  read3->tag = 0xff;
   
   // reset the device
   sim->reset();
 
   //queue reqs
-  sim->send_req(write);
-  sim->send_req(read);
+  //sim->send_req(write);
+  sim->send_req(read1);
+  sim->send_req(read2);
+  sim->send_req(read3);
+
 
   sim->run();
 
@@ -201,7 +224,7 @@ int main(int argc, char **argv)
   RAM ram;
 	CacheSim cachesim;
   cachesim.attach_ram(&ram);
-  int check = HIT_1(&cachesim);
+  int check = REQ_RSP(&cachesim);
   if(check){
     std::cout << "PASSED" << std::endl;
   } else {