diff --git a/hw/rtl/cache/VX_bank.v b/hw/rtl/cache/VX_bank.v index 83428229..74ba7bc5 100644 --- a/hw/rtl/cache/VX_bank.v +++ b/hw/rtl/cache/VX_bank.v @@ -208,8 +208,18 @@ module VX_bank #( wire [CORE_TAG_WIDTH-1:0] mrvq_tag_st0; wire [`BYTE_EN_BITS-1:0] mrvq_mem_read_st0; wire [`BYTE_EN_BITS-1:0] mrvq_mem_write_st0; - + wire mrvq_is_snp_st0; + +`DEBUG_BEGIN + wire mrvq_pending_hazard_st1e; + wire st2_pending_hazard_st1e; + wire force_request_miss_st1e; +`DEBUG_END + wire miss_add; + wire miss_add_unqual; + wire miss_add_because_miss; + wire miss_add_because_pending; wire[`LINE_ADDR_WIDTH-1:0] miss_add_addr; wire[`BASE_ADDR_BITS-1:0] miss_add_wsel; wire[`WORD_WIDTH-1:0] miss_add_data; @@ -238,9 +248,9 @@ module VX_bank #( end end - if (is_fill_st2) begin - is_fill_in_pipe = 1; - end + // if (is_fill_st2) begin + // is_fill_in_pipe = 1; + // end end assign mrvq_pop = mrvq_valid_st0 && !stall_bank_pipe; @@ -252,6 +262,7 @@ module VX_bank #( wire qual_valid_st0; wire [`LINE_ADDR_WIDTH-1:0] qual_addr_st0; wire [`WORD_SELECT_ADDR_END:0] qual_wsel_st0; + wire qual_from_mrvq_st0; wire [`WORD_WIDTH-1:0] qual_writeword_st0; wire [`BANK_LINE_WIDTH-1:0] qual_writedata_st0; @@ -267,6 +278,7 @@ module VX_bank #( wire [`BANK_LINE_WIDTH-1:0] writedata_st1 [STAGE_1_CYCLES-1:0]; wire [SNP_REQ_TAG_WIDTH-1:0] snrq_tag_st1 [STAGE_1_CYCLES-1:0]; wire is_snp_st1 [STAGE_1_CYCLES-1:0]; + wire from_mrvq_st1 [STAGE_1_CYCLES-1:0]; assign qual_is_fill_st0 = dfpq_pop; @@ -294,34 +306,38 @@ module VX_bank #( (snrq_pop) ? 1 : 0; - assign qual_is_snp_st0 = snrq_pop ? 1 : 0; + assign qual_is_snp_st0 = mrvq_pop ? mrvq_is_snp_st0 : + snrq_pop ? 1 : + 0; assign qual_writeword_st0 = mrvq_pop ? mrvq_writeword_st0 : reqq_pop ? reqq_req_writeword_st0 : 0; + assign qual_from_mrvq_st0 = mrvq_pop; + VX_generic_register #( - .N(1 + 1 + 1 + `LINE_ADDR_WIDTH + `BASE_ADDR_BITS + `WORD_WIDTH + `REQ_INST_META_WIDTH + 1 + `BANK_LINE_WIDTH + SNP_REQ_TAG_WIDTH) + .N(1+ 1 + 1 + 1 + `LINE_ADDR_WIDTH + `BASE_ADDR_BITS + `WORD_WIDTH + `REQ_INST_META_WIDTH + 1 + `BANK_LINE_WIDTH + SNP_REQ_TAG_WIDTH) ) s0_1_c0 ( .clk (clk), .reset (reset), .stall (stall_bank_pipe), .flush (0), - .in ({qual_is_snp_st0, snrq_tag_st0, qual_going_to_write_st0, qual_valid_st0, qual_addr_st0, qual_wsel_st0, qual_writeword_st0, qual_inst_meta_st0, qual_is_fill_st0, qual_writedata_st0}), - .out ({is_snp_st1[0], snrq_tag_st1[0], going_to_write_st1[0], valid_st1[0], addr_st1[0], wsel_st1[0], writeword_st1[0], inst_meta_st1[0], is_fill_st1[0], writedata_st1[0]}) + .in ({qual_from_mrvq_st0, qual_is_snp_st0, snrq_tag_st0, qual_going_to_write_st0, qual_valid_st0, qual_addr_st0, qual_wsel_st0, qual_writeword_st0, qual_inst_meta_st0, qual_is_fill_st0, qual_writedata_st0}), + .out ({from_mrvq_st1[0] , is_snp_st1[0], snrq_tag_st1[0], going_to_write_st1[0], valid_st1[0], addr_st1[0], wsel_st1[0], writeword_st1[0], inst_meta_st1[0], is_fill_st1[0], writedata_st1[0]}) ); genvar i; for (i = 1; i < STAGE_1_CYCLES; i++) begin VX_generic_register #( - .N(1 + 1 + 1 + `LINE_ADDR_WIDTH + `BASE_ADDR_BITS + `WORD_WIDTH + `REQ_INST_META_WIDTH + 1 + `BANK_LINE_WIDTH + SNP_REQ_TAG_WIDTH) + .N(1+ 1 + 1 + 1 + `LINE_ADDR_WIDTH + `BASE_ADDR_BITS + `WORD_WIDTH + `REQ_INST_META_WIDTH + 1 + `BANK_LINE_WIDTH + SNP_REQ_TAG_WIDTH) ) s0_1_cc ( .clk (clk), .reset(reset), .stall(stall_bank_pipe), .flush(0), - .in ({is_snp_st1[i-1], snrq_tag_st1[i-1], going_to_write_st1[i-1], valid_st1[i-1], addr_st1[i-1], wsel_st1[i-1], writeword_st1[i-1], inst_meta_st1[i-1], is_fill_st1[i-1], writedata_st1[i-1]}), - .out ({is_snp_st1[i], snrq_tag_st1[i], going_to_write_st1[i], valid_st1[i], addr_st1[i], wsel_st1[i], writeword_st1[i], inst_meta_st1[i], is_fill_st1[i], writedata_st1[i]}) + .in ({from_mrvq_st1[i-1], is_snp_st1[i-1], snrq_tag_st1[i-1], going_to_write_st1[i-1], valid_st1[i-1], addr_st1[i-1], wsel_st1[i-1], writeword_st1[i-1], inst_meta_st1[i-1], is_fill_st1[i-1], writedata_st1[i-1]}), + .out ({from_mrvq_st1[i] , is_snp_st1[i], snrq_tag_st1[i], going_to_write_st1[i], valid_st1[i], addr_st1[i], wsel_st1[i], writeword_st1[i], inst_meta_st1[i], is_fill_st1[i], writedata_st1[i]}) ); end @@ -338,10 +354,15 @@ module VX_bank #( wire [`BYTE_EN_BITS-1:0] mem_write_st1e; wire fill_saw_dirty_st1e; wire is_snp_st1e; + wire snp_to_mrvq_st1e; assign is_snp_st1e = is_snp_st1[STAGE_1_CYCLES-1]; assign {tag_st1e, mem_read_st1e, mem_write_st1e, tid_st1e} = inst_meta_st1[STAGE_1_CYCLES-1]; + assign st2_pending_hazard_st1e = (miss_add_because_miss) && ((addr_st2 == addr_st1[STAGE_1_CYCLES-1]) && !is_fill_st2); + + assign force_request_miss_st1e = (mrvq_pending_hazard_st1e || st2_pending_hazard_st1e) && valid_st1[STAGE_1_CYCLES-1] && !from_mrvq_st1[STAGE_1_CYCLES-1]; + VX_tag_data_access #( .CACHE_SIZE (CACHE_SIZE), .BANK_LINE_SIZE (BANK_LINE_SIZE), @@ -356,6 +377,8 @@ module VX_bank #( .stall (stall_bank_pipe), .stall_bank_pipe(stall_bank_pipe), + .force_request_miss_st1e(force_request_miss_st1e), + // Initial Read .readaddr_st10(addr_st1[0][`LINE_SELECT_BITS-1:0]), @@ -373,12 +396,13 @@ module VX_bank #( .is_snp_st1e (is_snp_st1e), // Read Data - .readword_st1e (readword_st1e), - .readdata_st1e (readdata_st1e), - .readtag_st1e (readtag_st1e), - .miss_st1e (miss_st1e), - .dirty_st1e (dirty_st1e), - .fill_saw_dirty_st1e(fill_saw_dirty_st1e) + .readword_st1e (readword_st1e), + .readdata_st1e (readdata_st1e), + .readtag_st1e (readtag_st1e), + .miss_st1e (miss_st1e), + .dirty_st1e (dirty_st1e), + .fill_saw_dirty_st1e(fill_saw_dirty_st1e), + .snp_to_mrvq_st1e (snp_to_mrvq_st1e) ); wire qual_valid_st1e_2 = valid_st1[STAGE_1_CYCLES-1] && !is_fill_st1[STAGE_1_CYCLES-1]; @@ -395,18 +419,22 @@ module VX_bank #( wire fill_saw_dirty_st2; wire [SNP_REQ_TAG_WIDTH-1:0] snrq_tag_st2; wire is_snp_st2; + wire snp_to_mrvq_st2; VX_generic_register #( - .N(1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `BASE_ADDR_BITS + `WORD_WIDTH + `WORD_WIDTH + `BANK_LINE_WIDTH + `TAG_SELECT_BITS + 1 + 1 + `REQ_INST_META_WIDTH + SNP_REQ_TAG_WIDTH) + .N(1+ 1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `BASE_ADDR_BITS + `WORD_WIDTH + `WORD_WIDTH + `BANK_LINE_WIDTH + `TAG_SELECT_BITS + 1 + 1 + `REQ_INST_META_WIDTH + SNP_REQ_TAG_WIDTH) ) st_1e_2 ( .clk (clk), .reset(reset), .stall(stall_bank_pipe), .flush(0), - .in ({is_snp_st1e, snrq_tag_st1[STAGE_1_CYCLES-1], fill_saw_dirty_st1e, is_fill_st1[STAGE_1_CYCLES-1] , qual_valid_st1e_2, addr_st1[STAGE_1_CYCLES-1], wsel_st1[STAGE_1_CYCLES-1], writeword_st1[STAGE_1_CYCLES-1], readword_st1e, readdata_st1e, readtag_st1e, miss_st1e, dirty_st1e, inst_meta_st1[STAGE_1_CYCLES-1]}), - .out ({is_snp_st2 , snrq_tag_st2, fill_saw_dirty_st2 , is_fill_st2 , valid_st2 , addr_st2 , wsel_st2, writeword_st2 , readword_st2 , readdata_st2 , readtag_st2 , miss_st2 , dirty_st2 , inst_meta_st2 }) + .in ({snp_to_mrvq_st1e, is_snp_st1e, snrq_tag_st1[STAGE_1_CYCLES-1], fill_saw_dirty_st1e, is_fill_st1[STAGE_1_CYCLES-1] , qual_valid_st1e_2, addr_st1[STAGE_1_CYCLES-1], wsel_st1[STAGE_1_CYCLES-1], writeword_st1[STAGE_1_CYCLES-1], readword_st1e, readdata_st1e, readtag_st1e, miss_st1e, dirty_st1e, inst_meta_st1[STAGE_1_CYCLES-1]}), + .out ({snp_to_mrvq_st2 , is_snp_st2 , snrq_tag_st2, fill_saw_dirty_st2 , is_fill_st2 , valid_st2 , addr_st2 , wsel_st2, writeword_st2 , readword_st2 , readdata_st2 , readtag_st2 , miss_st2 , dirty_st2 , inst_meta_st2 }) ); + + wire dram_fill_req_stall = (valid_st2 && miss_st2 && !invalidate_fill && ~dram_fill_req_ready); + wire cwbq_full; wire dwbq_push; wire dwbq_empty; @@ -414,21 +442,25 @@ module VX_bank #( wire srpq_full; wire invalidate_fill; + wire miss_add_is_snp; + // Enqueue to miss reserv if it's a valid miss - assign miss_add = valid_st2 - && !is_snp_st2 - && miss_st2 + assign miss_add_because_miss = valid_st2 && !is_snp_st2 && miss_st2; + assign miss_add_because_pending = snp_to_mrvq_st2; + + assign miss_add_unqual = (miss_add_because_miss || miss_add_because_pending); + assign miss_add = miss_add_unqual && !mrvq_full - && !((is_snp_st2 && valid_st2 && srpq_full) - || ((valid_st2 && !miss_st2) && cwbq_full) - || (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) - || (valid_st2 && miss_st2 && mrvq_full) - || (valid_st2 && miss_st2 && !invalidate_fill && ~dram_fill_req_ready)); + && !((snp_rsp_push_unqual && srpq_full) + || (cwbq_push_unqual && cwbq_full) + || (dwbq_push_unqual && dwbq_full) + || dram_fill_req_stall); assign miss_add_addr = addr_st2; assign miss_add_wsel = wsel_st2; assign miss_add_data = writeword_st2; assign {miss_add_tag, miss_add_mem_read, miss_add_mem_write, miss_add_tid} = inst_meta_st2; + assign miss_add_is_snp = is_snp_st2; VX_cache_miss_resrv #( .BANK_LINE_SIZE (BANK_LINE_SIZE), @@ -449,12 +481,16 @@ module VX_bank #( .miss_add_tag (miss_add_tag), .miss_add_mem_read (miss_add_mem_read), .miss_add_mem_write (miss_add_mem_write), + .miss_add_is_snp (miss_add_is_snp), .miss_resrv_full (mrvq_full), .miss_resrv_stop (mrvq_stop), // Broadcast - .is_fill_st1 (is_fill_st2), - .fill_addr_st1 (addr_st2), + .is_fill_st1 (is_fill_st1[STAGE_1_CYCLES-1]), + .fill_addr_st1 (addr_st1[STAGE_1_CYCLES-1]), + .pending_hazard (mrvq_pending_hazard_st1e), + // .is_fill_st1 (is_fill_st2), + // .fill_addr_st1 (addr_st2), // Dequeue .miss_resrv_pop (mrvq_pop), @@ -465,17 +501,19 @@ module VX_bank #( .miss_resrv_tid_st0 (mrvq_tid_st0), .miss_resrv_tag_st0 (mrvq_tag_st0), .miss_resrv_mem_read_st0 (mrvq_mem_read_st0), - .miss_resrv_mem_write_st0(mrvq_mem_write_st0) + .miss_resrv_mem_write_st0(mrvq_mem_write_st0), + .miss_resrv_is_snp_st0 (mrvq_is_snp_st0) ); + wire cwbq_push_unqual = valid_st2 && !miss_st2 && !is_fill_st2 && !is_snp_st2; // Enqueue to CWB Queue - wire cwbq_push = (valid_st2 && !miss_st2) + wire cwbq_push = cwbq_push_unqual && !cwbq_full && (miss_add_mem_write == `BYTE_EN_NO) - && !((is_snp_st2 && valid_st2 && srpq_full) - || (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) - || (valid_st2 && miss_st2 && mrvq_full) - || (valid_st2 && miss_st2 && !invalidate_fill && ~dram_fill_req_ready)); + && !((snp_rsp_push_unqual && srpq_full) + || (dwbq_push_unqual && dwbq_full) + || (miss_add_unqual && mrvq_full) + || dram_fill_req_stall); wire [`WORD_WIDTH-1:0] cwbq_data = readword_st2; wire [`REQS_BITS-1:0] cwbq_tid = miss_add_tid; @@ -503,13 +541,14 @@ module VX_bank #( .full (cwbq_full) ); + wire dwbq_push_unqual = ((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2); // Enqueue to DWB Queue - assign dwbq_push = ((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) + assign dwbq_push = dwbq_push_unqual && !dwbq_full - && !((is_snp_st2 && valid_st2 && srpq_full) - || ((valid_st2 && !miss_st2) && cwbq_full) - || (valid_st2 && miss_st2 && mrvq_full) - || (valid_st2 && miss_st2 && !invalidate_fill && ~dram_fill_req_ready)); + && !((snp_rsp_push_unqual && srpq_full) + || (cwbq_push_unqual && cwbq_full) + || (miss_add_unqual && mrvq_full) + || dram_fill_req_stall); wire [`BANK_LINE_WIDTH-1:0] dwbq_req_data = readdata_st2; wire [`LINE_ADDR_WIDTH-1:0] dwbq_req_addr = {readtag_st2, addr_st2[`LINE_SELECT_BITS-1:0]}; @@ -555,13 +594,14 @@ module VX_bank #( wire snp_rsp_push; wire srpq_empty; - assign snp_rsp_push = is_snp_st2 - && valid_st2 + wire snp_rsp_push_unqual = is_snp_st2 && valid_st2 && !snp_to_mrvq_st2; + + assign snp_rsp_push = snp_rsp_push_unqual && !srpq_full - && !(((valid_st2 && !miss_st2) && cwbq_full) - || (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) - || (valid_st2 && miss_st2 && mrvq_full) - || (valid_st2 && miss_st2 && !invalidate_fill && ~dram_fill_req_ready)); + && !((cwbq_push_unqual && cwbq_full) + || (dwbq_push_unqual && dwbq_full) + || (miss_add_unqual && mrvq_full) + || dram_fill_req_stall); assign snp_rsp_valid = !srpq_empty; @@ -579,10 +619,10 @@ module VX_bank #( .full (srpq_full) ); - assign stall_bank_pipe = (is_snp_st2 && valid_st2 && srpq_full) - || ((valid_st2 && !miss_st2) && cwbq_full) - || (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) - || (valid_st2 && miss_st2 && mrvq_full) - || (valid_st2 && miss_st2 && !invalidate_fill && ~dram_fill_req_ready); + assign stall_bank_pipe = (snp_rsp_push_unqual && srpq_full) + || (cwbq_push_unqual && cwbq_full) + || (dwbq_push_unqual && dwbq_full) + || (miss_add_unqual && mrvq_full) + || dram_fill_req_stall; endmodule : VX_bank \ No newline at end of file diff --git a/hw/rtl/cache/VX_cache_config.vh b/hw/rtl/cache/VX_cache_config.vh index f450ee84..8f79bdbf 100644 --- a/hw/rtl/cache/VX_cache_config.vh +++ b/hw/rtl/cache/VX_cache_config.vh @@ -3,8 +3,8 @@ `include "VX_define.vh" -// data tid tag read write base addr -`define MRVQ_METADATA_WIDTH (`WORD_WIDTH + `REQS_BITS + CORE_TAG_WIDTH + `BYTE_EN_BITS + `BYTE_EN_BITS + `BASE_ADDR_BITS) +// data tid tag read write base addr is_snp +`define MRVQ_METADATA_WIDTH (`WORD_WIDTH + `REQS_BITS + CORE_TAG_WIDTH + `BYTE_EN_BITS + `BYTE_EN_BITS + `BASE_ADDR_BITS + 1) // tag read write reqs `define REQ_INST_META_WIDTH (CORE_TAG_WIDTH + `BYTE_EN_BITS + `BYTE_EN_BITS + `REQS_BITS) diff --git a/hw/rtl/cache/VX_cache_miss_resrv.v b/hw/rtl/cache/VX_cache_miss_resrv.v index 6065fe67..5d1cb5fd 100644 --- a/hw/rtl/cache/VX_cache_miss_resrv.v +++ b/hw/rtl/cache/VX_cache_miss_resrv.v @@ -26,13 +26,16 @@ module VX_cache_miss_resrv #( input wire[CORE_TAG_WIDTH-1:0] miss_add_tag, input wire[`BYTE_EN_BITS-1:0] miss_add_mem_read, input wire[`BYTE_EN_BITS-1:0] miss_add_mem_write, + input wire miss_add_is_snp, output wire miss_resrv_full, output wire miss_resrv_stop, - // Broadcast Fill + // Broadcast Address input wire is_fill_st1, input wire[`LINE_ADDR_WIDTH-1:0] fill_addr_st1, + output wire pending_hazard, + // Miss dequeue input wire miss_resrv_pop, output wire miss_resrv_valid_st0, @@ -42,7 +45,8 @@ module VX_cache_miss_resrv #( output wire[`REQS_BITS-1:0] miss_resrv_tid_st0, output wire[CORE_TAG_WIDTH-1:0] miss_resrv_tag_st0, output wire[`BYTE_EN_BITS-1:0] miss_resrv_mem_read_st0, - output wire[`BYTE_EN_BITS-1:0] miss_resrv_mem_write_st0 + output wire[`BYTE_EN_BITS-1:0] miss_resrv_mem_write_st0, + output wire miss_resrv_is_snp_st0 ); reg [`MRVQ_METADATA_WIDTH-1:0] metadata_table[MRVQ_SIZE-1:0]; reg [MRVQ_SIZE-1:0][`LINE_ADDR_WIDTH-1:0] addr_table; @@ -60,19 +64,24 @@ module VX_cache_miss_resrv #( wire [`LOG2UP(MRVQ_SIZE)-1:0] enqueue_index = tail_ptr; reg [MRVQ_SIZE-1:0] make_ready; + reg [MRVQ_SIZE-1:0] valid_address_match; + genvar i; generate for (i = 0; i < MRVQ_SIZE; i++) begin - assign make_ready[i] = is_fill_st1 && valid_table[i] && (addr_table[i] == fill_addr_st1); + assign valid_address_match[i] = valid_table[i] && (addr_table[i] == fill_addr_st1); + assign make_ready[i] = is_fill_st1 && valid_address_match[i]; end endgenerate + assign pending_hazard = |(valid_address_match); + wire dequeue_possible = valid_table[head_ptr] && ready_table[head_ptr]; wire [`LOG2UP(MRVQ_SIZE)-1:0] dequeue_index = head_ptr; assign miss_resrv_valid_st0 = (MRVQ_SIZE != 2) && dequeue_possible; assign miss_resrv_addr_st0 = addr_table[dequeue_index]; - assign {miss_resrv_data_st0, miss_resrv_tid_st0, miss_resrv_tag_st0, miss_resrv_mem_read_st0, miss_resrv_mem_write_st0, miss_resrv_wsel_st0} = metadata_table[dequeue_index]; + assign {miss_resrv_data_st0, miss_resrv_tid_st0, miss_resrv_tag_st0, miss_resrv_mem_read_st0, miss_resrv_mem_write_st0, miss_resrv_wsel_st0, miss_resrv_is_snp_st0} = metadata_table[dequeue_index]; wire mrvq_push = miss_add && enqueue_possible && (MRVQ_SIZE != 2); wire mrvq_pop = miss_resrv_pop && dequeue_possible; @@ -91,7 +100,7 @@ module VX_cache_miss_resrv #( valid_table[enqueue_index] <= 1; ready_table[enqueue_index] <= 0; addr_table[enqueue_index] <= miss_add_addr; - metadata_table[enqueue_index] <= {miss_add_data, miss_add_tid, miss_add_tag, miss_add_mem_read, miss_add_mem_write, miss_add_wsel}; + metadata_table[enqueue_index] <= {miss_add_data, miss_add_tid, miss_add_tag, miss_add_mem_read, miss_add_mem_write, miss_add_wsel, miss_add_is_snp}; tail_ptr <= tail_ptr + 1; end diff --git a/hw/rtl/cache/VX_tag_data_access.v b/hw/rtl/cache/VX_tag_data_access.v index bfcec08d..0e3e605a 100644 --- a/hw/rtl/cache/VX_tag_data_access.v +++ b/hw/rtl/cache/VX_tag_data_access.v @@ -25,6 +25,8 @@ module VX_tag_data_access #( input wire is_snp_st1e, input wire stall_bank_pipe, + input wire force_request_miss_st1e, + input wire[`LINE_SELECT_BITS-1:0] readaddr_st10, input wire[`LINE_ADDR_WIDTH-1:0] writeaddr_st1e, @@ -44,7 +46,8 @@ module VX_tag_data_access #( output wire[`TAG_SELECT_BITS-1:0] readtag_st1e, output wire miss_st1e, output wire dirty_st1e, - output wire fill_saw_dirty_st1e + output wire fill_saw_dirty_st1e, + output wire snp_to_mrvq_st1e ); reg read_valid_st1c[STAGE_1_CYCLES-1:0]; @@ -229,16 +232,22 @@ module VX_tag_data_access #( // use "case equality" to handle uninitialized tag when block entry is not valid assign tags_match = ((writetag_st1e == use_read_tag_st1e) === 1'b1); - wire snoop_hit = valid_req_st1e && is_snp_st1e && use_read_valid_st1e && tags_match && use_read_dirty_st1e; - wire req_invalid = valid_req_st1e && !is_snp_st1e && !use_read_valid_st1e && !writefill_st1e; - wire req_miss = valid_req_st1e && !is_snp_st1e && use_read_valid_st1e && !writefill_st1e && !tags_match; + wire snoop_hit_no_pending = valid_req_st1e && is_snp_st1e && use_read_valid_st1e && tags_match && use_read_dirty_st1e && !force_request_miss_st1e; + wire req_invalid = valid_req_st1e && !is_snp_st1e && !use_read_valid_st1e && !writefill_st1e; + wire req_miss = valid_req_st1e && !is_snp_st1e && use_read_valid_st1e && !writefill_st1e && !tags_match; + + wire real_miss = req_invalid || req_miss || (force_request_miss_st1e && !is_snp_st1e); - assign miss_st1e = snoop_hit || req_invalid || req_miss; + assign snp_to_mrvq_st1e = valid_req_st1e && is_snp_st1e && force_request_miss_st1e; + assign miss_st1e = real_miss || snoop_hit_no_pending; assign dirty_st1e = valid_req_st1e && use_read_valid_st1e && use_read_dirty_st1e; assign readdata_st1e = use_read_data_st1e; assign readtag_st1e = use_read_tag_st1e; assign fill_sent = miss_st1e; assign fill_saw_dirty_st1e = real_writefill && dirty_st1e; - assign invalidate_line = snoop_hit; + assign invalidate_line = snoop_hit_no_pending; + +endmodule + + -endmodule \ No newline at end of file