pipeline optimization: fixed GPR fanout delay to execute units
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@@ -29,8 +29,8 @@ module VX_alu_unit #(
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wire [`NUM_THREADS-1:0][31:0] alu_in1 = alu_req_if.rs1_data;
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wire [`NUM_THREADS-1:0][31:0] alu_in2 = alu_req_if.rs2_data;
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wire [`NUM_THREADS-1:0][31:0] alu_in1_PC = alu_req_if.rs1_is_PC ? {`NUM_THREADS{alu_req_if.PC}} : alu_in1;
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wire [`NUM_THREADS-1:0][31:0] alu_in2_imm = alu_req_if.rs2_is_imm ? {`NUM_THREADS{alu_req_if.imm}} : alu_in2;
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wire [`NUM_THREADS-1:0][31:0] alu_in1_PC = alu_req_if.rs1_is_PC ? {`NUM_THREADS{alu_req_if.PC}} : alu_in1;
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wire [`NUM_THREADS-1:0][31:0] alu_in2_imm = alu_req_if.rs2_is_imm ? {`NUM_THREADS{alu_req_if.imm}} : alu_in2;
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wire [`NUM_THREADS-1:0][31:0] alu_in2_less = (alu_req_if.rs2_is_imm && !is_br_op) ? {`NUM_THREADS{alu_req_if.imm}} : alu_in2;
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for (genvar i = 0; i < `NUM_THREADS; i++) begin
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@@ -40,7 +40,7 @@ module VX_alu_unit #(
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end
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for (genvar i = 0; i < `NUM_THREADS; i++) begin
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wire [32:0] sub_in1 = {alu_signed & alu_in1[i][31], alu_in1[i]};
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wire [32:0] sub_in1 = {alu_signed & alu_in1[i][31], alu_in1[i]};
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wire [32:0] sub_in2 = {alu_signed & alu_in2_less[i][31], alu_in2_less[i]};
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always @(*) begin
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sub_result[i] = $signed(sub_in1) - $signed(sub_in2);
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