pipeline optimization: fixed GPR fanout delay to execute units
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@@ -17,24 +17,26 @@ module VX_skid_buffer #(
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reg valid_out_r;
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reg use_buffer;
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wire push = valid_in && ready_in;
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always @(posedge clk) begin
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if (reset) begin
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data_out_r <= 0;
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buffer <= 0;
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use_buffer <= 0;
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valid_out_r <= 0;
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end else begin
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if (valid_in && ready_in && valid_out && !ready_out) begin
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assert(!use_buffer);
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use_buffer <= 1;
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end
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end else begin
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if (ready_out) begin
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use_buffer <= 0;
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end
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if (valid_in && ready_in) begin
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if (push) begin
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buffer <= data_in;
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if (valid_out_r && !ready_out) begin
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assert(!use_buffer);
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use_buffer <= 1;
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end
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end
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if (!valid_out || ready_out) begin
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if (!valid_out_r || ready_out) begin
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valid_out_r <= valid_in || use_buffer;
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data_out_r <= use_buffer ? buffer : data_in;
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end
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