From b150327ca97a2ea32eded5509ac8372625a6e7a9 Mon Sep 17 00:00:00 2001 From: felsabbagh3 Date: Tue, 3 Mar 2020 16:57:05 -0800 Subject: [PATCH] Before fixing miss rsrv for ST->LD sequences --- rtl/VX_cache/VX_bank.v | 80 ++++++++++++++++++++++------ rtl/VX_cache/VX_cache.v | 2 + rtl/VX_cache/VX_cache_config.v | 6 +-- rtl/VX_cache/VX_cache_dram_req_arb.v | 1 + rtl/VX_cache/VX_tag_data_access.v | 26 +++++++++ rtl/VX_cache/VX_tag_data_structure.v | 15 ++++++ 6 files changed, 110 insertions(+), 20 deletions(-) create mode 100644 rtl/VX_cache/VX_tag_data_access.v create mode 100644 rtl/VX_cache/VX_tag_data_structure.v diff --git a/rtl/VX_cache/VX_bank.v b/rtl/VX_cache/VX_bank.v index f4232388..cf4e0e8a 100644 --- a/rtl/VX_cache/VX_bank.v +++ b/rtl/VX_cache/VX_bank.v @@ -43,7 +43,7 @@ module VX_bank ( ); - wire dfpq_pop; // Use this + wire dfpq_pop; wire dfpq_empty; wire dfpq_full; wire[31:0] dfpq_addr_st0; @@ -63,7 +63,7 @@ module VX_bank ( ); - wire reqq_pop; // Use this + wire reqq_pop; wire reqq_push; wire reqq_empty; wire reqq_req_st0; @@ -107,7 +107,7 @@ module VX_bank ( .reqq_full (reqq_full) ); - wire mrvq_pop; // Use this + wire mrvq_pop; wire mrvq_full; wire mrvq_valid_st0; wire[`vx_clog2(`NUMBER_REQUESTS)-1:0] mrvq_tid_st0; @@ -136,7 +136,7 @@ module VX_bank ( // Broadcast .is_fill_st1 (is_fill_st1), - .fill_addr_st1 (addr_st1), + .fill_addr_st1 (addr_st1[0]), // Dequeue .miss_resrv_pop (mrvq_pop), @@ -170,12 +170,12 @@ module VX_bank ( wire [`BANK_LINE_SIZE_RNG][31:0] qual_writedata_st0; wire [`REQ_INST_META_SIZE-1:0] qual_inst_meta_st0; - wire is_fill_st1; - wire valid_st1; - wire [31:0] addr_st1; - wire [31:0] writeword_st1; - wire [`BANK_LINE_SIZE_RNG][31:0] writedata_st1; - wire [`REQ_INST_META_SIZE-1:0] inst_meta_st1; + wire valid_st1[`STAGE_1_CYCLES-1:0]; + wire [31:0] addr_st1[`STAGE_1_CYCLES-1:0]; + wire [31:0] writeword_st1[`STAGE_1_CYCLES-1:0]; + wire [`REQ_INST_META_SIZE-1:0] inst_meta_st1[`STAGE_1_CYCLES-1:0]; + wire is_fill_st1[`STAGE_1_CYCLES-1:0]; + wire [`BANK_LINE_SIZE_RNG][31:0] writedata_st1[`STAGE_1_CYCLES-1:0]; assign qual_is_fill_st0 = dfpq_pop; assign qual_valid_st0 = dfpq_pop || mrvq_pop || reqq_pop; @@ -195,15 +195,61 @@ module VX_bank ( reqq_pop ? {reqq_rd_st0, reqq_wb_st0, reqq_warp_num_st0, reqq_mem_read_st0, reqq_mem_write_st0, reqq_tid_st0} : 0; - VX_generic_register #(.N(1)) s0_1 ( - .clk (clk), - .reset(reset), - .stall(stall_st1), - .flush(0), - .in ({qual_is_fill_st0, qual_valid_st0, qual_addr_st0, qual_writeword_st0, qual_writedata_st0, qual_inst_meta_st0}), - .out ({is_fill_st1 , valid_st1 , addr_st1 , writeword_st1 , writedata_st1 , inst_meta_st1 }) + VX_generic_register #(.N( 1 + 32 + 32 + `REQ_INST_META_SIZE + (`BANK_LINE_SIZE_RNG*32) + 1)) s0_1_c0 ( + .clk (clk), + .reset(reset), + .stall(stall_st1), + .flush(0), + .in ({qual_valid_st0, qual_addr_st0, qual_writeword_st0, qual_inst_meta_st0, qual_is_fill_st0, qual_writedata_st0}), + .out ({valid_st1[0] , addr_st1[0] , writeword_st1[0] , inst_meta_st1[0] , is_fill_st1[0] , writedata_st1[0]}) + ); + + genvar curr_stage; + generate + for (curr_stage = 1; curr_stage < `STAGE_1_CYCLES; curr_stage = curr_stage + 1) begin + VX_generic_register #(.N( 1 + 32 + 32 + `REQ_INST_META_SIZE + (`BANK_LINE_SIZE_RNG*32) + 1)) s0_1_cc ( + .clk (clk), + .reset(reset), + .stall(stall_st1), + .flush(is_fill_st1), + .in ({valid_st1[curr_stage-1], addr_st1[curr_stage-1], writeword_st1[curr_stage-1], inst_meta_st1[curr_stage-1], is_fill_st1[curr_stage-1] , writedata_st1[curr_stage-1]}), + .out ({valid_st1[curr_stage] , addr_st1[curr_stage] , writeword_st1[curr_stage] , inst_meta_st1[curr_stage] , is_fill_st1[curr_stage] , writedata_st1[curr_stage] }) + ); + end + endgenerate + + + wire[31:0] readword_st1e; + wire[`BANK_LINE_SIZE_RNG][31:0] readdata_st1e; + wire miss_st1e; + + VX_tag_data_access VX_tag_data_access( + .clk (clk), + .reset (reset), + .valid_st10 (valid_st10), + + // Read start + .readaddr_st10 (addr_st1[0]), + + // Write stuff + .writeaddr_st1e(addr_st1[`STAGE_1_CYCLES-1]), + .writeword_st1e(writeword_st1[`STAGE_1_CYCLES-1]), + .mem_write_st1e(mem_write_st1e), // TODO + + + // Fill info + .is_fill_st1e (is_fill_st1[`STAGE_1_CYCLES-1]), + .filldata_st1e (writedata_st1[`STAGE_1_CYCLES-1]), + + // Read stuff + result + .mem_read_st1e (mem_read_st1e), // TODO + .readword_st1e (readword_st1e), + .readdata_st1e (readdata_st1e), + .miss_st1e (miss_st1e), ); + + endmodule diff --git a/rtl/VX_cache/VX_cache.v b/rtl/VX_cache/VX_cache.v index 8ed074f8..b0e139d9 100644 --- a/rtl/VX_cache/VX_cache.v +++ b/rtl/VX_cache/VX_cache.v @@ -1,5 +1,7 @@ `include "VX_cache_config.v" +`include "VX_cache_config.v" + module VX_cache ( input wire clk, diff --git a/rtl/VX_cache/VX_cache_config.v b/rtl/VX_cache/VX_cache_config.v index 10b1ddd9..fbec7e5c 100644 --- a/rtl/VX_cache/VX_cache_config.v +++ b/rtl/VX_cache/VX_cache_config.v @@ -16,8 +16,8 @@ `define WORD_SIZE_BYTES 4 // Number of Word requests per cycle {1, 2, 4, 8, ...} `define NUMBER_REQUESTS `NT - // Number of cycles to complete stage 2 (read from memory) - `define STAGE_2_CYCLES 1 + // Number of cycles to complete stage 1 (read from memory) + `define STAGE_1_CYCLES 2 // Queues feeding into banks Knobs {1, 2, 4, 8, ...} @@ -94,7 +94,7 @@ `define OFFSET_SIZE_END 1 `define OFFSET_ADDR_START 0 `define OFFSET_ADDR_END 1 -`define OFFSET_ADDR_RNG `OFFSET_ADDR_START:`OFFSET_ADDR_END +`define OFFSET_ADDR_RNG `OFFSET_ADDR_END:`OFFSET_ADDR_START `define OFFSET_SIZE_RNG `OFFSET_SIZE_END:0 `define WORD_SELECT_NUM_BITS `vx_clog2(`BANK_LINE_SIZE_WORDS) diff --git a/rtl/VX_cache/VX_cache_dram_req_arb.v b/rtl/VX_cache/VX_cache_dram_req_arb.v index eebb5b3e..9c54c94e 100644 --- a/rtl/VX_cache/VX_cache_dram_req_arb.v +++ b/rtl/VX_cache/VX_cache_dram_req_arb.v @@ -63,6 +63,7 @@ module VX_cache_dram_req_arb ( assign dram_req_write = dwb_valid; assign dram_req_read = dfqq_req && !dwb_valid; assign dram_req_addr = dwb_valid ? per_bank_dram_wb_req_addr[dwb_bank] : dfqq_req_addr; + assign dram_req_size = `BANK_LINE_SIZE_BYTES; assign dram_req_data = dwb_valid ? per_bank_dram_wb_req_data[dwb_bank] : 0; endmodule \ No newline at end of file diff --git a/rtl/VX_cache/VX_tag_data_access.v b/rtl/VX_cache/VX_tag_data_access.v new file mode 100644 index 00000000..47d513d0 --- /dev/null +++ b/rtl/VX_cache/VX_tag_data_access.v @@ -0,0 +1,26 @@ +`include "VX_cache_config.v" + +module VX_tag_data_access ( + input wire clk, + input wire reset, + + input wire valid_st10, + input wire is_fill_st10, + input wire[31:0] readaddr_st10, + input wire[`BANK_LINE_SIZE_RNG][31:0] filldata_st10, + + input wire[31:0] writeaddr_st1e, + input wire[31:0] writeword_st1e, + input wire[2:0] mem_write_st1e, + input wire[2:0] mem_read_st1e, + + output wire[31:0] readword_st1e, + output wire[`BANK_LINE_SIZE_RNG][31:0] readdata_st1e, + output wire miss_st1e + +); + + + reg[`BANK_LINE_SIZE_RNG][31:0] readdata_st[`STAGE_1_CYCLES-1:0]; + +endmodule \ No newline at end of file diff --git a/rtl/VX_cache/VX_tag_data_structure.v b/rtl/VX_cache/VX_tag_data_structure.v new file mode 100644 index 00000000..4877a61f --- /dev/null +++ b/rtl/VX_cache/VX_tag_data_structure.v @@ -0,0 +1,15 @@ +module VX_tag_data_structure ( + input wire clk, + + input wire[31:0] readaddr, + output wire[`BANK_LINE_SIZE_RNG][31:0] readdata, + + input wire[`BANK_LINE_SIZE_RNG][3] writeenable, + input wire[31:0] writeaddr, + input wire[`BANK_LINE_SIZE_RNG][31:0] writedata + +); + +endmodule + +// OFFSET_SIZE_RNG \ No newline at end of file