diff --git a/rtl/VX_cache/VX_cache_req_queue.v b/rtl/VX_cache/VX_cache_req_queue.v
index 5938d349..e4b20e80 100644
--- a/rtl/VX_cache/VX_cache_req_queue.v
+++ b/rtl/VX_cache/VX_cache_req_queue.v
@@ -166,9 +166,9 @@ module VX_cache_req_queue
 
 
 	always @(*) begin
-		assign updated_valids = qual_valids;
+		updated_valids = qual_valids;
 		if (qual_has_request) begin
-			assign updated_valids[qual_request_index] = 0;
+			updated_valids[qual_request_index] = 0;
 		end
 	end
 
diff --git a/rtl/VX_cache/VX_snp_fwd_arb.v b/rtl/VX_cache/VX_snp_fwd_arb.v
index 7f2d3e64..354e1fdd 100644
--- a/rtl/VX_cache/VX_snp_fwd_arb.v
+++ b/rtl/VX_cache/VX_snp_fwd_arb.v
@@ -30,7 +30,7 @@ module VX_snp_fwd_arb
 	assign snp_fwd_addr  = per_bank_snp_fwd_addr[fsq_bank];
 
 	always @(*) begin
-		assign per_bank_snp_fwd_pop = 0;
+		per_bank_snp_fwd_pop = 0;
 		if (fsq_valid) begin
 			per_bank_snp_fwd_pop[fsq_bank] = 1;
 		end
diff --git a/rtl/VX_generic_queue_ll.v b/rtl/VX_generic_queue_ll.v
index dfe7828b..40b4d8c7 100644
--- a/rtl/VX_generic_queue_ll.v
+++ b/rtl/VX_generic_queue_ll.v
@@ -24,7 +24,8 @@ module VX_generic_queue_ll
         assign full     = 0;
     end else begin
 
-        reg[DATAW-1:0]          data[SIZE-1:0], curr_r, head_r;
+        (* syn_ramstyle = "mlab" *) reg[DATAW-1:0]          data[SIZE-1:0];
+        reg[DATAW-1:0]          curr_r, head_r;
         reg[$clog2(SIZE+1)-1:0] size_r;
         reg[$clog2(SIZE)-1:0]   wr_ctr_r;
         reg[$clog2(SIZE)-1:0]   rd_ptr_r, rd_next_ptr_r;