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rename use_imm and use_PC

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This commit is contained in:
Blaise Tine
2021-03-01 00:38:46 -08:00
parent 013dab4aeb
commit b441870789
9 changed files with 25 additions and 25 deletions
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6
hw/rtl/VX_alu_unit.v
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@@ -32,9 +32,9 @@ module VX_alu_unit #(
wire [`NUM_THREADS-1:0][31:0] alu_in1 = alu_req_if.rs1_data; wire [`NUM_THREADS-1:0][31:0] alu_in1 = alu_req_if.rs1_data;
wire [`NUM_THREADS-1:0][31:0] alu_in2 = alu_req_if.rs2_data; wire [`NUM_THREADS-1:0][31:0] alu_in2 = alu_req_if.rs2_data;
wire [`NUM_THREADS-1:0][31:0] alu_in1_PC = alu_req_if.rs1_is_PC ? {`NUM_THREADS{alu_req_if.PC}} : alu_in1; wire [`NUM_THREADS-1:0][31:0] alu_in1_PC = alu_req_if.use_PC ? {`NUM_THREADS{alu_req_if.PC}} : alu_in1;
wire [`NUM_THREADS-1:0][31:0] alu_in2_imm = alu_req_if.rs2_is_imm ? {`NUM_THREADS{alu_req_if.imm}} : alu_in2; wire [`NUM_THREADS-1:0][31:0] alu_in2_imm = alu_req_if.use_imm ? {`NUM_THREADS{alu_req_if.imm}} : alu_in2;
wire [`NUM_THREADS-1:0][31:0] alu_in2_less = (alu_req_if.rs2_is_imm && !is_br_op) ? {`NUM_THREADS{alu_req_if.imm}} : alu_in2; wire [`NUM_THREADS-1:0][31:0] alu_in2_less = (alu_req_if.use_imm && !is_br_op) ? {`NUM_THREADS{alu_req_if.imm}} : alu_in2;
for (genvar i = 0; i < `NUM_THREADS; i++) begin for (genvar i = 0; i < `NUM_THREADS; i++) begin
assign add_result[i] = alu_in1_PC[i] + alu_in2_imm[i]; assign add_result[i] = alu_in1_PC[i] + alu_in2_imm[i];

2
hw/rtl/VX_csr_io_arb.v
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@@ -24,7 +24,7 @@ module VX_csr_io_arb (
`UNUSED_VAR (clk) `UNUSED_VAR (clk)
`UNUSED_VAR (reset) `UNUSED_VAR (reset)
wire [31:0] csr_core_req_mask = csr_core_req_if.rs2_is_imm ? 32'(csr_core_req_if.rs1) : csr_core_req_if.rs1_data; wire [31:0] csr_core_req_mask = csr_core_req_if.use_imm ? 32'(csr_core_req_if.rs1) : csr_core_req_if.rs1_data;
// requests // requests
assign csr_pipe_req_if.valid = csr_core_req_if.valid || csr_io_req_if.valid; assign csr_pipe_req_if.valid = csr_core_req_if.valid || csr_io_req_if.valid;

6
hw/rtl/VX_decode.v
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@@ -392,8 +392,8 @@ module VX_decode #(
`endif `endif
assign decode_if.imm = imm; assign decode_if.imm = imm;
assign decode_if.rs1_is_PC = use_PC; assign decode_if.use_PC = use_PC;
assign decode_if.rs2_is_imm = use_imm; assign decode_if.use_imm = use_imm;
assign decode_if.used_regs = (`NUM_REGS'(use_rd) << decode_if.rd) assign decode_if.used_regs = (`NUM_REGS'(use_rd) << decode_if.rd)
| (`NUM_REGS'(use_rs1) << decode_if.rs1) | (`NUM_REGS'(use_rs1) << decode_if.rs1)
@@ -419,7 +419,7 @@ module VX_decode #(
print_ex_type(decode_if.ex_type); print_ex_type(decode_if.ex_type);
$write(", op="); $write(", op=");
print_ex_op(decode_if.ex_type, decode_if.op_type, decode_if.op_mod); print_ex_op(decode_if.ex_type, decode_if.op_type, decode_if.op_mod);
$write(", mod=%0d, tmask=%b, wb=%b, rd=%0d, rs1=%0d, rs2=%0d, rs3=%0d, imm=%0h, use_pc=%b, use_imm=%b, use_regs=%b\n", decode_if.op_mod, decode_if.tmask, decode_if.wb, decode_if.rd, decode_if.rs1, decode_if.rs2, decode_if.rs3, decode_if.imm, decode_if.rs1_is_PC, decode_if.rs2_is_imm, decode_if.used_regs); $write(", mod=%0d, tmask=%b, wb=%b, rd=%0d, rs1=%0d, rs2=%0d, rs3=%0d, imm=%0h, use_pc=%b, use_imm=%b, use_regs=%b\n", decode_if.op_mod, decode_if.tmask, decode_if.wb, decode_if.rd, decode_if.rs1, decode_if.rs2, decode_if.rs3, decode_if.imm, decode_if.use_PC, decode_if.use_imm, decode_if.used_regs);
end end
end end
`endif `endif

8
hw/rtl/VX_ibuffer.v
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@@ -185,8 +185,8 @@ module VX_ibuffer #(
ibuf_enq_if.rs2, ibuf_enq_if.rs2,
ibuf_enq_if.rs3, ibuf_enq_if.rs3,
ibuf_enq_if.imm, ibuf_enq_if.imm,
ibuf_enq_if.rs1_is_PC, ibuf_enq_if.use_PC,
ibuf_enq_if.rs2_is_imm, ibuf_enq_if.use_imm,
ibuf_enq_if.used_regs}; ibuf_enq_if.used_regs};
assign ibuf_deq_if.valid = deq_valid; assign ibuf_deq_if.valid = deq_valid;
@@ -202,8 +202,8 @@ module VX_ibuffer #(
ibuf_deq_if.rs2, ibuf_deq_if.rs2,
ibuf_deq_if.rs3, ibuf_deq_if.rs3,
ibuf_deq_if.imm, ibuf_deq_if.imm,
ibuf_deq_if.rs1_is_PC, ibuf_deq_if.use_PC,
ibuf_deq_if.rs2_is_imm, ibuf_deq_if.use_imm,
ibuf_deq_if.used_regs} = deq_instr; ibuf_deq_if.used_regs} = deq_instr;
endmodule endmodule

8
hw/rtl/VX_instr_demux.v
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@@ -44,8 +44,8 @@ module VX_instr_demux (
.reset (reset), .reset (reset),
.valid_in (alu_req_valid), .valid_in (alu_req_valid),
.ready_in (alu_req_ready), .ready_in (alu_req_ready),
.data_in ({execute_if.wid, execute_if.tmask, execute_if.PC, next_PC, `ALU_OP(execute_if.op_type), execute_if.op_mod, execute_if.imm, execute_if.rs1_is_PC, execute_if.rs2_is_imm, execute_if.rd, execute_if.wb, tid, gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data}), .data_in ({execute_if.wid, execute_if.tmask, execute_if.PC, next_PC, `ALU_OP(execute_if.op_type), execute_if.op_mod, execute_if.imm, execute_if.use_PC, execute_if.use_imm, execute_if.rd, execute_if.wb, tid, gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data}),
.data_out ({alu_req_if.wid, alu_req_if.tmask, alu_req_if.PC, alu_req_if.next_PC, alu_req_if.op_type, alu_req_if.op_mod, alu_req_if.imm, alu_req_if.rs1_is_PC, alu_req_if.rs2_is_imm, alu_req_if.rd, alu_req_if.wb, alu_req_if.tid, alu_req_if.rs1_data, alu_req_if.rs2_data}), .data_out ({alu_req_if.wid, alu_req_if.tmask, alu_req_if.PC, alu_req_if.next_PC, alu_req_if.op_type, alu_req_if.op_mod, alu_req_if.imm, alu_req_if.use_PC, alu_req_if.use_imm, alu_req_if.rd, alu_req_if.wb, alu_req_if.tid, alu_req_if.rs1_data, alu_req_if.rs2_data}),
.valid_out (alu_req_if.valid), .valid_out (alu_req_if.valid),
.ready_out (alu_req_if.ready) .ready_out (alu_req_if.ready)
); );
@@ -78,8 +78,8 @@ module VX_instr_demux (
.reset (reset), .reset (reset),
.valid_in (csr_req_valid), .valid_in (csr_req_valid),
.ready_in (csr_req_ready), .ready_in (csr_req_ready),
.data_in ({execute_if.wid, execute_if.tmask, execute_if.PC, `CSR_OP(execute_if.op_type), execute_if.imm[`CSR_ADDR_BITS-1:0], execute_if.rd, execute_if.wb, execute_if.rs2_is_imm, execute_if.rs1, gpr_rsp_if.rs1_data[0]}), .data_in ({execute_if.wid, execute_if.tmask, execute_if.PC, `CSR_OP(execute_if.op_type), execute_if.imm[`CSR_ADDR_BITS-1:0], execute_if.rd, execute_if.wb, execute_if.use_imm, execute_if.rs1, gpr_rsp_if.rs1_data[0]}),
.data_out ({csr_req_if.wid, csr_req_if.tmask, csr_req_if.PC, csr_req_if.op_type, csr_req_if.csr_addr, csr_req_if.rd, csr_req_if.wb, csr_req_if.rs2_is_imm, csr_req_if.rs1, csr_req_if.rs1_data}), .data_out ({csr_req_if.wid, csr_req_if.tmask, csr_req_if.PC, csr_req_if.op_type, csr_req_if.csr_addr, csr_req_if.rd, csr_req_if.wb, csr_req_if.use_imm, csr_req_if.rs1, csr_req_if.rs1_data}),
.valid_out (csr_req_if.valid), .valid_out (csr_req_if.valid),
.ready_out (csr_req_if.ready) .ready_out (csr_req_if.ready)
); );

8
hw/rtl/VX_issue.v
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@@ -74,8 +74,8 @@ module VX_issue #(
assign execute_if.rd = ibuf_deq_if.rd; assign execute_if.rd = ibuf_deq_if.rd;
assign execute_if.rs1 = ibuf_deq_if.rs1; assign execute_if.rs1 = ibuf_deq_if.rs1;
assign execute_if.imm = ibuf_deq_if.imm; assign execute_if.imm = ibuf_deq_if.imm;
assign execute_if.rs1_is_PC = ibuf_deq_if.rs1_is_PC; assign execute_if.use_PC = ibuf_deq_if.use_PC;
assign execute_if.rs2_is_imm= ibuf_deq_if.rs2_is_imm; assign execute_if.use_imm = ibuf_deq_if.use_imm;
VX_instr_demux instr_demux ( VX_instr_demux instr_demux (
.clk (clk), .clk (clk),
@@ -105,8 +105,8 @@ module VX_issue #(
`SCOPE_ASSIGN (issue_rs2, ibuf_deq_if.rs2); `SCOPE_ASSIGN (issue_rs2, ibuf_deq_if.rs2);
`SCOPE_ASSIGN (issue_rs3, ibuf_deq_if.rs3); `SCOPE_ASSIGN (issue_rs3, ibuf_deq_if.rs3);
`SCOPE_ASSIGN (issue_imm, ibuf_deq_if.imm); `SCOPE_ASSIGN (issue_imm, ibuf_deq_if.imm);
`SCOPE_ASSIGN (issue_rs1_is_pc, ibuf_deq_if.rs1_is_PC); `SCOPE_ASSIGN (issue_rs1_is_pc, ibuf_deq_if.use_PC);
`SCOPE_ASSIGN (issue_rs2_is_imm, ibuf_deq_if.rs2_is_imm); `SCOPE_ASSIGN (issue_use_imm, ibuf_deq_if.use_imm);
`SCOPE_ASSIGN (scoreboard_delay, scoreboard_delay); `SCOPE_ASSIGN (scoreboard_delay, scoreboard_delay);
`SCOPE_ASSIGN (execute_delay, ~execute_if.ready); `SCOPE_ASSIGN (execute_delay, ~execute_if.ready);
`SCOPE_ASSIGN (gpr_rsp_a, gpr_rsp_if.rs1_data); `SCOPE_ASSIGN (gpr_rsp_a, gpr_rsp_if.rs1_data);

4
hw/rtl/interfaces/VX_alu_req_if.v
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@@ -12,8 +12,8 @@ interface VX_alu_req_if ();
wire [31:0] next_PC; wire [31:0] next_PC;
wire [`ALU_BITS-1:0] op_type; wire [`ALU_BITS-1:0] op_type;
wire [`MOD_BITS-1:0] op_mod; wire [`MOD_BITS-1:0] op_mod;
wire rs1_is_PC; wire use_PC;
wire rs2_is_imm; wire use_imm;
wire [31:0] imm; wire [31:0] imm;
wire [`NT_BITS-1:0] tid; wire [`NT_BITS-1:0] tid;
wire [`NUM_THREADS-1:0][31:0] rs1_data; wire [`NUM_THREADS-1:0][31:0] rs1_data;

2
hw/rtl/interfaces/VX_csr_req_if.v
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@@ -12,7 +12,7 @@ interface VX_csr_req_if ();
wire [`CSR_BITS-1:0] op_type; wire [`CSR_BITS-1:0] op_type;
wire [`CSR_ADDR_BITS-1:0] csr_addr; wire [`CSR_ADDR_BITS-1:0] csr_addr;
wire [31:0] rs1_data; wire [31:0] rs1_data;
wire rs2_is_imm; wire use_imm;
wire [`NR_BITS-1:0] rs1; wire [`NR_BITS-1:0] rs1;
wire [`NR_BITS-1:0] rd; wire [`NR_BITS-1:0] rd;
wire wb; wire wb;

4
hw/rtl/interfaces/VX_decode_if.v
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@@ -18,8 +18,8 @@ interface VX_decode_if ();
wire [`NR_BITS-1:0] rs2; wire [`NR_BITS-1:0] rs2;
wire [`NR_BITS-1:0] rs3; wire [`NR_BITS-1:0] rs3;
wire [31:0] imm; wire [31:0] imm;
wire rs1_is_PC; wire use_PC;
wire rs2_is_imm; wire use_imm;
wire [`NUM_REGS-1:0] used_regs; wire [`NUM_REGS-1:0] used_regs;
wire ready; wire ready;