wu-arch/vortex
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Merge remote-tracking branch 'upstream/master' into vortex2

Browse Source
This commit is contained in:
Hansung Kim
2024-03-07 14:45:48 -08:00
parent e7b0a149c7 5f2b10b8a6
commit b63333a4ec
38 changed files with 553 additions and 390 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
sim/simx/cluster.cpp
View File

@@ -62,10 +62,10 @@ Cluster::Cluster(const SimContext& ctx,
snprintf(sname, 100, "cluster%d-l2cache", cluster_id);
l2cache_ = CacheSim::Create(sname, CacheSim::Config{
!L2_ENABLED,
log2ceil(L2_CACHE_SIZE), // C
log2ceil(MEM_BLOCK_SIZE), // L
log2ceil(L2_NUM_WAYS), // W
0, // A
log2ceil(L2_CACHE_SIZE),// C
log2ceil(MEM_BLOCK_SIZE),// L
log2ceil(L1_LINE_SIZE), // W
log2ceil(L2_NUM_WAYS), // A
log2ceil(L2_NUM_BANKS), // B
XLEN, // address bits
1, // number of ports

2
sim/simx/core.cpp
View File

@@ -210,7 +210,7 @@ void Core::schedule() {
void Core::fetch() {
perf_stats_.ifetch_latency += pending_ifetches_;
// handle icache reponse
// handle icache response
auto& icache_rsp_port = icache_rsp_ports.at(0);
if (!icache_rsp_port.empty()){
auto& mem_rsp = icache_rsp_port.front();

6
sim/simx/exe_unit.cpp
View File

@@ -207,7 +207,7 @@ void LsuUnit::tick() {
for (uint32_t t = 1; t < num_lanes_; ++t) {
if (!trace->tmask.test(t0 + t))
continue;
auto mem_addr = trace_data->mem_addrs.at(t).addr & ~addr_mask;
auto mem_addr = trace_data->mem_addrs.at(t + t0).addr & ~addr_mask;
matches += (addr0 == mem_addr);
}
#ifdef LSU_DUP_ENABLE
@@ -229,7 +229,7 @@ void LsuUnit::tick() {
continue;
auto& dcache_req_port = core_->smem_demuxs_.at(t)->ReqIn;
auto mem_addr = trace_data->mem_addrs.at(t);
auto mem_addr = trace_data->mem_addrs.at(t + t0);
auto type = core_->get_addr_type(mem_addr.addr);
MemReq mem_req;
@@ -324,4 +324,4 @@ void SfuUnit::tick() {
break; // single block
}
++input_idx_;
}
}

6
sim/simx/execute.cpp
View File

@@ -339,7 +339,7 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
break;
}
case 1: {
// RV64I: SLLI
// RV32I: SLLI
rddata[t].i = rsdata[t][0].i << immsrc;
break;
}
@@ -360,11 +360,11 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
}
case 5: {
if (func7) {
// RV64I: SRAI
// RV32I: SRAI
Word result = rsdata[t][0].i >> immsrc;
rddata[t].i = result;
} else {
// RV64I: SRLI
// RV32I: SRLI
Word result = rsdata[t][0].u >> immsrc;
rddata[t].i = result;
}

2
sim/simx/main.cpp
View File

@@ -34,7 +34,7 @@ static void show_usage() {
uint32_t num_threads = NUM_THREADS;
uint32_t num_warps = NUM_WARPS;
uint32_t num_cores = NUM_CORES;
bool showStats = false;;
bool showStats = false;
bool riscv_test = false;
const char* program = nullptr;

6
sim/simx/processor.cpp
View File

@@ -33,8 +33,8 @@ ProcessorImpl::ProcessorImpl(const Arch& arch)
!L3_ENABLED,
log2ceil(L3_CACHE_SIZE), // C
log2ceil(MEM_BLOCK_SIZE), // L
log2ceil(L3_NUM_WAYS), // W
0, // A
log2ceil(L2_LINE_SIZE), // W
log2ceil(L3_NUM_WAYS), // A
log2ceil(L3_NUM_BANKS), // B
XLEN, // address bits
1, // number of ports
@@ -58,7 +58,7 @@ ProcessorImpl::ProcessorImpl(const Arch& arch)
l3cache_->CoreRspPorts.at(i).bind(&clusters_.at(i)->mem_rsp_port);
}
// set up memory perf recording
// set up memory profiling
memsim_->MemReqPort.tx_callback([&](const MemReq& req, uint64_t cycle){
__unused (cycle);
perf_mem_reads_ += !req.write;

2
sim/simx/socket.cpp
View File

@@ -44,7 +44,7 @@ Socket::Socket(const SimContext& ctx,
XLEN, // address bits
1, // number of ports
1, // number of inputs
true, // write-through
false, // write-through
false, // write response
(uint8_t)arch.num_warps(), // mshr
2, // pipeline latency