diff --git a/hw/rtl/cache/VX_bank.v b/hw/rtl/cache/VX_bank.v index dab4e612..da525ac1 100644 --- a/hw/rtl/cache/VX_bank.v +++ b/hw/rtl/cache/VX_bank.v @@ -82,14 +82,14 @@ module VX_bank #( // Dram Fill Response input wire dram_fill_rsp_valid, - input wire [`BANK_LINE_WORDS-1:0][`WORD_WIDTH-1:0] dram_fill_rsp_data, + input wire [`BANK_LINE_WIDTH-1:0] dram_fill_rsp_data, input wire [`LINE_ADDR_WIDTH-1:0] dram_fill_rsp_addr, output wire dram_fill_rsp_ready, // Dram WB Requests output wire dram_wb_req_valid, output wire [`LINE_ADDR_WIDTH-1:0] dram_wb_req_addr, - output wire [`BANK_LINE_WORDS-1:0][`WORD_WIDTH-1:0] dram_wb_req_data, + output wire [`BANK_LINE_WIDTH-1:0] dram_wb_req_data, input wire dram_wb_req_pop, // Snp Request @@ -121,7 +121,7 @@ module VX_bank #( assign snrq_valid_st0 = !snrq_empty; VX_generic_queue #( - .DATAW($bits(snp_req_addr)), + .DATAW(`LINE_ADDR_WIDTH), .SIZE(SNRQ_SIZE) ) snr_queue ( .clk (clk), @@ -138,12 +138,12 @@ module VX_bank #( wire dfpq_empty; wire dfpq_full; wire [`LINE_ADDR_WIDTH-1:0] dfpq_addr_st0; - wire [`BANK_LINE_WORDS-1:0][`WORD_WIDTH-1:0] dfpq_filldata_st0; + wire [`BANK_LINE_WIDTH-1:0] dfpq_filldata_st0; assign dram_fill_rsp_ready = !dfpq_full; VX_generic_queue #( - .DATAW($bits(dram_fill_rsp_addr) + $bits(dram_fill_rsp_data)), + .DATAW(`LINE_ADDR_WIDTH + $bits(dram_fill_rsp_data)), .SIZE(DFPQ_SIZE) ) dfp_queue ( .clk (clk), @@ -259,7 +259,7 @@ module VX_bank #( wire [`WORD_SELECT_ADDR_END:0] qual_wsel_st0; wire [`WORD_WIDTH-1:0] qual_writeword_st0; - wire [`BANK_LINE_WORDS-1:0][`WORD_WIDTH-1:0] qual_writedata_st0; + wire [`BANK_LINE_WIDTH-1:0] qual_writedata_st0; wire [`REQ_INST_META_WIDTH-1:0] qual_inst_meta_st0; wire qual_going_to_write_st0; wire qual_is_snp; @@ -269,7 +269,7 @@ module VX_bank #( wire [`WORD_SELECT_ADDR_END:0] wsel_st1 [STAGE_1_CYCLES-1:0]; wire [`WORD_WIDTH-1:0] writeword_st1 [STAGE_1_CYCLES-1:0]; wire [`REQ_INST_META_WIDTH-1:0] inst_meta_st1 [STAGE_1_CYCLES-1:0]; - wire [`BANK_LINE_WORDS-1:0][`WORD_WIDTH-1:0] writedata_st1[STAGE_1_CYCLES-1:0]; + wire [`BANK_LINE_WIDTH-1:0] writedata_st1 [STAGE_1_CYCLES-1:0]; wire is_snp_st1 [STAGE_1_CYCLES-1:0]; assign qual_is_fill_st0 = dfpq_pop; @@ -305,7 +305,7 @@ module VX_bank #( 0; VX_generic_register #( - .N(1 + 1 + 1 + `LINE_ADDR_WIDTH + `BASE_ADDR_BITS + `WORD_WIDTH + `REQ_INST_META_WIDTH + 1 + (`BANK_LINE_WORDS*`WORD_WIDTH)) + .N(1 + 1 + 1 + `LINE_ADDR_WIDTH + `BASE_ADDR_BITS + `WORD_WIDTH + `REQ_INST_META_WIDTH + 1 + `BANK_LINE_WIDTH) ) s0_1_c0 ( .clk (clk), .reset (reset), @@ -318,7 +318,7 @@ module VX_bank #( genvar i; for (i = 1; i < STAGE_1_CYCLES; i = i + 1) begin VX_generic_register #( - .N(1 + 1 + 1 + `LINE_ADDR_WIDTH + `BASE_ADDR_BITS + `WORD_WIDTH + `REQ_INST_META_WIDTH + 1 + (`BANK_LINE_WORDS*`WORD_WIDTH)) + .N(1 + 1 + 1 + `LINE_ADDR_WIDTH + `BASE_ADDR_BITS + `WORD_WIDTH + `REQ_INST_META_WIDTH + 1 + `BANK_LINE_WIDTH) ) s0_1_cc ( .clk (clk), .reset(reset), @@ -329,19 +329,19 @@ module VX_bank #( ); end - wire[`WORD_WIDTH-1:0] readword_st1e; - wire[`BANK_LINE_WORDS-1:0][`WORD_WIDTH-1:0] readdata_st1e; - wire[`TAG_SELECT_BITS-1:0] readtag_st1e; - wire miss_st1e; - wire dirty_st1e; + wire[`WORD_WIDTH-1:0] readword_st1e; + wire[`BANK_LINE_WIDTH-1:0] readdata_st1e; + wire[`TAG_SELECT_BITS-1:0] readtag_st1e; + wire miss_st1e; + wire dirty_st1e; `DEBUG_BEGIN - wire [CORE_TAG_WIDTH-1:0] tag_st1e; - wire [`REQS_BITS-1:0] tid_st1e; + wire [CORE_TAG_WIDTH-1:0] tag_st1e; + wire [`REQS_BITS-1:0] tid_st1e; `DEBUG_END - wire [`BYTE_EN_BITS-1:0] mem_read_st1e; - wire [`BYTE_EN_BITS-1:0] mem_write_st1e; - wire fill_saw_dirty_st1e; - wire is_snp_st1e; + wire [`BYTE_EN_BITS-1:0] mem_read_st1e; + wire [`BYTE_EN_BITS-1:0] mem_write_st1e; + wire fill_saw_dirty_st1e; + wire is_snp_st1e; assign is_snp_st1e = is_snp_st1[STAGE_1_CYCLES-1]; assign {tag_st1e, mem_read_st1e, mem_write_st1e, tid_st1e} = inst_meta_st1[STAGE_1_CYCLES-1]; @@ -391,7 +391,7 @@ module VX_bank #( wire [`BASE_ADDR_BITS-1:0] wsel_st2; wire [`WORD_WIDTH-1:0] writeword_st2; wire [`WORD_WIDTH-1:0] readword_st2; - wire [`BANK_LINE_WORDS-1:0][`WORD_WIDTH-1:0] readdata_st2; + wire [`BANK_LINE_WIDTH-1:0] readdata_st2; wire miss_st2; wire dirty_st2; wire [`REQ_INST_META_WIDTH-1:0] inst_meta_st2; @@ -400,7 +400,7 @@ module VX_bank #( wire is_snp_st2; VX_generic_register #( - .N(1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `BASE_ADDR_BITS + `WORD_WIDTH + `WORD_WIDTH + (`BANK_LINE_WORDS * `WORD_WIDTH) + `TAG_SELECT_BITS + 1 + 1 + `REQ_INST_META_WIDTH) + .N(1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `BASE_ADDR_BITS + `WORD_WIDTH + `WORD_WIDTH + `BANK_LINE_WIDTH + `TAG_SELECT_BITS + 1 + 1 + `REQ_INST_META_WIDTH) ) st_1e_2 ( .clk (clk), .reset(reset), @@ -522,7 +522,7 @@ module VX_bank #( wire[`LINE_ADDR_WIDTH-1:0] dwbq_req_addr; wire dwbq_empty; - wire[`BANK_LINE_WORDS-1:0][`WORD_WIDTH-1:0] dwbq_req_data; + wire[`BANK_LINE_WIDTH-1:0] dwbq_req_data; if (SNOOP_FORWARDING) begin assign dwbq_req_data = (should_flush && dwbq_push) ? writeword_st2 : readdata_st2; @@ -556,7 +556,7 @@ module VX_bank #( assign dram_wb_req_valid = !dwbq_empty; VX_generic_queue #( - .DATAW(`LINE_ADDR_WIDTH + (`BANK_LINE_WORDS * `WORD_WIDTH)), + .DATAW(`LINE_ADDR_WIDTH + `BANK_LINE_WIDTH), .SIZE(DWBQ_SIZE) ) dwb_queue ( .clk (clk), diff --git a/hw/rtl/cache/VX_cache.v b/hw/rtl/cache/VX_cache.v index 120f757c..3eb2c976 100644 --- a/hw/rtl/cache/VX_cache.v +++ b/hw/rtl/cache/VX_cache.v @@ -105,33 +105,33 @@ module VX_cache #( input wire snp_fwd_ready ); - wire [NUM_BANKS-1:0][NUM_REQUESTS-1:0] per_bank_valids; + wire [NUM_BANKS-1:0][NUM_REQUESTS-1:0] per_bank_valids; - wire [NUM_BANKS-1:0] per_bank_core_rsp_pop; - wire [NUM_BANKS-1:0] per_bank_core_rsp_valid; - wire [NUM_BANKS-1:0][`REQS_BITS-1:0] per_bank_core_rsp_tid; - wire [NUM_BANKS-1:0][`WORD_WIDTH-1:0] per_bank_core_rsp_data; - wire [NUM_BANKS-1:0][CORE_TAG_WIDTH-1:0] per_bank_core_rsp_tag; + wire [NUM_BANKS-1:0] per_bank_core_rsp_pop; + wire [NUM_BANKS-1:0] per_bank_core_rsp_valid; + wire [NUM_BANKS-1:0][`REQS_BITS-1:0] per_bank_core_rsp_tid; + wire [NUM_BANKS-1:0][`WORD_WIDTH-1:0] per_bank_core_rsp_data; + wire [NUM_BANKS-1:0][CORE_TAG_WIDTH-1:0] per_bank_core_rsp_tag; - wire dfqq_full; - wire [NUM_BANKS-1:0] per_bank_dram_fill_req_valid; - wire [NUM_BANKS-1:0][`DRAM_ADDR_WIDTH-1:0] per_bank_dram_fill_req_addr; - wire [NUM_BANKS-1:0] per_bank_dram_fill_rsp_ready; + wire dfqq_full; + wire [NUM_BANKS-1:0] per_bank_dram_fill_req_valid; + wire [NUM_BANKS-1:0][`DRAM_ADDR_WIDTH-1:0] per_bank_dram_fill_req_addr; + wire [NUM_BANKS-1:0] per_bank_dram_fill_rsp_ready; - wire [NUM_BANKS-1:0] per_bank_dram_wb_queue_pop; - wire [NUM_BANKS-1:0] per_bank_dram_wb_req_valid; - wire [NUM_BANKS-1:0][`DRAM_ADDR_WIDTH-1:0] per_bank_dram_wb_req_addr; - wire [NUM_BANKS-1:0][`BANK_LINE_WORDS-1:0][`WORD_WIDTH-1:0] per_bank_dram_wb_req_data; + wire [NUM_BANKS-1:0] per_bank_dram_wb_queue_pop; + wire [NUM_BANKS-1:0] per_bank_dram_wb_req_valid; + wire [NUM_BANKS-1:0][`DRAM_ADDR_WIDTH-1:0] per_bank_dram_wb_req_addr; + wire [NUM_BANKS-1:0][`BANK_LINE_WIDTH-1:0] per_bank_dram_wb_req_data; - wire [NUM_BANKS-1:0] per_bank_reqq_full; - wire [NUM_BANKS-1:0] per_bank_snp_req_full; + wire [NUM_BANKS-1:0] per_bank_reqq_full; + wire [NUM_BANKS-1:0] per_bank_snp_req_full; - wire [NUM_BANKS-1:0] per_bank_snp_fwd_valid; - wire [NUM_BANKS-1:0][`DRAM_ADDR_WIDTH-1:0] per_bank_snp_fwd_addr; - wire [NUM_BANKS-1:0] per_bank_snp_fwd_pop; + wire [NUM_BANKS-1:0] per_bank_snp_fwd_valid; + wire [NUM_BANKS-1:0][`DRAM_ADDR_WIDTH-1:0] per_bank_snp_fwd_addr; + wire [NUM_BANKS-1:0] per_bank_snp_fwd_pop; `DEBUG_BEGIN - wire [NUM_BANKS-1:0] per_bank_dram_fill_req_is_snp; + wire [NUM_BANKS-1:0] per_bank_dram_fill_req_is_snp; `DEBUG_END assign dram_req_tag = dram_req_addr; @@ -160,36 +160,36 @@ module VX_cache #( wire [NUM_REQUESTS-1:0][`BYTE_EN_BITS-1:0] curr_bank_core_req_read; wire [NUM_REQUESTS-1:0][`BYTE_EN_BITS-1:0] curr_bank_core_req_write; - wire curr_bank_core_rsp_pop; - wire curr_bank_core_rsp_valid; - wire [`REQS_BITS-1:0] curr_bank_core_rsp_tid; - wire [`WORD_WIDTH-1:0] curr_bank_core_rsp_data; - wire [CORE_TAG_WIDTH-1:0] curr_bank_core_rsp_tag; + wire curr_bank_core_rsp_pop; + wire curr_bank_core_rsp_valid; + wire [`REQS_BITS-1:0] curr_bank_core_rsp_tid; + wire [`WORD_WIDTH-1:0] curr_bank_core_rsp_data; + wire [CORE_TAG_WIDTH-1:0] curr_bank_core_rsp_tag; - wire curr_bank_dram_fill_rsp_valid; - wire [`BANK_LINE_WORDS-1:0][`WORD_WIDTH-1:0] curr_bank_dram_fill_rsp_data; - wire [`LINE_ADDR_WIDTH-1:0] curr_bank_dram_fill_rsp_addr; - wire curr_bank_dram_fill_rsp_ready; + wire curr_bank_dram_fill_rsp_valid; + wire [`BANK_LINE_WIDTH-1:0] curr_bank_dram_fill_rsp_data; + wire [`LINE_ADDR_WIDTH-1:0] curr_bank_dram_fill_rsp_addr; + wire curr_bank_dram_fill_rsp_ready; - wire curr_bank_dram_fill_req_full; - wire curr_bank_dram_fill_req_valid; - wire curr_bank_dram_fill_req_is_snp; - wire [`LINE_ADDR_WIDTH-1:0] curr_bank_dram_fill_req_addr; + wire curr_bank_dram_fill_req_full; + wire curr_bank_dram_fill_req_valid; + wire curr_bank_dram_fill_req_is_snp; + wire [`LINE_ADDR_WIDTH-1:0] curr_bank_dram_fill_req_addr; - wire curr_bank_dram_wb_req_pop; - wire curr_bank_dram_wb_req_valid; - wire [`LINE_ADDR_WIDTH-1:0] curr_bank_dram_wb_req_addr; - wire[`BANK_LINE_WORDS-1:0][`WORD_WIDTH-1:0] curr_bank_dram_wb_req_data; + wire curr_bank_dram_wb_req_pop; + wire curr_bank_dram_wb_req_valid; + wire [`LINE_ADDR_WIDTH-1:0] curr_bank_dram_wb_req_addr; + wire[`BANK_LINE_WIDTH-1:0] curr_bank_dram_wb_req_data; - wire curr_bank_snp_req_valid; - wire [`LINE_ADDR_WIDTH-1:0] curr_bank_snp_req_addr; - wire curr_bank_snp_req_full; + wire curr_bank_snp_req_valid; + wire [`LINE_ADDR_WIDTH-1:0] curr_bank_snp_req_addr; + wire curr_bank_snp_req_full; - wire curr_bank_snp_fwd_valid; - wire [`LINE_ADDR_WIDTH-1:0] curr_bank_snp_fwd_addr; - wire curr_bank_snp_fwd_pop; + wire curr_bank_snp_fwd_valid; + wire [`LINE_ADDR_WIDTH-1:0] curr_bank_snp_fwd_addr; + wire curr_bank_snp_fwd_pop; - wire curr_bank_reqq_full; + wire curr_bank_reqq_full; // Core Req assign curr_bank_core_req_valids = per_bank_valids[i]; diff --git a/hw/rtl/cache/VX_cache_dram_req_arb.v b/hw/rtl/cache/VX_cache_dram_req_arb.v index f49cefe4..6170f2c0 100644 --- a/hw/rtl/cache/VX_cache_dram_req_arb.v +++ b/hw/rtl/cache/VX_cache_dram_req_arb.v @@ -24,7 +24,7 @@ module VX_cache_dram_req_arb #( // Writeback Request input wire [NUM_BANKS-1:0] per_bank_dram_wb_req_valid, input wire [NUM_BANKS-1:0][`DRAM_ADDR_WIDTH-1:0] per_bank_dram_wb_req_addr, - input wire [NUM_BANKS-1:0][`BANK_LINE_WORDS-1:0][`WORD_WIDTH-1:0] per_bank_dram_wb_req_data, + input wire [NUM_BANKS-1:0][`BANK_LINE_WIDTH-1:0] per_bank_dram_wb_req_data, output wire [NUM_BANKS-1:0] per_bank_dram_wb_queue_pop, // Merged Request diff --git a/hw/rtl/cache/VX_snp_fwd_arb.v b/hw/rtl/cache/VX_snp_fwd_arb.v index 07532119..bfd3bb57 100644 --- a/hw/rtl/cache/VX_snp_fwd_arb.v +++ b/hw/rtl/cache/VX_snp_fwd_arb.v @@ -5,7 +5,7 @@ module VX_snp_fwd_arb #( parameter BANK_LINE_SIZE = 1 ) ( input wire [NUM_BANKS-1:0] per_bank_snp_fwd_valid, - input wire [NUM_BANKS-1:0][`DRAM_ADDR_WIDTH-1:0] per_bank_snp_fwd_addr, + input wire [NUM_BANKS-1:0][`DRAM_ADDR_WIDTH-1:0] per_bank_snp_fwd_addr, output reg [NUM_BANKS-1:0] per_bank_snp_fwd_pop, output wire snp_fwd_valid,