diff --git a/hw/rtl/VX_core_wrapper.sv b/hw/rtl/VX_core_wrapper.sv index 18477c76..6fee8b53 100644 --- a/hw/rtl/VX_core_wrapper.sv +++ b/hw/rtl/VX_core_wrapper.sv @@ -20,110 +20,80 @@ module Vortex import VX_gpu_pkg::*; #( input interrupts_meip, input interrupts_seip, - input imem_0_a_ready, - input imem_0_d_valid, - input [2:0] imem_0_d_bits_opcode, - // input [1:0] imem_0_d_bits_param, - input [3:0] imem_0_d_bits_size, - input [ICACHE_TAG_WIDTH-1:0] imem_0_d_bits_source, - // input [2:0] imem_0_d_bits_sink, - // input imem_0_d_bits_denied, - input [31:0] imem_0_d_bits_data, - // input imem_0_d_bits_corrupt, - output imem_0_a_valid, - output [2:0] imem_0_a_bits_opcode, - // output [2:0] imem_0_a_bits_param, - output [3:0] imem_0_a_bits_size, - output [ICACHE_TAG_WIDTH-1:0] imem_0_a_bits_source, - output [31:0] imem_0_a_bits_address, - output [3:0] imem_0_a_bits_mask, - output [31:0] imem_0_a_bits_data, - // output imem_0_a_bits_corrupt, - output imem_0_d_ready, + input imem_0_a_ready, + input imem_0_d_valid, + input [2:0] imem_0_d_bits_opcode, + input [3:0] imem_0_d_bits_size, + input [ICACHE_TAG_WIDTH-1:0] imem_0_d_bits_source, + input [31:0] imem_0_d_bits_data, + output imem_0_a_valid, + output [2:0] imem_0_a_bits_opcode, + output [3:0] imem_0_a_bits_size, + output [ICACHE_TAG_WIDTH-1:0] imem_0_a_bits_source, + output [31:0] imem_0_a_bits_address, + output [3:0] imem_0_a_bits_mask, + output [31:0] imem_0_a_bits_data, + output imem_0_d_ready, - input dmem_0_a_ready, - input dmem_0_d_valid, - input [2:0] dmem_0_d_bits_opcode, - // input [1:0] dmem_0_d_bits_param, - input [3:0] dmem_0_d_bits_size, - input [DCACHE_NOSM_TAG_WIDTH-1:0] dmem_0_d_bits_source, - // input [2:0] dmem_0_d_bits_sink, - // input dmem_0_d_bits_denied, - input [31:0] dmem_0_d_bits_data, - // input dmem_0_d_bits_corrupt, - output dmem_0_a_valid, - output [2:0] dmem_0_a_bits_opcode, - // output [2:0] dmem_0_a_bits_param, - output [3:0] dmem_0_a_bits_size, - output [DCACHE_NOSM_TAG_WIDTH-1:0] dmem_0_a_bits_source, - output [31:0] dmem_0_a_bits_address, - output [3:0] dmem_0_a_bits_mask, - output [31:0] dmem_0_a_bits_data, - // output dmem_0_a_bits_corrupt, - output dmem_0_d_ready, + input dmem_0_a_ready, + input dmem_0_d_valid, + input [2:0] dmem_0_d_bits_opcode, + input [3:0] dmem_0_d_bits_size, + input [DCACHE_NOSM_TAG_WIDTH-1:0] dmem_0_d_bits_source, + input [31:0] dmem_0_d_bits_data, + output dmem_0_a_valid, + output [2:0] dmem_0_a_bits_opcode, + output [3:0] dmem_0_a_bits_size, + output [DCACHE_NOSM_TAG_WIDTH-1:0] dmem_0_a_bits_source, + output [31:0] dmem_0_a_bits_address, + output [3:0] dmem_0_a_bits_mask, + output [31:0] dmem_0_a_bits_data, + output dmem_0_d_ready, - input dmem_1_a_ready, - input dmem_1_d_valid, - input [2:0] dmem_1_d_bits_opcode, - // input [1:0] dmem_1_d_bits_param, - input [3:0] dmem_1_d_bits_size, - input [DCACHE_NOSM_TAG_WIDTH-1:0] dmem_1_d_bits_source, - // input [2:0] dmem_1_d_bits_sink, - // input dmem_1_d_bits_denied, - input [31:0] dmem_1_d_bits_data, - // input dmem_1_d_bits_corrupt, - output dmem_1_a_valid, - output [2:0] dmem_1_a_bits_opcode, - // output [2:0] dmem_1_a_bits_param, - output [3:0] dmem_1_a_bits_size, - output [DCACHE_NOSM_TAG_WIDTH-1:0] dmem_1_a_bits_source, - output [31:0] dmem_1_a_bits_address, - output [3:0] dmem_1_a_bits_mask, - output [31:0] dmem_1_a_bits_data, - // output dmem_1_a_bits_corrupt, - output dmem_1_d_ready, + input dmem_1_a_ready, + input dmem_1_d_valid, + input [2:0] dmem_1_d_bits_opcode, + input [3:0] dmem_1_d_bits_size, + input [DCACHE_NOSM_TAG_WIDTH-1:0] dmem_1_d_bits_source, + input [31:0] dmem_1_d_bits_data, + output dmem_1_a_valid, + output [2:0] dmem_1_a_bits_opcode, + output [3:0] dmem_1_a_bits_size, + output [DCACHE_NOSM_TAG_WIDTH-1:0] dmem_1_a_bits_source, + output [31:0] dmem_1_a_bits_address, + output [3:0] dmem_1_a_bits_mask, + output [31:0] dmem_1_a_bits_data, + output dmem_1_d_ready, - input dmem_2_a_ready, - input dmem_2_d_valid, - input [2:0] dmem_2_d_bits_opcode, - // input [1:0] dmem_2_d_bits_param, - input [3:0] dmem_2_d_bits_size, - input [DCACHE_NOSM_TAG_WIDTH-1:0] dmem_2_d_bits_source, - // input [2:0] dmem_2_d_bits_sink, - // input dmem_2_d_bits_denied, - input [31:0] dmem_2_d_bits_data, - // input dmem_2_d_bits_corrupt, - output dmem_2_a_valid, - output [2:0] dmem_2_a_bits_opcode, - // output [2:0] dmem_2_a_bits_param, - output [3:0] dmem_2_a_bits_size, - output [DCACHE_NOSM_TAG_WIDTH-1:0] dmem_2_a_bits_source, - output [31:0] dmem_2_a_bits_address, - output [3:0] dmem_2_a_bits_mask, - output [31:0] dmem_2_a_bits_data, - // output dmem_2_a_bits_corrupt, - output dmem_2_d_ready, + input dmem_2_a_ready, + input dmem_2_d_valid, + input [2:0] dmem_2_d_bits_opcode, + input [3:0] dmem_2_d_bits_size, + input [DCACHE_NOSM_TAG_WIDTH-1:0] dmem_2_d_bits_source, + input [31:0] dmem_2_d_bits_data, + output dmem_2_a_valid, + output [2:0] dmem_2_a_bits_opcode, + output [3:0] dmem_2_a_bits_size, + output [DCACHE_NOSM_TAG_WIDTH-1:0] dmem_2_a_bits_source, + output [31:0] dmem_2_a_bits_address, + output [3:0] dmem_2_a_bits_mask, + output [31:0] dmem_2_a_bits_data, + output dmem_2_d_ready, - input dmem_3_a_ready, - input dmem_3_d_valid, - input [2:0] dmem_3_d_bits_opcode, - // input [1:0] dmem_3_d_bits_param, - input [3:0] dmem_3_d_bits_size, - input [DCACHE_NOSM_TAG_WIDTH-1:0] dmem_3_d_bits_source, - // input [2:0] dmem_3_d_bits_sink, - // input dmem_3_d_bits_denied, - input [31:0] dmem_3_d_bits_data, - // input dmem_3_d_bits_corrupt, - output dmem_3_a_valid, - output [2:0] dmem_3_a_bits_opcode, - // output [2:0] dmem_3_a_bits_param, - output [3:0] dmem_3_a_bits_size, - output [DCACHE_NOSM_TAG_WIDTH-1:0] dmem_3_a_bits_source, - output [31:0] dmem_3_a_bits_address, - output [3:0] dmem_3_a_bits_mask, - output [31:0] dmem_3_a_bits_data, - // output dmem_3_a_bits_corrupt, - output dmem_3_d_ready, + input dmem_3_a_ready, + input dmem_3_d_valid, + input [2:0] dmem_3_d_bits_opcode, + input [3:0] dmem_3_d_bits_size, + input [DCACHE_NOSM_TAG_WIDTH-1:0] dmem_3_d_bits_source, + input [31:0] dmem_3_d_bits_data, + output dmem_3_a_valid, + output [2:0] dmem_3_a_bits_opcode, + output [3:0] dmem_3_a_bits_size, + output [DCACHE_NOSM_TAG_WIDTH-1:0] dmem_3_a_bits_source, + output [31:0] dmem_3_a_bits_address, + output [3:0] dmem_3_a_bits_mask, + output [31:0] dmem_3_a_bits_data, + output dmem_3_d_ready, // input fpu_fcsr_flags_valid, // input [4:0] fpu_fcsr_flags_bits, @@ -201,6 +171,8 @@ module Vortex import VX_gpu_pkg::*; #( // NOTE(hansung): need to use DCACHE_NOSM_TAG_WIDTH here instead of // DCACHE_TAG_WIDTH; the latter is only used inside the core to // differentiate between requests going to the cache vs. sharedmem. + // FIXME: DCACHE_NUM_REQS is assumed to be the same as NUM_LANES as of + // now. VX_mem_bus_if #( .DATA_SIZE (DCACHE_WORD_SIZE), .TAG_WIDTH (DCACHE_NOSM_TAG_WIDTH)