From b70df8cbc9fe73c7e5e2dea8ce0d796eab0bf7ee Mon Sep 17 00:00:00 2001 From: Richard Yan Date: Tue, 7 May 2024 13:52:07 -0700 Subject: [PATCH] proper srams --- hw/rtl/libs/VX_dp_ram.sv | 123 +++++++++++++++++++++++++++++---------- 1 file changed, 93 insertions(+), 30 deletions(-) diff --git a/hw/rtl/libs/VX_dp_ram.sv b/hw/rtl/libs/VX_dp_ram.sv index 4963c397..0303f3aa 100644 --- a/hw/rtl/libs/VX_dp_ram.sv +++ b/hw/rtl/libs/VX_dp_ram.sv @@ -160,37 +160,69 @@ module VX_dp_ram #( assign rdata = ram[raddr]; end end else begin - if (OUT_REG != 0) begin - reg [DATAW-1:0] ram [SIZE-1:0]; - reg [DATAW-1:0] rdata_r; - `RAM_INITIALIZATION - always @(posedge clk) begin - if (write) begin - for (integer i = 0; i < WRENW; ++i) begin - if (wren[i]) - ram[waddr][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW]; - end - end - if (read) begin - rdata_r <= ram[raddr]; - end - end - assign rdata = rdata_r; + `ifndef FIRESIM + if (DATAW == 1024 && SIZE == 16) begin // dcache data + dcache_data ram ( + .R0_addr(raddr), + .R0_clk(clk), + .R0_data(rdata), + .R0_en(read), + .W0_addr(waddr), + .W0_clk(clk), + .W0_data(wdata), + .W0_en(write), + .W0_mask(wren) + ); + end else if (DATAW == 305 && SIZE == 8) begin // mshr + cache_mshr ram ( + .R0_addr(raddr), + .R0_clk(clk), + .R0_data(rdata), + .R0_en(read), + .W0_addr(waddr), + .W0_clk(clk), + .W0_data(wdata), + .W0_en(write) + ); + end else if (DATAW == 24 && SIZE == 16) begin // dcache tags + dcache_tags ram ( + .R0_addr(raddr), + .R0_clk(clk), + .R0_data(rdata), + .R0_en(read), + .W0_addr(waddr), + .W0_clk(clk), + .W0_data(wdata), + .W0_en(write) + ); + end else if (DATAW == 1024 && SIZE == 128) begin // icache data + icache_data ram ( + .R0_addr(raddr), + .R0_clk(clk), + .R0_data(rdata), + .R0_en(read), + .W0_addr(waddr), + .W0_clk(clk), + .W0_data(wdata), + .W0_en(write), + .W0_mask(wren) + ); + end else if (DATAW == 21 && SIZE == 128) begin // icache tags + icache_tags ram ( + .R0_addr(raddr), + .R0_clk(clk), + .R0_data(rdata), + .R0_en(read), + .W0_addr(waddr), + .W0_clk(clk), + .W0_data(wdata), + .W0_en(write) + ); end else begin - if (NO_RWCHECK != 0) begin - `NO_RW_RAM_CHECK reg [DATAW-1:0] ram [SIZE-1:0]; - `RAM_INITIALIZATION - always @(posedge clk) begin - if (write) begin - for (integer i = 0; i < WRENW; ++i) begin - if (wren[i]) - ram[waddr][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW]; - end - end - end - assign rdata = ram[raddr]; - end else begin + `endif + if (OUT_REG != 0) begin reg [DATAW-1:0] ram [SIZE-1:0]; + reg [DATAW-1:0] rdata_r; `RAM_INITIALIZATION always @(posedge clk) begin if (write) begin @@ -199,10 +231,41 @@ module VX_dp_ram #( ram[waddr][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW]; end end + if (read) begin + rdata_r <= ram[raddr]; + end + end + assign rdata = rdata_r; + end else begin + if (NO_RWCHECK != 0) begin + `NO_RW_RAM_CHECK reg [DATAW-1:0] ram [SIZE-1:0]; + `RAM_INITIALIZATION + always @(posedge clk) begin + if (write) begin + for (integer i = 0; i < WRENW; ++i) begin + if (wren[i]) + ram[waddr][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW]; + end + end + end + assign rdata = ram[raddr]; + end else begin + reg [DATAW-1:0] ram [SIZE-1:0]; + `RAM_INITIALIZATION + always @(posedge clk) begin + if (write) begin + for (integer i = 0; i < WRENW; ++i) begin + if (wren[i]) + ram[waddr][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW]; + end + end + end + assign rdata = ram[raddr]; end - assign rdata = ram[raddr]; end + `ifndef FIRESIM end + `endif end `endif end else begin