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update DRAM simulation - reduce the latency of duplicate requests (simulate DRAM cache)

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This commit is contained in:
Blaise Tine
2020-12-03 07:30:19 -08:00
parent f3b1069ce8
commit b7a724410b
4 changed files with 37 additions and 19 deletions
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24
driver/opae/vlsim/opae_sim.cpp
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@@ -245,15 +245,17 @@ void opae_sim::sTxPort_bus() {
} }
void opae_sim::avs_bus() { void opae_sim::avs_bus() {
// schedule DRAM read responses // update DRAM responses schedule
for (auto& rsp : dram_reads_) {
if (rsp.cycles_left > 0)
rsp.cycles_left -= 1;
}
// schedule DRAM responses in FIFO order
std::list<dram_rd_req_t>::iterator dram_rd_it(dram_reads_.end()); std::list<dram_rd_req_t>::iterator dram_rd_it(dram_reads_.end());
for (auto it = dram_reads_.begin(), ie = dram_reads_.end(); it != ie; ++it) { if (!dram_reads_.empty()
if (it->cycles_left > 0) { && (0 == dram_reads_.begin()->cycles_left)) {
it->cycles_left -= 1; dram_rd_it = dram_reads_.begin();
}
if ((it != ie) && (it->cycles_left == 0)) {
dram_rd_it = it;
}
} }
// send DRAM response // send DRAM response
@@ -304,6 +306,12 @@ void opae_sim::avs_bus() {
dram_req.addr = vortex_afu_->avs_address; dram_req.addr = vortex_afu_->avs_address;
ram_.read(vortex_afu_->avs_address * CACHE_BLOCK_SIZE, CACHE_BLOCK_SIZE, dram_req.block.data()); ram_.read(vortex_afu_->avs_address * CACHE_BLOCK_SIZE, CACHE_BLOCK_SIZE, dram_req.block.data());
dram_req.cycles_left = DRAM_LATENCY; dram_req.cycles_left = DRAM_LATENCY;
for (auto& rsp : dram_reads_) {
if (dram_req.addr == rsp.addr) {
dram_req.cycles_left = rsp.cycles_left;
break;
}
}
dram_reads_.emplace_back(dram_req); dram_reads_.emplace_back(dram_req);
/*printf("%0ld: [sim] DRAM Rd Req: addr=%x, pending={", timestamp, dram_req.addr * CACHE_BLOCK_SIZE); /*printf("%0ld: [sim] DRAM Rd Req: addr=%x, pending={", timestamp, dram_req.addr * CACHE_BLOCK_SIZE);
for (auto& req : dram_reads_) { for (auto& req : dram_reads_) {

2
hw/rtl/VX_config.vh
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@@ -16,7 +16,7 @@
`endif `endif
`ifndef NUM_THREADS `ifndef NUM_THREADS
`define NUM_THREADS 4 `define NUM_THREADS 8
`endif `endif
`ifndef NUM_BARRIERS `ifndef NUM_BARRIERS

25
hw/simulate/simulator.cpp
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@@ -127,15 +127,17 @@ void Simulator::eval_dram_bus() {
return; return;
} }
// schedule DRAM responses // update DRAM responses schedule
for (auto& rsp : dram_rsp_vec_) {
if (rsp.cycles_left > 0)
rsp.cycles_left -= 1;
}
// schedule DRAM responses in FIFO order
std::list<dram_req_t>::iterator dram_rsp_it(dram_rsp_vec_.end()); std::list<dram_req_t>::iterator dram_rsp_it(dram_rsp_vec_.end());
for (auto it = dram_rsp_vec_.begin(), ie = dram_rsp_vec_.end(); it != ie; ++it) { if (!dram_rsp_vec_.empty()
if (it->cycles_left > 0) { && (0 == dram_rsp_vec_.begin()->cycles_left)) {
it->cycles_left -= 1; dram_rsp_it = dram_rsp_vec_.begin();
}
if ((dram_rsp_it == ie) && (it->cycles_left == 0)) {
dram_rsp_it = it;
}
} }
// send DRAM response // send DRAM response
@@ -181,8 +183,15 @@ void Simulator::eval_dram_bus() {
} else { } else {
dram_req_t dram_req; dram_req_t dram_req;
dram_req.tag = vortex_->dram_req_tag; dram_req.tag = vortex_->dram_req_tag;
dram_req.addr = vortex_->dram_req_addr;
ram_->read(vortex_->dram_req_addr * GLOBAL_BLOCK_SIZE, GLOBAL_BLOCK_SIZE, dram_req.block.data()); ram_->read(vortex_->dram_req_addr * GLOBAL_BLOCK_SIZE, GLOBAL_BLOCK_SIZE, dram_req.block.data());
dram_req.cycles_left = DRAM_LATENCY; dram_req.cycles_left = DRAM_LATENCY;
for (auto& rsp : dram_rsp_vec_) {
if (dram_req.addr == rsp.addr) {
dram_req.cycles_left = rsp.cycles_left;
break;
}
}
dram_rsp_vec_.emplace_back(dram_req); dram_rsp_vec_.emplace_back(dram_req);
} }
} }

1
hw/simulate/simulator.h
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@@ -51,6 +51,7 @@ private:
typedef struct { typedef struct {
int cycles_left; int cycles_left;
std::array<uint8_t, GLOBAL_BLOCK_SIZE> block; std::array<uint8_t, GLOBAL_BLOCK_SIZE> block;
uint32_t addr;
uint32_t tag; uint32_t tag;
} dram_req_t; } dram_req_t;