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rtl refactoring

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This commit is contained in:
Blaise Tine
2020-05-05 10:46:48 -04:00
parent f142afac80
commit b7e892ee16
39 changed files with 393 additions and 425 deletions
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6
hw/rtl/VX_alu_unit.v
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@@ -90,7 +90,7 @@ module VX_alu_unit (
assign alu_stall = inst_delay_stall;
always @(*) begin
case(alu_op)
case (alu_op)
`DIV,
`DIVU,
`REM,
@@ -136,7 +136,7 @@ module VX_alu_unit (
assign upper_immed = {upper_immed, {12{1'b0}}};
always @(*) begin
case(alu_op)
case (alu_op)
`ADD: alu_result = $signed(ALU_in1) + $signed(ALU_in2);
`SUB: alu_result = $signed(ALU_in1) - $signed(ALU_in2);
`SLLA: alu_result = ALU_in1 << ALU_in2[4:0];
@@ -177,7 +177,7 @@ module VX_alu_unit (
assign upper_immed_s = {upper_immed, {12{1'b0}}};
always @(*) begin
case(alu_op)
case (alu_op)
`ADD: alu_result = $signed(ALU_in1) + $signed(ALU_in2);
`SUB: alu_result = $signed(ALU_in1) - $signed(ALU_in2);
`SLLA: alu_result = ALU_in1 << ALU_in2[4:0];