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rtl refactoring

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This commit is contained in:
Blaise Tine
2020-05-05 10:46:48 -04:00
parent f142afac80
commit b7e892ee16
39 changed files with 393 additions and 425 deletions
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31
hw/rtl/cache/VX_bank.v vendored
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@@ -11,7 +11,7 @@ module VX_bank #(
parameter WORD_SIZE = 4,
// Number of Word requests per cycle {1, 2, 4, 8, ...}
parameter NUM_REQUESTS = 2,
// Number of cycles to complete stage 1 (read from memory)
// Number of cycles to complete i 1 (read from memory)
parameter STAGE_1_CYCLES = 2,
// Queues feeding into banks Knobs {1, 2, 4, 8, ...}
@@ -46,7 +46,7 @@ module VX_bank #(
parameter DRAM_ENABLE = 1,
// Enable snoop forwarding
parameter SNOOP_FORWARDING_ENABLE = 0,
parameter SNOOP_FORWARDING = 0,
// core request tag size
parameter CORE_TAG_WIDTH = 1,
@@ -108,7 +108,7 @@ module VX_bank #(
if (reset) begin
snoop_state <= 0;
end else begin
snoop_state <= (snoop_state | snp_req_valid) && SNOOP_FORWARDING_ENABLE;
snoop_state <= (snoop_state | snp_req_valid) && SNOOP_FORWARDING;
end
end
@@ -169,7 +169,7 @@ module VX_bank #(
wire [`BYTE_EN_BITS-1:0] reqq_req_mem_read_st0;
wire [`BYTE_EN_BITS-1:0] reqq_req_mem_write_st0;
assign reqq_push = core_req_ready && (|core_req_valids);
assign reqq_push = core_req_ready && (| core_req_valids);
VX_cache_req_queue #(
.CACHE_SIZE (CACHE_SIZE),
@@ -241,16 +241,16 @@ module VX_bank #(
wire stall_bank_pipe;
reg is_fill_in_pipe;
wire is_fill_st1 [STAGE_1_CYCLES-1:0];
wire is_fill_st1 [STAGE_1_CYCLES-1:0];
`DEBUG_BEGIN
wire going_to_write_st1[STAGE_1_CYCLES-1:0];
wire going_to_write_st1 [STAGE_1_CYCLES-1:0];
`DEBUG_END
integer i;
integer j;
always @(*) begin
is_fill_in_pipe = 0;
for (i = 0; i < STAGE_1_CYCLES; i=i+1) begin
if (is_fill_st1[i]) begin
for (j = 0; j < STAGE_1_CYCLES; j=j+1) begin
if (is_fill_st1[j]) begin
is_fill_in_pipe = 1;
end
end
@@ -327,8 +327,8 @@ module VX_bank #(
.out ({is_snp_st1[0], going_to_write_st1[0], valid_st1[0], addr_st1[0], wsel_st1[0], writeword_st1[0], inst_meta_st1[0], is_fill_st1[0], writedata_st1[0]})
);
genvar stage;
for (stage = 1; stage < STAGE_1_CYCLES; stage = stage + 1) begin
genvar i;
for (i = 1; i < STAGE_1_CYCLES; i = i + 1) begin
VX_generic_register #(
.N(1 + 1 + 1 + `LINE_ADDR_WIDTH + `BASE_ADDR_BITS + `WORD_WIDTH + `REQ_INST_META_WIDTH + 1 + (`BANK_LINE_WORDS*`WORD_WIDTH))
) s0_1_cc (
@@ -336,8 +336,8 @@ module VX_bank #(
.reset(reset),
.stall(stall_bank_pipe),
.flush(0),
.in ({is_snp_st1[stage-1], going_to_write_st1[stage-1], valid_st1[stage-1], addr_st1[stage-1], wsel_st1[stage-1], writeword_st1[stage-1], inst_meta_st1[stage-1], is_fill_st1[stage-1], writedata_st1[stage-1]}),
.out ({is_snp_st1[stage], going_to_write_st1[stage], valid_st1[stage], addr_st1[stage], wsel_st1[stage], writeword_st1[stage], inst_meta_st1[stage], is_fill_st1[stage], writedata_st1[stage]})
.in ({is_snp_st1[i-1], going_to_write_st1[i-1], valid_st1[i-1], addr_st1[i-1], wsel_st1[i-1], writeword_st1[i-1], inst_meta_st1[i-1], is_fill_st1[i-1], writedata_st1[i-1]}),
.out ({is_snp_st1[i], going_to_write_st1[i], valid_st1[i], addr_st1[i], wsel_st1[i], writeword_st1[i], inst_meta_st1[i], is_fill_st1[i], writedata_st1[i]})
);
end
@@ -506,9 +506,10 @@ module VX_bank #(
);
// Enqueue to CWB Queue
// TODO: should investigae the need for "SNOOP_FORWARDING" here
wire cwbq_push = (valid_st2 && !miss_st2)
&& !cwbq_full
&& !(SNOOP_FORWARDING_ENABLE && (miss_add_mem_write == `BYTE_EN_NO))
&& !(SNOOP_FORWARDING && (miss_add_mem_write == `BYTE_EN_NO))
&& !((is_snp_st2 && valid_st2 && ffsq_full)
|| (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full)
|| (valid_st2 && miss_st2 && mrvq_full)
@@ -554,7 +555,7 @@ module VX_bank #(
wire[`BANK_LINE_WORDS-1:0][`WORD_WIDTH-1:0] dwbq_req_data;
if (SNOOP_FORWARDING_ENABLE) begin
if (SNOOP_FORWARDING) begin
assign dwbq_req_data = (should_flush && dwbq_push) ? writeword_st2 : readdata_st2;
assign dwbq_req_addr = (should_flush && dwbq_push) ? addr_st2 : {readtag_st2, addr_st2[`LINE_SELECT_BITS-1:0]};
end else begin

10
hw/rtl/cache/VX_cache.v vendored
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@@ -47,7 +47,7 @@ module VX_cache #(
parameter DRAM_ENABLE = 1,
// Enable snoop forwarding
parameter SNOOP_FORWARDING_ENABLE = 0,
parameter SNOOP_FORWARDING = 0,
// Prefetcher
parameter PRFQ_SIZE = 64,
@@ -135,9 +135,9 @@ module VX_cache #(
`DEBUG_END
assign dram_req_tag = dram_req_addr;
assign core_req_ready = ~(|per_bank_reqq_full);
assign snp_req_ready = ~(|per_bank_snp_req_full);
assign dram_rsp_ready = (|per_bank_dram_fill_rsp_ready);
assign core_req_ready = ~(| per_bank_reqq_full);
assign snp_req_ready = ~(| per_bank_snp_req_full);
assign dram_rsp_ready = (| per_bank_dram_fill_rsp_ready);
VX_cache_core_req_bank_sel #(
.CACHE_SIZE (CACHE_SIZE),
@@ -265,7 +265,7 @@ module VX_cache #(
.FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE),
.DRAM_ENABLE (DRAM_ENABLE),
.WRITE_ENABLE (WRITE_ENABLE),
.SNOOP_FORWARDING_ENABLE(SNOOP_FORWARDING_ENABLE),
.SNOOP_FORWARDING (SNOOP_FORWARDING),
.CORE_TAG_WIDTH (CORE_TAG_WIDTH),
.CORE_TAG_ID_BITS (CORE_TAG_ID_BITS)
) bank (

4
hw/rtl/cache/VX_cache_dfq_queue.v vendored
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@@ -63,8 +63,8 @@ module VX_cache_dfq_queue #(
wire o_empty;
wire use_empty = !(|use_per_bank_dram_fill_req_valid);
wire out_empty = !(|out_per_bank_dram_fill_req_valid) || o_empty;
wire use_empty = !(| use_per_bank_dram_fill_req_valid);
wire out_empty = !(| out_per_bank_dram_fill_req_valid) || o_empty;
wire push_qual = dfqq_push && !dfqq_full;
wire pop_qual = dfqq_pop && use_empty && !out_empty;

2
hw/rtl/cache/VX_cache_dram_req_arb.v vendored
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@@ -98,7 +98,7 @@ module VX_cache_dram_req_arb #(
`DEBUG_END
wire dfqq_pop = !dwb_valid && dfqq_req && dram_req_ready; // If no dwb, and dfqq has valids, then pop
wire dfqq_push = (|per_bank_dram_fill_req_valid);
wire dfqq_push = (| per_bank_dram_fill_req_valid);
VX_cache_dfq_queue cache_dfq_queue(
.clk (clk),

8
hw/rtl/cache/VX_cache_miss_resrv.v vendored
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@@ -90,10 +90,10 @@ module VX_cache_miss_resrv #(
wire [`LOG2UP(MRVQ_SIZE)-1:0] enqueue_index = tail_ptr;
reg [MRVQ_SIZE-1:0] make_ready;
genvar curr_e;
genvar i;
generate
for (curr_e = 0; curr_e < MRVQ_SIZE; curr_e=curr_e+1) begin
assign make_ready[curr_e] = is_fill_st1 && valid_table[curr_e] && (addr_table[curr_e] == fill_addr_st1);
for (i = 0; i < MRVQ_SIZE; i=i+1) begin
assign make_ready[i] = is_fill_st1 && valid_table[i] && (addr_table[i] == fill_addr_st1);
end
endgenerate
@@ -107,7 +107,7 @@ module VX_cache_miss_resrv #(
wire mrvq_push = miss_add && enqueue_possible && (MRVQ_SIZE != 2);
wire mrvq_pop = miss_resrv_pop && dequeue_possible;
wire update_ready = (|make_ready);
wire update_ready = (| make_ready);
always @(posedge clk) begin
if (reset) begin

4
hw/rtl/cache/VX_cache_req_queue.v vendored
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@@ -97,8 +97,8 @@ module VX_cache_req_queue #(
wire o_empty;
wire use_empty = !(|use_per_valids);
wire out_empty = !(|out_per_valids) || o_empty;
wire use_empty = !(| use_per_valids);
wire out_empty = !(| out_per_valids) || o_empty;
wire push_qual = reqq_push && !reqq_full;
wire pop_qual = !out_empty && use_empty;

6
hw/rtl/cache/VX_fill_invalidator.v vendored
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@@ -60,10 +60,10 @@ module VX_fill_invalidator #(
reg [FILL_INVALIDAOR_SIZE-1:0] matched_fill;
wire matched;
integer fi;
integer i;
always @(*) begin
for (fi = 0; fi < FILL_INVALIDAOR_SIZE; fi+=1) begin
matched_fill[fi] = fills_active[fi] && (fills_address[fi] == fill_addr);
for (i = 0; i < FILL_INVALIDAOR_SIZE; i+=1) begin
matched_fill[i] = fills_active[i] && (fills_address[i] == fill_addr);
end
end

2
hw/rtl/cache/VX_tag_data_structure.v vendored
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@@ -68,7 +68,7 @@ module VX_tag_data_structure #(
assign read_tag = tag [read_addr];
assign read_data = data [read_addr];
wire going_to_write = (|write_enable);
wire going_to_write = (| write_enable);
integer i;
always @(posedge clk) begin