RTL code refactoring

2020-04-21 01:03:37 -04:00
parent cfa8626bf7
commit ba4e736782
29 changed files with 332 additions and 563 deletions
--- a/hw/rtl/VX_warp_sched.v
+++ b/hw/rtl/VX_warp_sched.v
@@ -55,7 +55,7 @@ module VX_warp_sched (
 	output wire[`NUM_THREADS-1:0] thread_mask,
 	output wire[`NW_BITS-1:0] warp_num,
 	output wire[31:0]     warp_pc,
-	output wire           ebreak_o,
+	output wire           ebreak,
 	output wire           scheduled_warp,

 	input  wire[`NW_BITS-1:0]    icache_stage_wid,
@@ -331,10 +331,6 @@ module VX_warp_sched (
 	// 	.ones_found()
 	// 	);

-
-	wire ebreak = (warp_active == 0);
-	assign ebreak_o = ebreak;
-
-	/* verilator lint_on WIDTH */
+	assign ebreak = (warp_active == 0);

 endmodule