diff --git a/hw/simulate/Makefile b/hw/simulate/Makefile
index 7fb0de8a..b43b0d4c 100644
--- a/hw/simulate/Makefile
+++ b/hw/simulate/Makefile
@@ -47,7 +47,7 @@ VL_FLAGS += --x-initial unique --x-assign unique
 VL_FLAGS += verilator.vlt
 
 VL_FLAGS += --exe $(SRCS) $(RTL_INCLUDE)
-VL_FLAGS += --cc Vortex.v --top-module $(TOP)
+VL_FLAGS += --cc $(TOP) --top-module $(TOP)
 
 # FPU backend
 FPU_CORE ?= FPU_FPNEW
diff --git a/hw/syn/quartus/vortex/Makefile b/hw/syn/quartus/vortex/Makefile
index ff735e86..48e40608 100644
--- a/hw/syn/quartus/vortex/Makefile
+++ b/hw/syn/quartus/vortex/Makefile
@@ -1,6 +1,6 @@
 PROJECT = Vortex
 TOP_LEVEL_ENTITY = Vortex
-SRC_FILE = Vortex.v
+SRC_FILE = Vortex.sv
 RTL_DIR = ../../../../rtl
 
 FAMILY = "Arria 10"
diff --git a/hw/syn/yosys/Makefile b/hw/syn/yosys/Makefile
index 0aabcef4..6ac5f6a0 100644
--- a/hw/syn/yosys/Makefile
+++ b/hw/syn/yosys/Makefile
@@ -1,6 +1,6 @@
 PROJECT = Vortex
 TOP_LEVEL_ENTITY = Vortex
-SRC_FILE = Vortex.v
+SRC_FILE = Vortex.sv
 RTL_DIR = ../../rtl
 
 DEFINES = -DNDEBUG -DSYNTHESIS -DEXT_F_DISABLE -DNUM_CORES=1 -DNUM_THREADS=2 -DNUM_WARPS=2 -DMEM_BLOCK_SIZE=64