From bcea9866a725c8a5e6492cb56810ead4afd41fbd Mon Sep 17 00:00:00 2001 From: felsabbagh3 Date: Sat, 4 Apr 2020 18:20:06 -0700 Subject: [PATCH] Fixed a couple of things --- rtl/VX_cache/VX_cache_dram_req_arb.v | 4 ++-- rtl/VX_dmem_controller.v | 1 + 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/rtl/VX_cache/VX_cache_dram_req_arb.v b/rtl/VX_cache/VX_cache_dram_req_arb.v index b720dc63..37264833 100644 --- a/rtl/VX_cache/VX_cache_dram_req_arb.v +++ b/rtl/VX_cache/VX_cache_dram_req_arb.v @@ -140,8 +140,8 @@ module VX_cache_dram_req_arb assign dram_req = dwb_valid || dfqq_req || pref_pop; - assign dram_req_write = dwb_valid; - assign dram_req_read = (dfqq_req && !dwb_valid) || pref_pop; + assign dram_req_write = dwb_valid && dram_req; + assign dram_req_read = ((dfqq_req && !dwb_valid) || pref_pop) && dram_req; assign dram_req_addr = (dwb_valid ? per_bank_dram_wb_req_addr[dwb_bank] : (dfqq_req ? dfqq_req_addr : pref_addr)) & `BASE_ADDR_MASK; assign dram_req_size = BANK_LINE_SIZE_BYTES; assign {dram_req_data} = dwb_valid ? {per_bank_dram_wb_req_data[dwb_bank] }: 0; diff --git a/rtl/VX_dmem_controller.v b/rtl/VX_dmem_controller.v index b033896e..f1b44faa 100644 --- a/rtl/VX_dmem_controller.v +++ b/rtl/VX_dmem_controller.v @@ -155,6 +155,7 @@ module VX_dmem_controller ( // Snoop Request .snp_req (0), .snp_req_addr (0), + .snp_req_delay (0), // Snoop Forward .snp_fwd (),