wu-arch/vortex
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

temp

Browse Source
This commit is contained in:
Sungwoong Ha
2024-02-22 16:31:42 -08:00
parent 5f2b10b8a6
commit be7d87c82d
2 changed files with 33 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
ci/toolchain_env.sh
View File

@@ -24,3 +24,7 @@ export PATH=$SV2V_PATH/bin:$PATH
export YOSYS_PATH=$TOOLDIR/yosys export YOSYS_PATH=$TOOLDIR/yosys
export PATH=$YOSYS_PATH/bin:$PATH export PATH=$YOSYS_PATH/bin:$PATH
export LLVM_VORTEX=$TOOLDIR/llvm-vortex
export POCL_CC_PATH=$TOOLDIR/pocl/compiler
export POCL_RT_PATH=$TOOLDIR/pocl/runtime

31
hw/rtl/core/VX_core.sv
View File

@@ -45,7 +45,7 @@ module VX_core import VX_gpu_pkg::*; #(
output wire [`NUM_REGS-1:0][`XLEN-1:0] sim_wb_value, output wire [`NUM_REGS-1:0][`XLEN-1:0] sim_wb_value,
// Status // Status
output wire busy output wire busy //stays 1 when busy, 0 when done (termination) detect the negative edge
); );
VX_schedule_if schedule_if(); VX_schedule_if schedule_if();
VX_fetch_if fetch_if(); VX_fetch_if fetch_if();
@@ -258,7 +258,7 @@ module VX_core import VX_gpu_pkg::*; #(
`endif `endif
`ifdef PERF_ENABLE `ifdef PERF_ENABLE // expose these perf counter to console using $display, %time; flag: --perf=0?
wire [`CLOG2(DCACHE_NUM_REQS+1)-1:0] perf_dcache_rd_req_per_cycle; wire [`CLOG2(DCACHE_NUM_REQS+1)-1:0] perf_dcache_rd_req_per_cycle;
wire [`CLOG2(DCACHE_NUM_REQS+1)-1:0] perf_dcache_wr_req_per_cycle; wire [`CLOG2(DCACHE_NUM_REQS+1)-1:0] perf_dcache_wr_req_per_cycle;
@@ -333,6 +333,33 @@ module VX_core import VX_gpu_pkg::*; #(
assign pipeline_perf_if.ifetch_latency = perf_icache_lat; assign pipeline_perf_if.ifetch_latency = perf_icache_lat;
assign pipeline_perf_if.load_latency = perf_dcache_lat; assign pipeline_perf_if.load_latency = perf_dcache_lat;
always @(negedge busy) begin
if (!reset) begin
$display("time : %t", $time);
$display("perf_dcache_rd_req_per_cycle: %h", perf_dcache_rd_req_per_cycle);
$display("perf_dcache_wr_req_per_cycle: %h", perf_dcache_wr_req_per_cycle);
$display("perf_dcache_rsp_per_cycle: %h", perf_dcache_rsp_per_cycle);
$display("perf_icache_pending_read_cycle: %h", perf_icache_pending_read_cycle);
$display("perf_dcache_pending_read_cycle: %h", perf_dcache_pending_read_cycle);
$display("perf_icache_pending_reads: %h", perf_icache_pending_reads);
$display("perf_dcache_pending_reads: %h", perf_dcache_pending_reads);
$display("perf_ifetches: %h", perf_ifetches);
$display("perf_loads: %h", perf_loads);
$display("perf_stores: %h", perf_stores);
$display("perf_icache_req_fire: %b", perf_icache_req_fire);
$display("perf_icache_rsp_fire: %b", perf_icache_rsp_fire);
$display("perf_dcache_rd_req_fire: %b", perf_dcache_rd_req_fire);
$display("perf_dcache_rd_req_fire_r: %b", perf_dcache_rd_req_fire_r);
$display("perf_dcache_wr_req_fire: %b", perf_dcache_wr_req_fire);
$display("perf_dcache_wr_req_fire_r: %b", perf_dcache_wr_req_fire_r);
$display("perf_dcache_rsp_fire: %b", perf_dcache_rsp_fire);
$display("scheduler idle: %d", pipeline_perf_if.sched_idles[31:0]);
$display("Instruction: %d",commit_csr_if.instret[31:0]);
$display("Cycle: %d",sched_csr_if.cycles);
end
end
`endif `endif
endmodule endmodule