Vortex 2.0 changes:

+ Microarchitecture optimizations
+ 64-bit support
+ Xilinx FPGA support
+ LLVM-16 support
+ Refactoring and quality control fixes

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cleanup

cleanup

cache bindings and memory perf refactory

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hw unit tests fixes

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minor udpate

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docs/fpga_setup.md

@@ -17,22 +17,16 @@ OPAE Build
 ------------------
 
 The FPGA has to following configuration options:
-- 1 core fpga (fpga-1c)
-- 2 cores fpga (fpga-2c)
-- 4 cores fpga (fpga-4c)
-- 8 cores fpga (fpga-8c)
-- 16 cores fpga (fpga-16c)
-- 32 cores fpga (fpga-32c)
-- 64 cores fpga (fpga-64c)
+- DEVICE_FAMILY=arria10 | stratix10
+- NUM_CORES=#n
 
 Command line:
 
-    $ cd hw/syn/opae
-    $ make fpga-<num-of-cores>c
+    $ cd hw/syn/altera/opae
+    $ PREFIX=test1 TARGET=fpga NUM_CORES=4 make
 
-Example: `make fpga-4c`
-
-A new folder (ex: `build_fpga_4c`) will be created and the build will start and take ~30-480 min to complete.
+A new folder (ex: `test1_xxx_4c`) will be created and the build will start and take ~30-480 min to complete.
+Setting TARGET=ase will build the project for simulation using Intel ASE.
 
 
 OPAE Build Configuration
@@ -45,35 +39,32 @@ The hardware configuration file `/hw/rtl/VX_config.vh` defines all the hardware
 
 You configure the syntesis build from the command line:
 
-    $ CONFIGS="-DPERF_ENABLE -DNUM_THREADS=8" make fpga-4c
+    $ CONFIGS="-DPERF_ENABLE -DNUM_THREADS=8" make
 
 OPAE Build Progress
 -------------------
 
 You could check the last 10 lines in the build log for possible errors until build completion.
 
-    $ tail -n 10 ./build_fpga_<num-of-cores>c/build.log
+    $ tail -n 10 <build_dir>/build.log
 
 Check if the build is still running by looking for quartus_sh, quartus_syn, or quartus_fit programs.
 
     $ ps -u <username>
 
-
 If the build fails and you need to restart it, clean up the build folder using the following command:
 
-    $ make clean-fpga-<num-of-cores>c
-
-Example: `make clean-fpga-4c`
+    $ make clean
 
 The file `vortex_afu.gbs` should exist when the build is done:
 
-    $ ls -lsa ./build_fpga_<num-of-cores>c/vortex_afu.gbs
+    $ ls -lsa <build_dir>/vortex_afu.gbs
 
 
 Signing the bitstream and Programming the FPGA
 ----------------------------------------------
 
-    $ cd ./build_fpga_<num-of-cores>c
+    $ cd <build_dir>
     $ PACSign PR -t UPDATE -H openssl_manager -i vortex_afu.gbs -o vortex_afu_unsigned_ssl.gbs
     $ fpgasupdate vortex_afu_unsigned_ssl.gbs