Vortex 2.0 changes:

+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
2023-10-19 20:51:22 -07:00
parent d69a64c32c
commit c1e168fdbe
1309 changed files with 247412 additions and 311463 deletions
--- a/hw/syn/altera/.gitignore
+++ b/hw/syn/altera/.gitignore
@@ -0,0 +1 @@
+ip_cache/*
--- a/hw/syn/altera/NOTEBOOK
+++ b/hw/syn/altera/NOTEBOOK
@@ -0,0 +1,96 @@
+## Altera synthesis Notebook
+
+## To configure quartus and opae. Run this after logging in.
+source /export/fpga/bin/setup-fpga-env fpga-pac-a10
+
+# Configure a Quartus build area
+afu_synth_setup -s sources.txt build_fpga
+
+# Run Quartus in the vLab batch queue
+cd build_fpga && qsub-synth
+
+# check last 10 lines in build log for possible errors
+tail -n 10 ./build_arria10_fpga_1c/build.log
+
+# Check if the job is submitted to the queue and running. Status should be R 
+qstat | grep <user>
+
+# Constantly monitoring the job submitted to the queue. Stop this using Ctrl+C 
+watch ‘qstat | grep <user>’
+
+#
+## Executing on FPGA
+#
+
+# From the build_fpga directory acquire a fpga node
+qsub-fpga
+
+# Go to the directory whree qsub-synth was run above
+cd $PBS_O_WORKDIR
+
+# Load the image onto an FPGA
+fpgaconf <build>/synth/vortex_afu.gbs
+
+# If this says Multiple ports. Then use --bus with fpgaconf. #bus info can be found by fpgainfo port
+fpgaconf --bus 0xaf <build>/synth/vortex_afu.gbs
+
+# get portid
+fpgainfo port
+
+# Running the Test case 
+cd /driver/tests/basic
+make run-fpga
+
+#
+## ASE build instructions
+#
+source /export/fpga/bin/setup-fpga-env fpga-pac-a10
+
+# Acquire a sever node for running ASE simulations
+qsub-sim
+
+# build ASE runtime
+TARGET=asesim make -C runtime/opae
+
+# build ASE hw image
+PREFIX=build_base CONFIGS="-DEXT_F_DISABLE -DL1_DISABLE -DSM_DISABLE -DNUM_WARPS=2 -DNUM_THREADS=2" TARGET=asesim make
+
+# ASE test runs
+./run_ase.sh build_base_arria10_asesim_1c/synth ../../../../tests/regression/basic/basic -n1 -t0
+./run_ase.sh build_base_arria10_asesim_1c/synth ../../../../tests/regression/basic/basic -n1 -t1
+./run_ase.sh build_base_arria10_asesim_1c/synth ../../../../tests/regression/basic/basic -n16
+./run_ase.sh build_base_arria10_asesim_1c/synth ../../../../tests/regression/demo/demo -n16
+./run_ase.sh build_base_arria10_asesim_1c/synth ../../../../tests/regression/dogfood/dogfood -n16
+./run_ase.sh build_base_arria10_asesim_1c/synth ../../../../tests/opencl/vecadd/vecadd
+./run_ase.sh build_base_arria10_asesim_1c/synth ../../../../tests/opencl/sgemm/sgemm -n4
+
+# modify "vsim_run.tcl" to dump VCD trace
+vcd file trace.vcd
+vcd add -r /*/Vortex/hw/rtl/* 
+run -all
+
+# compress FPGA output files
+tar -zcvf output_files_1c.tar.gz `find ./build_fpga_1c -type f \( -iname \*.rpt -o -iname \*.txt -o -iname \*summary -o -iname \*.log \)`
+
+# compress log trace
+tar -zcvf run.log.tar.gz run.log
+tar -cvjf trace.vcd.tar.bz2 trace.vcd run.log
+tar -cvjf trace.vcd.tar.bz2 build_arria10_ase_1c/synth/work/run.log build_arria10_ase_1c/work/trace.vcd
+
+# decompress log trace
+tar -zxvf vortex.vcd.tar.gz
+tar -xvf vortex.vcd.tar.bz2
+
+# building FPGA images
+make all
+
+# running benchmarks on FPGA
+fpgaconf --bus 0xaf <build>/synth/vortex_afu.gbs
+TARGET=fpga ./ci/blackbox.sh --driver=opae --app=sgemm
+
+# quick off synthesis
+make core
+
+# generate reports
+./report_timing.sh <project_dir> <project_name>
+./report_area.sh <project_dir> <project_name>
--- a/hw/syn/altera/analyze_timing.sh
+++ b/hw/syn/altera/analyze_timing.sh
@@ -0,0 +1,17 @@
+#!/bin/bash
+
+# Timing Analysis
+# first argument is the project name
+
+SCRIPT_DIR="$(dirname "${BASH_SOURCE[0]}")"
+SCRIPT_DIR="$(realpath "${SCRIPT_DIR}")"
+
+PROJECT_DIR=$1
+PROJECT=$2
+MODE=${3-fit}
+
+echo "Running quartus_sh -t $SCRIPT_DIR/report_area.tcl $PROJECT $MODE in $PROJECT_DIR ..."
+
+pushd $PROJECT_DIR
+quartus_sta -t $SCRIPT_DIR/analyze_timing.tcl $PROJECT $MODE
+popd
--- a/hw/syn/altera/analyze_timing.tcl
+++ b/hw/syn/altera/analyze_timing.tcl
@@ -0,0 +1,145 @@
+# Copyright © 2019-2023
+# 
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+# http://www.apache.org/licenses/LICENSE-2.0
+# 
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+set ProjectName [lindex $argv 0]
+set SynMode     [lindex $argv 1]
+if { $SynMode == "map" } {
+	set FileSuffix "map"
+} else {
+	set FileSuffix "fit"
+}
+
+proc do_timing_checks { ProjectName FileSuffix } {
+	# Validate timing DRC rules
+	# REF: http://quartushelp.altera.com/14.0/mergedProjects/tafs/tafs/tcl_pkg_sta_ver_1.0_cmd_check_timing.htm
+	check_timing -include {no_clock multiple_clock loops latches } -file $ProjectName.$FileSuffix.timing.check_errors.html
+	# NOTE: metastability requires QSF setting of Synchronizer Identification = Auto
+	# can also embed in Verilog: (* altera_attribute = "-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS" *) 
+	report_metastability -nchains 100 -file $ProjectName.$FileSuffix.timing.check_metastability.html
+}
+
+proc do_timing_detailed_slackpaths { ProjectName FileSuffix SynMode } {
+	# Detailed info for top 100 setup/hold paths
+	if { $SynMode == "fit" } {
+		set npaths_detailed 200
+		set npaths_pairs    10000
+		set npaths_maxslack 0.2
+		# Create html reports showing details of each of the top 100 paths (creates html index + subdir with css/images/etc)
+		set ExtraRTArgs "-show_routing"
+		report_timing -setup    -nworst $npaths_detailed -detail full_path $ExtraRTArgs -file $ProjectName.$FileSuffix.timing.setup.html
+		report_timing -hold     -nworst $npaths_detailed -detail full_path $ExtraRTArgs -file $ProjectName.$FileSuffix.timing.hold.html
+		report_timing -recovery -nworst $npaths_detailed -detail full_path $ExtraRTArgs -file $ProjectName.$FileSuffix.timing.recovery.html
+		report_timing -removal  -nworst $npaths_detailed -detail full_path $ExtraRTArgs -file $ProjectName.$FileSuffix.timing.removal.html
+
+		# Create txt with (slack,src,dst) for cross-seed comparisons
+		report_timing -setup    -nworst $npaths_pairs -less_than_slack $npaths_maxslack -detail summary -pairs_only -file $ProjectName.$FileSuffix.timing_paths.setup.txt
+		report_timing -hold     -nworst $npaths_pairs -less_than_slack $npaths_maxslack -detail summary -pairs_only -file $ProjectName.$FileSuffix.timing_paths.hold.txt
+		report_timing -recovery -nworst $npaths_pairs -less_than_slack $npaths_maxslack -detail summary -pairs_only -file $ProjectName.$FileSuffix.timing_paths.recovery.txt
+		report_timing -removal  -nworst $npaths_pairs -less_than_slack $npaths_maxslack -detail summary -pairs_only -file $ProjectName.$FileSuffix.timing_paths.removal.txt
+
+		# Histogram of setup/hold slacks across all clocks
+		set allclocks [get_clocks]
+		foreach_in_collection curclk $allclocks {
+			set clkname [ get_clock_info -name $curclk ]
+			create_slack_histogram -clock_name $clkname -setup -file $ProjectName.$FileSuffix.timing_histogram.$clkname.setup.html
+			#create_slack_histogram -clock_name $clkname -hold  -file $ProjectName.$FileSuffix.timing_histogram.$clkname.hold.html
+		}
+	# Just emit simple setup paths if analyzing MAP netlist
+	} else {
+		set ExtraRTArgs ""
+		report_timing -setup -nworst 100 -detail full_path $ExtraRTArgs -file $ProjectName.$FileSuffix.timing.setup.html
+	}
+}
+
+proc do_timing_summary { ProjectName FileSuffix } {
+	# Save summary into to single txt file
+	create_timing_summary -setup         -file $ProjectName.$FileSuffix.timing.summary.txt
+	create_timing_summary -hold  -append -file $ProjectName.$FileSuffix.timing.summary.txt
+	report_clocks -summary       -append -file $ProjectName.$FileSuffix.timing.summary.txt
+	report_clock_fmax_summary    -append -file $ProjectName.$FileSuffix.timing.summary.txt
+}
+
+proc do_timing_detailed_bottleneck_paths { ProjectName FileSuffix } {
+	# Create bottleneck timing analysis with different metrics to analyze setup paths
+	#proc custom_metric_fanins {arg} {
+	#	upvar $arg metric
+	#	set rating $metric(num_fanins)
+	#	return $rating
+	#}
+	#report_bottleneck -cmetric custom_metric_fanins -file timing.bottlneck.num_fanins.html $tpaths
+	set tpaths [ get_timing_paths -nworst 1000 -setup ]
+	set tns_paths [ report_bottleneck -metric tns         $tpaths -stdout ]
+	set np_paths  [ report_bottleneck -metric num_paths   $tpaths -stdout ] 
+	set nfp_paths [ report_bottleneck -metric num_fpaths  $tpaths -stdout ]
+	set nfo_paths [ report_bottleneck -metric num_fanouts $tpaths -stdout ]
+	set nfi_paths [ report_bottleneck -metric num_fanins  $tpaths -stdout ]
+
+	set fo [ open "$ProjectName.$FileSuffix.timing.setup.bottlenecks.txt" "w" ]
+	puts $fo "Bottlenecks by TNS"
+	puts $fo $tns_paths
+
+	puts $fo "Bottlenecks by NumPaths"
+	puts $fo $np_paths
+
+	puts $fo "Bottlenecks by NumFailingPaths"
+	puts $fo $nfp_paths
+
+	puts $fo "Bottlenecks by NumFanOuts"
+	puts $fo $nfo_paths
+
+	puts $fo "Bottlenecks by NumFanIns"
+	puts $fo $nfi_paths
+}
+
+# Iterate over all known operating conditions
+# 3_H2_slow_850mv_100c / 3_H2_slow_850mv_100c / 3_H2_slow_850mv_0c / MIN_fast_850mv_100c / MIN_fast_850mv_0c
+#foreach_in_collection oc [get_available_operating_conditions] {
+#	set_operating_conditions $oc
+#	post_message "Setting Operating Conditions $oc"
+#	update_timing_netlist
+#	report_timing -setup    -npaths 100 -file $ProjectName.timing.setup.html
+#	report_timing -hold     -npaths 100 -file $ProjectName.timing.hold.html
+#}
+
+project_open $ProjectName
+
+# => allows comparison of raw logic vs impact of routing delays
+if { $SynMode == "map" } {
+	create_timing_netlist -post_map
+	read_sdc
+	update_timing_netlist
+
+	do_timing_detailed_slackpaths $ProjectName $FileSuffix $SynMode
+	do_timing_summary $ProjectName $FileSuffix
+
+	delete_timing_netlist
+
+# normal post-par analysis (includes routing congestion/physical placement constraints)
+} else {	
+	create_timing_netlist
+	read_sdc
+	update_timing_netlist
+	
+	# Iterate over a single worst-case operating condition (grade/speed pre-selected based on netlist)
+	set_operating_conditions -voltage 900 -temperature 100
+	update_timing_netlist
+	
+	do_timing_checks $ProjectName $FileSuffix
+	do_timing_detailed_slackpaths $ProjectName $FileSuffix $SynMode
+	do_timing_detailed_bottleneck_paths $ProjectName $FileSuffix
+	do_timing_summary $ProjectName $FileSuffix
+	
+	delete_timing_netlist
+}
+
+project_close
--- a/hw/syn/altera/ip_gen.sh
+++ b/hw/syn/altera/ip_gen.sh
@@ -0,0 +1,50 @@
+#!/bin/bash
+
+# Copyright © 2019-2023
+# 
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+# http://www.apache.org/licenses/LICENSE-2.0
+# 
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+
+BUILD_DIR=$1
+
+EXP_BITS=8
+MAN_BITS=23
+FBITS="f$(($EXP_BITS + $MAN_BITS + 1))"
+
+CMD_POLY_EVAL_PATH=$QUARTUS_HOME/dspba/backend/linux64
+
+OPTIONS="-target $DEVICE_FAMILY -noChanValid -enable -enableHardFP 1 -faithfulRounding -speedgrade 2 -frequency 200 -lang verilog -printMachineReadable"
+
+export LD_LIBRARY_PATH=$CMD_POLY_EVAL_PATH:$LD_LIBRARY_PATH
+
+CMD="$CMD_POLY_EVAL_PATH/cmdPolyEval $OPTIONS"
+
+mkdir -p $BUILD_DIR
+pushd $BUILD_DIR
+
+echo Generating IP cores for $FBITS
+{
+    #$CMD -name acl_fadd FPAdd $EXP_BITS $MAN_BITS
+    #$CMD -name acl_fsub FPSub $EXP_BITS $MAN_BITS
+    #$CMD -name acl_fmul FPMul $EXP_BITS $MAN_BITS
+    $CMD -name acl_fmadd FPMultAdd $EXP_BITS $MAN_BITS
+    $CMD -name acl_fdiv  FPDiv     $EXP_BITS $MAN_BITS 0
+    $CMD -name acl_fsqrt FPSqrt    $EXP_BITS $MAN_BITS
+    #$CMD -name acl_ftoi FPToFXP $EXP_BITS $MAN_BITS 32 0 1
+    #$CMD -name acl_ftou FPToFXP $EXP_BITS $MAN_BITS 32 0 0
+    #$CMD -name acl_itof FXPToFP 32 0 1 $EXP_BITS $MAN_BITS
+    #$CMD -name acl_utof FXPToFP 32 0 0 $EXP_BITS $MAN_BITS
+} > ip_gen.log 2>&1
+
+cp $QUARTUS_HOME/dspba/backend/Libraries/sv/base/dspba_library_ver.sv dspba_delay_ver.sv
+
+popd
--- a/hw/syn/altera/opae/.gitignore
+++ b/hw/syn/altera/opae/.gitignore
@@ -0,0 +1 @@
+build*/*
--- a/hw/syn/altera/opae/Makefile
+++ b/hw/syn/altera/opae/Makefile
@@ -0,0 +1,148 @@
+DEVICE_FAMILY ?= arria10
+XLEN ?= 32
+PREFIX ?= build$(XLEN)
+TARGET ?= fpga
+NUM_CORES ?= 1
+
+SCRIPT_DIR = ../../../scripts
+RTL_DIR = ../../../rtl
+DPI_DIR = ../../../dpi
+AFU_DIR = $(RTL_DIR)/afu/opae
+THIRD_PARTY_DIR = ../../../../third_party
+IP_CACHE_DIR = ../ip_cache/$(DEVICE_FAMILY)
+
+BUILD_DIR = $(PREFIX)_$(DEVICE_FAMILY)_$(TARGET)_$(NUM_CORES)c
+
+ifeq ($(shell which qsub-synth),)
+	RUN_SYNTH=$(OPAE_PLATFORM_ROOT)/bin/run.sh > build.log 2>&1 &
+else
+	RUN_SYNTH=qsub-synth
+endif
+
+# control RTL debug tracing states
+DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_PIPELINE  
+DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_ICACHE
+DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_DCACHE
+DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_MEM
+DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_BANK 
+DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_MSHR
+DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_TAG
+DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_DATA
+DBG_TRACE_FLAGS += -DDBG_TRACE_AFU
+DBG_TRACE_FLAGS += -DDBG_TRACE_GBAR
+
+# Control logic analyzer monitors
+DBG_SCOPE_FLAGS += -DDBG_SCOPE_AFU
+DBG_SCOPE_FLAGS += -DDBG_SCOPE_ISSUE
+DBG_SCOPE_FLAGS += -DDBG_SCOPE_FETCH
+DBG_SCOPE_FLAGS += -DDBG_SCOPE_LSU
+DBG_SCOPE_FLAGS += -DDBG_SCOPE_MSCHED
+
+ifeq ($(DEVICE_FAMILY), stratix10)
+    CONFIGS += -DALTERA_S10
+endif
+ifeq ($(DEVICE_FAMILY), arria10)
+    CONFIGS += -DALTERA_A10
+endif
+
+# cluster configuration
+CONFIGS_1c  := -DNUM_CLUSTERS=1 -DNUM_CORES=1
+CONFIGS_2c  := -DNUM_CLUSTERS=1 -DNUM_CORES=2
+CONFIGS_4c  := -DNUM_CLUSTERS=1 -DNUM_CORES=4
+CONFIGS_8c	:= -DNUM_CLUSTERS=1 -DNUM_CORES=8
+CONFIGS_16c	:= -DNUM_CLUSTERS=1 -DNUM_CORES=16 -DL2_ENABLE
+CONFIGS_32c := -DNUM_CLUSTERS=2 -DNUM_CORES=16 -DL2_ENABLE
+CONFIGS_64c := -DNUM_CLUSTERS=4 -DNUM_CORES=16 -DL2_ENABLE
+CONFIGS += $(CONFIGS_$(NUM_CORES)c)
+
+# include paths
+FPU_INCLUDE = -I$(RTL_DIR)/fpu
+ifneq (,$(findstring FPU_FPNEW,$(CONFIGS)))
+	FPU_INCLUDE += -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -J$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -J$(THIRD_PARTY_DIR)/fpnew/src
+endif
+RTL_INCLUDE = -I$(RTL_DIR) -I$(DPI_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/mem -I$(RTL_DIR)/cache -I$(AFU_DIR) -I$(IP_CACHE_DIR)
+RTL_INCLUDE += $(FPU_INCLUDE)
+
+# compilation flags
+CFLAGS += -DSYNTHESIS -DQUARTUS
+CFLAGS += -DXLEN_$(XLEN)
+CFLAGS += $(CONFIGS)
+CFLAGS += $(RTL_INCLUDE)
+
+ifneq ($(TARGET), fpga)
+	CFLAGS += -DSIMULATION
+endif
+
+# Debugigng
+ifdef DEBUG
+	ifeq ($(TARGET), fpga)
+		CFLAGS += -DNDEBUG -DSCOPE $(DBG_SCOPE_FLAGS)
+		SCOPE_JSON += $(BUILD_DIR)/scope.json
+	else
+		CFLAGS += $(DBG_TRACE_FLAGS)
+	endif
+else    
+	CFLAGS += -DNDEBUG
+endif
+
+# Enable scope analyzer
+ifdef SCOPE
+	CFLAGS += -DSCOPE
+endif
+
+# Enable perf counters
+ifdef PERF
+	CFLAGS += -DPERF_ENABLE
+endif
+
+# ast dump flags
+XML_CFLAGS = $(filter-out -DSYNTHESIS -DQUARTUS, $(CFLAGS)) -I$(AFU_DIR)/ccip -I$(DPI_DIR) -DNOPAE
+
+all: swconfig ip-gen setup build
+
+ip-gen: $(IP_CACHE_DIR)/ip-gen.log
+$(IP_CACHE_DIR)/ip-gen.log:
+	../ip_gen.sh $(IP_CACHE_DIR)
+
+swconfig: vortex_afu.h
+vortex_afu.h: vortex_afu.json
+	afu_json_mgr json-info --afu-json=$^ --c-hdr=$@
+
+$(BUILD_DIR)/setup.cfg:
+	mkdir -p $(BUILD_DIR); cp setup.cfg $(BUILD_DIR)/setup.cfg
+
+$(BUILD_DIR)/vortex_afu.qsf:
+	mkdir -p $(BUILD_DIR); cp vortex_afu.qsf $(BUILD_DIR)/vortex_afu.qsf
+
+$(BUILD_DIR)/vortex_afu.json:
+	mkdir -p $(BUILD_DIR); cp vortex_afu.json $(BUILD_DIR)/vortex_afu.json
+
+gen-sources: $(BUILD_DIR)/sources.txt
+$(BUILD_DIR)/sources.txt:
+	mkdir -p $(BUILD_DIR); $(SCRIPT_DIR)/gen_sources.sh $(CFLAGS) -C$(BUILD_DIR)/src -O$(BUILD_DIR)/sources.txt
+
+setup: $(BUILD_DIR)/synth
+$(BUILD_DIR)/synth: $(BUILD_DIR)/sources.txt $(BUILD_DIR)/setup.cfg $(BUILD_DIR)/vortex_afu.qsf $(BUILD_DIR)/vortex_afu.json
+ifeq ($(TARGET), asesim)
+	afu_sim_setup -s $(BUILD_DIR)/setup.cfg $(BUILD_DIR)/synth
+else
+	afu_synth_setup -s $(BUILD_DIR)/setup.cfg $(BUILD_DIR)/synth
+endif	
+
+build: ip-gen setup $(SCOPE_JSON)
+ifeq ($(TARGET), asesim)
+	make -C $(BUILD_DIR)/synth > $(BUILD_DIR)/synth/build.log 2>&1 &
+else
+	cd $(BUILD_DIR)/synth && $(RUN_SYNTH)
+endif
+
+gen-ast: $(BUILD_DIR)/vortex.xml
+$(BUILD_DIR)/vortex.xml: setup
+	verilator --xml-only -O0 $(XML_CFLAGS) vortex_afu.sv --xml-output $(BUILD_DIR)/vortex.xml
+
+scope-json: $(BUILD_DIR)/scope.json
+$(BUILD_DIR)/scope.json: $(BUILD_DIR)/vortex.xml
+	$(SCRIPT_DIR)/scope.py $(BUILD_DIR)/vortex.xml -o $(BUILD_DIR)/scope.json
+
+clean:  
+	rm -rf vortex_afu.h $(BUILD_DIR)
--- a/hw/syn/altera/opae/fpga_prog.sh
+++ b/hw/syn/altera/opae/fpga_prog.sh
@@ -0,0 +1,19 @@
+#!/bin/bash
+
+# Copyright © 2019-2023
+# 
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+# http://www.apache.org/licenses/LICENSE-2.0
+# 
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+# FPGA programming
+# first argument is the bitstream
+
+fpgaconf --bus 0xaf $1
--- a/hw/syn/altera/opae/run_ase.sh
+++ b/hw/syn/altera/opae/run_ase.sh
@@ -0,0 +1,52 @@
+#!/bin/bash
+
+# Copyright © 2019-2023
+# 
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+# http://www.apache.org/licenses/LICENSE-2.0
+# 
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+SCRIPT_DIR="$( cd "$( dirname "${BASH_SOURCE[0]}" )" >/dev/null 2>&1 && pwd )"
+
+BUILD_DIR=$1
+
+PROGRAM=$(basename "$2")
+PROGRAM_DIR=`dirname $2`
+
+VORTEX_RT_PATH=$SCRIPT_DIR/../../../../runtime
+
+# Export ASE_WORKDIR variable
+export ASE_WORKDIR=$SCRIPT_DIR/$BUILD_DIR/work
+
+shift 2
+
+# cleanup incomplete runs
+rm -f $ASE_WORKDIR/.app_lock.pid 
+rm -f $ASE_WORKDIR/.ase_ready.pid
+rm -f $SCRIPT_DIR/$BUILD_DIR/nohup.out
+
+# Start Simulator in background
+pushd $SCRIPT_DIR/$BUILD_DIR 
+echo "  [DBG]  starting ASE simnulator (stdout saved to '$SCRIPT_DIR/$BUILD_DIR/nohup.out')"
+nohup make sim & 
+popd
+
+# Wait for simulator readiness
+# When .ase_ready is created in the $ASE_WORKDIR, ASE is ready for simulation
+while [ ! -f $ASE_WORKDIR/.ase_ready.pid ]
+do
+  sleep 1
+done
+
+# run application
+pushd $PROGRAM_DIR
+echo "  [DBG]  running ./$PROGRAM $*"
+ASE_LOG=0 LD_LIBRARY_PATH=$POCL_RT_PATH/lib:$VORTEX_RT_PATH/opae:$LD_LIBRARY_PATH ./$PROGRAM $*
+popd
--- a/hw/syn/altera/opae/setup.cfg
+++ b/hw/syn/altera/opae/setup.cfg
@@ -0,0 +1,4 @@
+vortex_afu.json
+QI:vortex_afu.qsf
+
+C:sources.txt
--- a/hw/syn/altera/opae/vortex_afu.json
+++ b/hw/syn/altera/opae/vortex_afu.json
@@ -0,0 +1,54 @@
+{
+   "version": 1,
+   "afu-image": {
+      "power": 0,
+      "clock-frequency-high": "auto-200",
+      "clock-frequency-low":  "auto-100",
+      
+      "cmd-mem-read":     1,
+      "cmd-mem-write":    2,
+      "cmd-run":          3,
+      "cmd-dcr-write":    4,
+      "cmd-max-value":    4,
+      
+      "mmio-cmd-type":    10,     
+      "mmio-cmd-arg0":    12,
+      "mmio-cmd-arg1":    14,
+      "mmio-cmd-arg2":    16,          
+      "mmio-status":      18,   
+      "mmio-scope-read":  20,
+      "mmio-scope-write": 22,
+      "mmio-dev-caps":    24,
+      "mmio-isa-caps":    26,
+
+      "afu-top-interface":
+         {
+            "class": "ccip_std_afu_avalon_mm",
+            "module-ports" :
+               [
+                  {
+                     "class": "cci-p",
+                     "params":
+                        {
+                           "clock": "uClk_usr"
+                        }
+                  },
+                  {
+                     "class": "local-memory",
+                     "params":
+                        {
+                           "clock": "uClk_usr"
+                        }
+                  }
+               ]
+         },
+      "accelerator-clusters":
+         [
+            {
+               "name": "vortex_afu",
+               "total-contexts": 1,
+               "accelerator-type-uuid": "35f9452b-25c2-434c-93d5-6f8c60db361c"
+            }
+         ]
+   }
+}
--- a/hw/syn/altera/opae/vortex_afu.qsf
+++ b/hw/syn/altera/opae/vortex_afu.qsf
@@ -0,0 +1,36 @@
+
+# Analysis & Synthesis Assignments
+
+set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
+set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009
+set_global_assignment -name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS ON
+set_global_assignment -name MESSAGE_DISABLE 16818
+set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
+
+set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE PERFORMANCE"
+
+set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
+set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 2.0
+set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
+
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
+
+set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
+set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON
+set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON
+
+#set_global_assignment -name USE_HIGH_SPEED_ADDER ON
+#set_global_assignment -name MUX_RESTRUCTURE ON
+#set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
+#set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING "FORCE ALL TILES WITH FAILING TIMING PATHS TO HIGH SPEED"
+#set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
+#set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
+
+#set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+#set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
+#set_global_assignment -name SEED 1
--- a/hw/syn/altera/power_play.sh
+++ b/hw/syn/altera/power_play.sh
@@ -0,0 +1,6 @@
+#!/bin/bash
+
+# Generate Power Report
+# first argument is the project name
+
+quartus_pow --input_vcd=trace.vcd --vcd_filter_glitches=on --default_input_io_toggle_rate=10000transitions/s $1
--- a/hw/syn/altera/quartus/.gitignore
+++ b/hw/syn/altera/quartus/.gitignore
@@ -0,0 +1,29 @@
+/unittest/*
+!/unittest/Makefile
+
+/smem/*
+!/smem/Makefile
+
+/cache/*
+!/cache/Makefile
+
+/vortex/*
+!/vortex/Makefile
+
+/pipeline/*
+!/pipeline/Makefile
+
+/core/*
+!/core/Makefile
+
+/top/*
+!/top/Makefile
+
+/top-gfx/*
+!/top-gfx/Makefile
+
+/test/*
+!/test/Makefile
+
+/fpu/*
+!/fpu/Makefile
--- a/hw/syn/altera/quartus/Makefile
+++ b/hw/syn/altera/quartus/Makefile
@@ -0,0 +1,61 @@
+PREFIX ?= build
+
+BUILD_DIR=$(PREFIX)_$(DEVICE_FAMILY)
+
+IP_CACHE_DIR=../ip_cache/$(DEVICE_FAMILY)
+
+.PHONY: dogfood unittest pipeline smem cache fpu core vortex top test
+
+ip-gen: $(IP_CACHE_DIR)/ip_gen.log
+$(IP_CACHE_DIR)/ip_gen.log:
+	../ip_gen.sh $(IP_CACHE_DIR)
+
+dogfood:
+	mkdir -p dogfood/$(BUILD_DIR)
+	cp dogfood/Makefile dogfood/$(BUILD_DIR)
+	$(MAKE) -C dogfood/$(BUILD_DIR) clean && $(MAKE) -C dogfood/$(BUILD_DIR) > dogfood/$(BUILD_DIR)/build.log 2>&1 &
+
+unittest:
+	mkdir -p unittest/$(BUILD_DIR)
+	cp unittest/Makefile unittest/$(BUILD_DIR)
+	$(MAKE) -C unittest/$(BUILD_DIR) clean && $(MAKE) -C unittest/$(BUILD_DIR) > unittest/$(BUILD_DIR)/build.log 2>&1 &
+
+pipeline:
+	mkdir -p pipeline/$(BUILD_DIR)
+	cp pipeline/Makefile pipeline/$(BUILD_DIR)
+	$(MAKE) -C pipeline/$(BUILD_DIR) clean && $(MAKE) -C pipeline/$(BUILD_DIR) > pipeline/$(BUILD_DIR)/build.log 2>&1 &
+
+smem:
+	mkdir -p smem/$(BUILD_DIR)
+	cp smem/Makefile smem/$(BUILD_DIR)
+	$(MAKE) -C smem/$(BUILD_DIR) clean && $(MAKE) -C smem/$(BUILD_DIR) > smem/$(BUILD_DIR)/build.log 2>&1 &
+
+cache:
+	mkdir -p cache/$(BUILD_DIR)
+	cp cache/Makefile cache/$(BUILD_DIR)
+	$(MAKE) -C cache/$(BUILD_DIR) clean && $(MAKE) -C cache/$(BUILD_DIR) > cache/$(BUILD_DIR)/build.log 2>&1 &
+
+fpu: ip-gen
+	mkdir -p fpu/$(BUILD_DIR)
+	cp fpu/Makefile fpu/$(BUILD_DIR)
+	$(MAKE) -C fpu/$(BUILD_DIR) clean && $(MAKE) -C fpu/$(BUILD_DIR) > fpu/$(BUILD_DIR)/build.log 2>&1 &
+
+core:
+	mkdir -p core/$(BUILD_DIR)
+	cp core/Makefile core/$(BUILD_DIR)
+	$(MAKE) -C core/$(BUILD_DIR) clean && $(MAKE) -C core/$(BUILD_DIR) > core/$(BUILD_DIR)/build.log 2>&1 &
+
+vortex: ip-gen
+	mkdir -p vortex/$(BUILD_DIR)
+	cp vortex/Makefile vortex/$(BUILD_DIR)
+	$(MAKE) -C vortex/$(BUILD_DIR) clean && $(MAKE) -C vortex/$(BUILD_DIR) > vortex/$(BUILD_DIR)/build.log 2>&1 &
+
+top: ip-gen
+	mkdir -p top/$(BUILD_DIR)
+	cp top/Makefile top/$(BUILD_DIR)
+	$(MAKE) -C top/$(BUILD_DIR) clean && $(MAKE) -C top/$(BUILD_DIR) > top/$(BUILD_DIR)/build.log 2>&1 &
+
+test: ip-gen
+	mkdir -p test/$(BUILD_DIR)
+	cp test/Makefile test/$(BUILD_DIR)
+	$(MAKE) -C test/$(BUILD_DIR) clean && $(MAKE) -C test/$(BUILD_DIR) > test/$(BUILD_DIR)/build.log 2>&1 &
--- a/hw/syn/altera/quartus/cache/Makefile
+++ b/hw/syn/altera/quartus/cache/Makefile
@@ -0,0 +1,7 @@
+PROJECT = VX_cache_cluster_top
+TOP_LEVEL_ENTITY = $(PROJECT)
+SRC_FILE = VX_cache_cluster.sv
+
+include ../../common.mk
+
+RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/mem -I$(RTL_DIR)/cache
--- a/hw/syn/altera/quartus/common.mk
+++ b/hw/syn/altera/quartus/common.mk
@@ -0,0 +1,99 @@
+RTL_DIR = ../../../../../rtl
+AFU_DIR = $(RTL_DIR)/afu/opae
+THIRD_PARTY_DIR = ../../../../../../third_party
+IP_CACHE_DIR = ../../../ip_cache/$(DEVICE_FAMILY)
+SCRIPT_DIR = ../../../../../scripts
+THIRD_PARTY_DIR = ../../../../../../third_party
+
+ifeq ($(DEVICE_FAMILY), stratix10)
+    FAMILY = "Stratix 10"
+	DEVICE = 1SX280HN2F43E2VG
+endif
+ifeq ($(DEVICE_FAMILY), arria10)
+    FAMILY = "Arria 10"
+	DEVICE = 10AX115N3F40E2SG
+endif
+
+CONFIGS += -DNDEBUG
+CONFIGS += -DQUARTUS
+CONFIGS += -DSYNTHESIS
+CONFIGS += -DNOGLOBALS
+
+PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
+
+# Executable Configuration
+SYN_ARGS = --parallel --read_settings_files=on
+FIT_ARGS = --parallel --part=$(DEVICE) --read_settings_files=on
+ASM_ARGS =
+STA_ARGS = --parallel --do_report_timing
+POW_ARGS = --no_input_file --default_input_io_toggle_rate=60% --default_toggle_rate=20% --use_vectorless_estimation=off
+
+# Build targets
+all: gen-sources $(PROJECT).sta.rpt $(PROJECT).pow.rpt
+
+gen-sources: src
+src:
+	mkdir -p src
+	$(SCRIPT_DIR)/gen_sources.sh $(CONFIGS) $(RTL_INCLUDE) -P -Csrc
+
+syn: $(PROJECT).syn.rpt
+
+fit: $(PROJECT).fit.rpt
+
+asm: $(PROJECT).asm.rpt
+
+sta: $(PROJECT).sta.rpt
+
+pow: $(PROJECT).pow.rpt
+
+smart: smart.log
+
+# Target implementations
+STAMP = echo done >
+
+$(PROJECT).syn.rpt: smart.log syn.chg
+	quartus_syn $(SYN_ARGS) $(PROJECT)
+	$(STAMP) fit.chg
+
+$(PROJECT).fit.rpt: smart.log fit.chg $(PROJECT).syn.rpt
+	quartus_fit $(FIT_ARGS) $(PROJECT)
+	$(STAMP) asm.chg
+	$(STAMP) sta.chg
+
+$(PROJECT).asm.rpt: smart.log asm.chg $(PROJECT).fit.rpt
+	quartus_asm $(ASM_ARGS) $(PROJECT)
+	$(STAMP) pow.chg
+
+$(PROJECT).sta.rpt: smart.log sta.chg $(PROJECT).fit.rpt
+	quartus_sta $(STA_ARGS) $(PROJECT)
+
+$(PROJECT).pow.rpt: smart.log pow.chg $(PROJECT).asm.rpt
+	quartus_pow $(POW_ARGS) $(PROJECT)
+
+smart.log: $(PROJECT_FILES)
+	quartus_sh --determine_smart_action $(PROJECT) > smart.log
+
+# Project initialization
+$(PROJECT_FILES): gen-sources
+	quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../../project.sdc -inc "src"
+	
+syn.chg:
+	$(STAMP) syn.chg
+
+fit.chg:
+	$(STAMP) fit.chg
+
+sta.chg:
+	$(STAMP) sta.chg
+
+asm.chg:
+	$(STAMP) asm.chg
+
+pow.chg:
+	$(STAMP) pow.chg
+
+program: $(PROJECT).sof
+	quartus_pgm --no_banner --mode=jtag -o "$(PROJECT).sof"
+	
+clean:
+	rm -rf src bin *.rpt *.chg *.qsf *.qpf *.qws *.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox
--- a/hw/syn/altera/quartus/core/Makefile
+++ b/hw/syn/altera/quartus/core/Makefile
@@ -0,0 +1,14 @@
+PROJECT = VX_core_top
+TOP_LEVEL_ENTITY = $(PROJECT)
+SRC_FILE = VX_core.sv
+
+include ../../common.mk
+
+#CONFIGS += -DNUM_WARPS=32
+#CONFIGS += -DNUM_THREADS=32
+
+FPU_INCLUDE = -I$(RTL_DIR)/fpu
+ifneq (,$(findstring FPU_FPNEW,$(CONFIGS)))
+	FPU_INCLUDE += -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -J$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -J$(THIRD_PARTY_DIR)/fpnew/src
+endif
+RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/mem -I$(RTL_DIR)/cache -I$(IP_CACHE_DIR) $(FPU_INCLUDE)
--- a/hw/syn/altera/quartus/fpu/Makefile
+++ b/hw/syn/altera/quartus/fpu/Makefile
@@ -0,0 +1,11 @@
+PROJECT = VX_fpu_dsp
+TOP_LEVEL_ENTITY = $(PROJECT)
+SRC_FILE = $(PROJECT).sv
+
+include ../../common.mk
+
+FPU_INCLUDE = -I$(RTL_DIR)/fpu
+ifneq (,$(findstring FPU_FPNEW,$(CONFIGS)))
+	FPU_INCLUDE += -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -J$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -J$(THIRD_PARTY_DIR)/fpnew/src
+endif
+RTL_INCLUDE = $(FPU_INCLUDE) -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(IP_CACHE_DIR)
--- a/hw/syn/altera/quartus/project.sdc
+++ b/hw/syn/altera/quartus/project.sdc
@@ -0,0 +1 @@
+create_clock -name {clk} -period "200 MHz" -waveform { 0.000 1.0 } [get_ports {clk}]
--- a/hw/syn/altera/quartus/project.tcl
+++ b/hw/syn/altera/quartus/project.tcl
@@ -0,0 +1,104 @@
+# Copyright © 2019-2023
+# 
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+# http://www.apache.org/licenses/LICENSE-2.0
+# 
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+load_package flow
+package require cmdline
+
+set options { 
+    { "project.arg" "" "Project name" } 
+    { "family.arg" "" "Device family name" } 
+    { "device.arg" "" "Device name" } 
+    { "top.arg" "" "Top level module" }     
+    { "src.arg" "" "Verilog source file" } 
+    { "inc.arg" "" "Include path (optional)" } 
+    { "sdc.arg" "" "Timing Design Constraints file (optional)" } 
+    { "set.arg" "" "Macro value (optional)" } 
+}
+
+set q_args_orig $quartus(args)
+
+array set opts [::cmdline::getoptions quartus(args) $options]
+
+# Verify required parameters
+set requiredParameters {project family device top src}
+foreach p $requiredParameters {
+    if {$opts($p) == ""} {
+        puts stderr "Missing required parameter: -$p"
+        exit 1
+    }
+}
+
+project_new $opts(project) -overwrite
+
+set_global_assignment -name FAMILY $opts(family)
+set_global_assignment -name DEVICE $opts(device)
+set_global_assignment -name TOP_LEVEL_ENTITY $opts(top)
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY bin
+
+set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
+set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009
+set_global_assignment -name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS ON
+set_global_assignment -name MESSAGE_DISABLE 16818
+set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON
+
+set_global_assignment -name SEED 1
+
+switch $opts(family) {
+    "Arria 10" {
+        set_global_assignment -name VERILOG_MACRO ALTERA_A10    
+    }
+    "Stratix 10" {
+        set_global_assignment -name VERILOG_MACRO ALTERA_S10    
+    }
+    default {
+        puts stderr "Invalid device family"
+        exit 1
+    }
+}
+
+set idx 0
+foreach arg $q_args_orig {
+    incr idx
+    if [string match "-src" $arg] {
+        set_global_assignment -name VERILOG_FILE [lindex $q_args_orig $idx]
+    }
+    if [string match "-inc" $arg] {
+        set_global_assignment -name SEARCH_PATH [lindex $q_args_orig $idx]
+    }
+    if [string match "-sdc" $arg] {
+        set_global_assignment -name SDC_FILE [lindex $q_args_orig $idx]
+    }
+    if [string match "-set" $arg] {
+        set_global_assignment -name VERILOG_MACRO [lindex $q_args_orig $idx]
+    }
+}
+
+proc make_all_pins_virtual {} {
+    execute_module -tool map
+    set excludes { clk }
+    set name_ids [get_names -filter * -node_type pin]
+    foreach_in_collection name_id $name_ids {        
+        set pin_name [get_name_info -info full_path $name_id]
+        if { [lsearch -exact -nocase $excludes $pin_name] >= 0 } {
+            post_message "Skipping VIRTUAL_PIN assignment to $pin_name"
+        } else {
+            post_message "Making VIRTUAL_PIN assignment to $pin_name"
+            set_instance_assignment -to $pin_name -name VIRTUAL_PIN ON
+        }
+    }
+    export_assignments
+}
+
+make_all_pins_virtual
+
+project_close
--- a/hw/syn/altera/quartus/smem/Makefile
+++ b/hw/syn/altera/quartus/smem/Makefile
@@ -0,0 +1,7 @@
+PROJECT = VX_shared_mem
+TOP_LEVEL_ENTITY = $(PROJECT)
+SRC_FILE = $(PROJECT).sv
+
+include ../../common.mk
+
+RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/mem
--- a/hw/syn/altera/quartus/test/Makefile
+++ b/hw/syn/altera/quartus/test/Makefile
@@ -0,0 +1,11 @@
+PROJECT = Vortex
+TOP_LEVEL_ENTITY = $(PROJECT)
+SRC_FILE = $(PROJECT).sv
+
+include ../../common.mk
+
+FPU_INCLUDE = -I$(RTL_DIR)/fpu
+ifneq (,$(findstring FPU_FPNEW,$(CONFIGS)))
+	FPU_INCLUDE += -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -J$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -J$(THIRD_PARTY_DIR)/fpnew/src
+endif
+RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/cache -I$(IP_CACHE_DIR) $(FPU_INCLUDE)
--- a/hw/syn/altera/quartus/timing-html.tcl
+++ b/hw/syn/altera/quartus/timing-html.tcl
@@ -0,0 +1,53 @@
+# Copyright © 2019-2023
+# 
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+# http://www.apache.org/licenses/LICENSE-2.0
+# 
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+package require cmdline
+
+set options { 
+    { "project.arg" "" "Project name" }
+    { "outdir.arg" "timing-html" "Output directory" } 
+}
+
+array set opts [::cmdline::getoptions quartus(args) $options]
+
+# Verify required parameters
+set requiredParameters {project}
+foreach p $requiredParameters {
+    if {$opts($p) == ""} {
+        puts stderr "Missing required parameter: -$p"
+        exit 1
+    }
+}
+
+project_open $opts(project)
+
+set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
+
+create_timing_netlist
+read_sdc
+update_timing_netlist
+
+foreach_in_collection op [get_available_operating_conditions] {
+  set_operating_conditions $op
+
+  report_timing -setup -npaths 150 -detail full_path -multi_corner -pairs_only -nworst 8 \
+    -file "$opts(outdir)/timing_paths_$op.html" \
+    -panel_name "Critical paths for $op"
+
+  create_slack_histogram -num_bins 50 -clock clk -multi_corner -file "$opts(outdir)/slack_histogram_$op.html"
+}
+
+
+
+
+
--- a/hw/syn/altera/quartus/top/Makefile
+++ b/hw/syn/altera/quartus/top/Makefile
@@ -0,0 +1,18 @@
+PROJECT = vortex_afu
+TOP_LEVEL_ENTITY = $(PROJECT)
+SRC_FILE = $(PROJECT).sv
+
+include ../../common.mk
+
+CONFIGS += -DNOPAE
+
+#CONFIGS += -DNUM_CORES=2
+#CONFIGS += -DNUM_WARPS=32
+#CONFIGS += -DNUM_THREADS=32
+#CONFIGS += -DL2_ENABLE
+
+FPU_INCLUDE = -I$(RTL_DIR)/fpu
+ifneq (,$(findstring FPU_FPNEW,$(CONFIGS)))
+	FPU_INCLUDE += -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -J$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -J$(THIRD_PARTY_DIR)/fpnew/src
+endif
+RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/mem -I$(RTL_DIR)/cache -I$(AFU_DIR) -I$(AFU_DIR)/ccip -I$(IP_CACHE_DIR) $(FPU_INCLUDE)
--- a/hw/syn/altera/quartus/unittest/Makefile
+++ b/hw/syn/altera/quartus/unittest/Makefile
@@ -0,0 +1,11 @@
+PROJECT = Unittest
+TOP_LEVEL_ENTITY = $(PROJECT)
+SRC_FILE = $(PROJECT).sv
+
+include ../../common.mk
+
+FPU_INCLUDE = -I$(RTL_DIR)/fpu
+ifneq (,$(findstring FPU_FPNEW,$(CONFIGS)))
+	FPU_INCLUDE += -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -J$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -J$(THIRD_PARTY_DIR)/fpnew/src
+endif
+RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/mem -I$(RTL_DIR)/cache -I$(IP_CACHE_DIR) $(FPU_INCLUDE)
--- a/hw/syn/altera/quartus/vortex/Makefile
+++ b/hw/syn/altera/quartus/vortex/Makefile
@@ -0,0 +1,16 @@
+PROJECT = Vortex
+TOP_LEVEL_ENTITY = $(PROJECT)
+SRC_FILE = $(PROJECT).sv
+
+include ../../common.mk
+
+#CONFIGS += -DNUM_CORES=2
+#CONFIGS += -DNUM_WARPS=32
+#CONFIGS += -DNUM_THREADS=32
+#CONFIGS += -DL2_ENABLE
+
+FPU_INCLUDE = -I$(RTL_DIR)/fpu
+ifneq (,$(findstring FPU_FPNEW,$(CONFIGS)))
+	FPU_INCLUDE += -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -J$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -J$(THIRD_PARTY_DIR)/fpnew/src
+endif
+RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/mem -I$(RTL_DIR)/cache -I$(IP_CACHE_DIR) $(FPU_INCLUDE)
--- a/hw/syn/altera/report_area.sh
+++ b/hw/syn/altera/report_area.sh
@@ -0,0 +1,17 @@
+#!/bin/bash
+
+# Dump Area Report
+# first argument is the project name
+
+SCRIPT_DIR="$(dirname "${BASH_SOURCE[0]}")"
+SCRIPT_DIR="$(realpath "${SCRIPT_DIR}")"
+
+PROJECT_DIR=$1
+PROJECT=$2
+MODE=${3-fit}
+
+echo "Running quartus_sh -t $SCRIPT_DIR/report_area.tcl $PROJECT $MODE in $PROJECT_DIR ..."
+
+pushd $PROJECT_DIR
+quartus_sh -t $SCRIPT_DIR/report_area.tcl $PROJECT $MODE
+popd
--- a/hw/syn/altera/report_area.tcl
+++ b/hw/syn/altera/report_area.tcl
@@ -0,0 +1,105 @@
+# Copyright © 2019-2023
+# 
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+# http://www.apache.org/licenses/LICENSE-2.0
+# 
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+load_package report
+
+set ProjectName [lindex $argv 0]
+set SynMode     [lindex $argv 1]
+
+proc panel_to_csv { panel_name csv_file } {
+    set fh [open $csv_file w]
+    # Its possible for some panels to not exist based on design (ex. if no RAMs )
+    set num_rows [get_number_of_rows -name $panel_name]
+    catch {	    
+	    for { set i 0 } { $i < $num_rows } { incr i } {
+	        set row_data_raw [get_report_panel_row -name $panel_name -row $i]
+	        set row_data [regsub -all , $row_data_raw ""]
+	        puts $fh [join $row_data ","]
+	    }
+	}
+    close $fh
+}
+
+# Dump names of all known panels
+proc do_dump_panelnames { } {
+	set fh [open "panels.txt" w]
+	set panel_names [get_report_panel_names]
+	foreach panel_name $panel_names {
+		puts $fh "$panel_name"
+	}
+	close $fh
+}
+
+proc do_map_analysis { ProjectName } {
+	# Save synthesis results
+	set RSyn1 "Synthesis||Synthesis Source Files Read"
+	set RSyn2 "Synthesis||Partition \"root_partition\"||Synthesis Resource Usage Summary for Partition \"root_partition\""
+	set RSyn3 "Synthesis||Partition \"root_partition\"||Partition \"root_partition\" Resource Utilization by Entity"
+	set RSyn4 "Synthesis||Partition \"root_partition\"||Synthesis RAM Summary for Partition \"root_partition\""
+	set RSyn5 "Synthesis||Partition \"root_partition\"||Partition \"root_partition\" Optimization Results||Register Statistics||Registers Protected by Synthesis"
+	set RSyn6 "Synthesis||Partition \"root_partition\"||Post-Synthesis Netlist Statistics for Partition \"root_partition\""
+	panel_to_csv $RSyn1 "$ProjectName.syn.area.source_files.csv"
+	panel_to_csv $RSyn2 "$ProjectName.syn.area.resource_summmary.csv"
+	panel_to_csv $RSyn3 "$ProjectName.syn.area.resource_breakdown.csv"
+	panel_to_csv $RSyn4 "$ProjectName.syn.area.ram_summary.csv"
+	panel_to_csv $RSyn5 "$ProjectName.syn.area.regs_removed.csv"
+	panel_to_csv $RSyn6 "$ProjectName.syn.area.stats.csv"
+}
+
+proc do_fit_analysis { ProjectName } {
+	# Save par results
+	set RPar1 "Fitter||Place Stage||Fitter Resource Usage Summary"
+	set RPar2 "Fitter||Place Stage||Fitter Resource Utilization by Entity"
+	set RPar3 "Fitter||Place Stage||Fitter Partition Statistics"
+	set RPar4 "Fitter||Place Stage||Fitter RAM Summary"
+	set RPar5 "Fitter||Plan Stage||Global & Other Fast Signals Summary"
+	set RPar6 "Fitter||Place Stage||Non-Global High Fan-Out Signals"
+	set RPar7 "Fitter||Route Stage||Routing Usage Summary"
+	panel_to_csv $RPar1 "$ProjectName.fit.area.resource_summary.csv"
+	panel_to_csv $RPar2 "$ProjectName.fit.area.resource_breakdown.csv"
+	#panel_to_csv $RPar3 "$ProjectName.fit.area.stats.csv"
+	panel_to_csv $RPar4 "$ProjectName.fit.area.ram_summary.csv"
+	panel_to_csv $RPar5 "$ProjectName.fit.area.routing_global.csv"
+	panel_to_csv $RPar6 "$ProjectName.fit.area.routing_high_fanout.csv"
+	panel_to_csv $RPar7 "$ProjectName.fit.area.routing_summary.csv"
+}
+
+proc do_fit_analysis_timingsummary { ProjectName } {
+	# Save timing results
+	set RT1 "TimeQuest Timing Analyzer||Slow 900mV 100C Model||Slow 900mV 100C Model Fmax Summary"
+	set RT2 "TimeQuest Timing Analyzer||Slow 900mV 100C Model||Slow 900mV 100C Model Setup Summary"
+	set RT3 "TimeQuest Timing Analyzer||Slow 900mV 100C Model||Slow 900mV 100C Model Hold Summary"
+	set RT4 "TimeQuest Timing Analyzer||Multicorner Timing Analysis Summary"
+	panel_to_csv $RT1 "$ProjectName.fit.timing.summary.fmax.csv"
+	panel_to_csv $RT2 "$ProjectName.fit.timing.summary.setup.csv"
+	panel_to_csv $RT3 "$ProjectName.fit.timing.summary.hold.csv"
+	panel_to_csv $RT4 "$ProjectName.fit.timing.summary.multicorner.csv"
+}
+
+project_open $ProjectName
+load_report
+
+# print available panels
+#do_dump_panelnames
+
+# => allows comparison of raw logic vs impact of routing delays
+if { $SynMode == "map" } {
+	do_map_analysis $ProjectName
+# normal post-par analysis (includes routing congestion/physical placement constraints)
+} else {	
+	do_fit_analysis $ProjectName
+	do_fit_analysis_timingsummary $ProjectName
+}
+
+unload_report
+project_close
				`@@ -0,0 +1 @@`
				`create_clock -name {clk} -period "200 MHz" -waveform { 0.000 1.0 } [get_ports {clk}]`