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OPAE rtl fixes

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This commit is contained in:
Blaise Tine
2020-05-08 08:28:28 -07:00
parent 13dfd5c8c7
commit c2e9240b7d
12 changed files with 208 additions and 243 deletions
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12
hw/rtl/VX_back_end.v
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@@ -8,12 +8,8 @@ module VX_back_end #(
input wire schedule_delay,
VX_cache_core_rsp_if dcache_rsp_if,
VX_cache_core_req_if dcache_req_if,
output wire mem_delay,
output wire exec_delay,
output wire gpr_stage_delay,
VX_cache_core_rsp_if dcache_rsp_if,
VX_jal_rsp_if jal_rsp_if,
VX_branch_rsp_if branch_rsp_if,
@@ -22,6 +18,10 @@ module VX_back_end #(
VX_warp_ctl_if warp_ctl_if,
output wire mem_delay,
output wire exec_delay,
output wire gpr_stage_delay,
output wire ebreak
);
@@ -78,8 +78,8 @@ module VX_back_end #(
.reset (reset),
.lsu_req_if (lsu_req_if),
.mem_wb_if (mem_wb_if),
.dcache_rsp_if (dcache_rsp_if),
.dcache_req_if (dcache_req_if),
.dcache_rsp_if (dcache_rsp_if),
.delay (mem_delay),
.no_slot_mem (no_slot_mem)
);

5
hw/rtl/VX_dmem_ctrl.v
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@@ -35,8 +35,11 @@ module VX_dmem_ctrl (
.CORE_TAG_ID_BITS(`CORE_TAG_ID_BITS)
) dcache_core_rsp_qual_if(), smem_core_rsp_if();
// use "case equality" to handle uninitialized address value
wire smem_select = ((dcache_core_req_if.core_req_addr[0][31:24] == `SHARED_MEM_TOP_ADDR) === 1'b1);
VX_dcache_io_arb dcache_io_arb (
.io_select (dcache_core_req_if.core_req_addr[0][31:24] == `SHARED_MEM_TOP_ADDR),
.io_select (smem_select),
.core_req_if (dcache_core_req_if),
.dcache_core_req_if (dcache_core_req_qual_if),
.io_core_req_if (smem_core_req_if),

25
hw/rtl/VX_icache_stage.v
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@@ -9,19 +9,24 @@ module VX_icache_stage (
output wire[`NUM_THREADS-1:0] icache_stage_valids,
VX_inst_meta_if fe_inst_meta_fi,
VX_inst_meta_if fe_inst_meta_id,
VX_cache_core_rsp_if icache_rsp_if,
VX_cache_core_req_if icache_req_if
VX_cache_core_req_if icache_req_if,
VX_cache_core_rsp_if icache_rsp_if
);
reg[`NUM_THREADS-1:0] pending_threads[`NUM_WARPS-1:0];
reg [`NUM_THREADS-1:0] valid_threads [`NUM_WARPS-1:0];
wire valid_inst = (| fe_inst_meta_fi.valid);
`DEBUG_BEGIN
wire [`CORE_REQ_TAG_WIDTH-1:0] core_req_tag = icache_req_if.core_req_tag;
wire [`CORE_REQ_TAG_WIDTH-1:0] core_rsp_tag = icache_rsp_if.core_rsp_tag;
`DEBUG_END
// Icache Request
assign icache_req_if.core_req_valid = valid_inst && !total_freeze;
assign icache_req_if.core_req_addr = fe_inst_meta_fi.inst_pc;
assign icache_req_if.core_req_data = 32'b0;
assign icache_req_if.core_req_data = 'z;
assign icache_req_if.core_req_read = `BYTE_EN_LW;
assign icache_req_if.core_req_write = `BYTE_EN_NO;
assign icache_req_if.core_req_tag = {fe_inst_meta_fi.inst_pc, 2'b1, 5'b0, fe_inst_meta_fi.warp_num};
@@ -33,8 +38,8 @@ module VX_icache_stage (
assign {fe_inst_meta_id.inst_pc, rsp_wb, rsp_rd, fe_inst_meta_id.warp_num} = icache_rsp_if.core_rsp_tag;
assign fe_inst_meta_id.instruction = icache_rsp_if.core_rsp_data[0][31:0];
assign fe_inst_meta_id.valid = icache_rsp_if.core_rsp_valid ? pending_threads[fe_inst_meta_id.warp_num] : 0;
assign fe_inst_meta_id.instruction = icache_rsp_if.core_rsp_data[0];
assign fe_inst_meta_id.valid = icache_rsp_if.core_rsp_valid ? valid_threads[fe_inst_meta_id.warp_num] : 0;
assign icache_stage_wid = fe_inst_meta_id.warp_num;
assign icache_stage_valids = fe_inst_meta_id.valid & {`NUM_THREADS{!icache_stage_delay}};
@@ -49,12 +54,10 @@ module VX_icache_stage (
always @(posedge clk) begin
if (reset) begin
for (i = 0; i < `NUM_WARPS; i = i + 1) begin
pending_threads[i] <= 0;
end
//--
end else begin
if (icache_req_if.core_req_valid && icache_req_if.core_req_ready) begin
pending_threads[fe_inst_meta_fi.warp_num] <= fe_inst_meta_fi.valid;
valid_threads[fe_inst_meta_fi.warp_num] <= fe_inst_meta_fi.valid;
end
end
end

2
hw/rtl/VX_lsu_unit.v
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@@ -11,8 +11,8 @@ module VX_lsu_unit (
VX_wb_if mem_wb_if,
// Dcache interface
VX_cache_core_rsp_if dcache_rsp_if,
VX_cache_core_req_if dcache_req_if,
VX_cache_core_rsp_if dcache_rsp_if,
output wire delay
);

5
hw/rtl/Vortex.v
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@@ -244,8 +244,11 @@ module Vortex #(
.icache_dram_rsp_if (icache_dram_rsp_if)
);
// use "case equality" to handle uninitialized address value
wire io_select = ((dcache_io_core_req_if.core_req_addr[0] >= `IO_BUS_BASE_ADDR) === 1'b1);
VX_dcache_io_arb dcache_io_arb (
.io_select (dcache_io_core_req_if.core_req_addr[0] >= `IO_BUS_BASE_ADDR),
.io_select (io_select),
.core_req_if (dcache_io_core_req_if),
.dcache_core_req_if (dcache_core_req_if),
.io_core_req_if (io_core_req_if),

14
hw/rtl/cache/VX_tag_data_access.v vendored
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@@ -90,13 +90,11 @@ module VX_tag_data_access #(
wire fill_sent;
wire invalidate_line;
wire tags_match;
wire real_writefill = writefill_st1e
&& ((valid_req_st1e
&& !use_read_valid_st1e)
|| (valid_req_st1e
&& use_read_valid_st1e
&& (writeaddr_st1e[`TAG_LINE_ADDR_RNG] != use_read_tag_st1e)));
&& ((valid_req_st1e && !use_read_valid_st1e)
|| (valid_req_st1e && use_read_valid_st1e && !tags_match));
VX_tag_data_structure #(
.CACHE_SIZE (CACHE_SIZE),
@@ -256,14 +254,14 @@ module VX_tag_data_access #(
assign data_write[i * `WORD_WIDTH +: `WORD_WIDTH] = force_write ? writedata_st1e[i * `WORD_WIDTH +: `WORD_WIDTH] : use_write_dat;
end
end
assign use_write_enable = (writefill_st1e && !real_writefill) ? 0 : we;
assign use_write_data = data_write;
wire[`TAG_SELECT_BITS-1:0] writeaddr_tag = writeaddr_st1e[`TAG_LINE_ADDR_RNG];
wire tags_match = writeaddr_tag == use_read_tag_st1e;
// use "case equality" to handle uninitialized tag when block entry is not valid
assign tags_match = ((writeaddr_st1e[`TAG_LINE_ADDR_RNG] == use_read_tag_st1e) === 1'b1);
wire snoop_hit = valid_req_st1e && is_snp_st1e && use_read_valid_st1e && tags_match && use_read_dirty_st1e;
wire req_invalid = valid_req_st1e && !is_snp_st1e && !use_read_valid_st1e && !writefill_st1e;