From c63217f67d6d4747524c7bcce5a598d5681dc3a7 Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Tue, 1 Sep 2020 05:20:13 -0700 Subject: [PATCH] fixed SCOPE interface --- driver/opae/scope.cpp | 53 ++++++------- driver/rtlsim/Makefile | 4 +- hw/opae/vortex_afu.sv | 6 +- hw/rtl/VX_cluster.v | 4 +- hw/rtl/VX_core.v | 4 +- hw/rtl/VX_execute.v | 24 ++---- hw/rtl/VX_fetch.v | 2 + hw/rtl/VX_lsu_unit.v | 4 +- hw/rtl/VX_pipeline.v | 10 +-- hw/rtl/VX_scope.vh | 174 +++++++++++++++-------------------------- hw/rtl/Vortex.v | 6 +- 11 files changed, 117 insertions(+), 174 deletions(-) diff --git a/driver/opae/scope.cpp b/driver/opae/scope.cpp index 0bbe4b10..9181b748 100644 --- a/driver/opae/scope.cpp +++ b/driver/opae/scope.cpp @@ -32,6 +32,12 @@ constexpr int ilog2(int n) { static constexpr int NW_BITS = ilog2(NUM_WARPS); +#ifdef EXT_F_ENABLE +static constexpr int NR_BITS = ilog2(64); +#else +static constexpr int NR_BITS = ilog2(32); +#endif + static const scope_signal_t scope_signals[] = { { 32, "dram_req_addr" }, @@ -47,39 +53,32 @@ static const scope_signal_t scope_signals[] = { { 16, "snp_req_tag" }, { 16, "snp_rsp_tag" }, - { NW_BITS, "icache_req_warp_num" }, + { NW_BITS, "icache_req_wid" }, { 32, "icache_req_addr" }, { NW_BITS, "icache_req_tag" }, { 32, "icache_rsp_data" }, { NW_BITS, "icache_rsp_tag" }, - { NW_BITS, "dcache_req_warp_num" }, - { 32, "dcache_req_curr_PC" }, - { 64, "dcache_req_addr" }, + { NW_BITS, "dcache_req_wid" }, + { 32, "dcache_req_PC" }, + { NUM_THREADS * 32, "dcache_req_addr" }, { 1, "dcache_req_rw" }, - { 8, "dcache_req_byteen" }, - { 64, "dcache_req_data" }, + { NUM_THREADS * 4, "dcache_req_byteen" }, + { NUM_THREADS * 32, "dcache_req_data" }, { NW_BITS, "dcache_req_tag" }, - { 64, "dcache_rsp_data" }, + { NUM_THREADS * 32, "dcache_rsp_data" }, { NW_BITS, "dcache_rsp_tag" }, - { NW_BITS, "decode_warp_num" }, - { 32, "decode_curr_PC" }, - { 1, "decode_is_jal" }, - { 5, "decode_rs1" }, - { 5, "decode_rs2" }, + { NW_BITS, "alu_req_wid" }, + { 32, "alu_req_PC" }, + { NR_BITS, "alu_req_rd" }, + { NUM_THREADS * 32, "alu_req_a" }, + { NUM_THREADS * 32, "alu_req_b" }, - { NW_BITS, "execute_warp_num" }, - { 32, "execute_curr_PC" }, - { 5, "execute_rd" }, - { 64, "execute_a" }, - { 64, "execute_b" }, - - { NW_BITS, "writeback_warp_num" }, - { 32, "writeback_curr_PC" }, - { 2, "writeback_wb" }, - { 5, "writeback_rd" }, - { 64, "writeback_data" }, + { NW_BITS, "writeback_wid" }, + { 32, "writeback_PC" }, + { NR_BITS, "writeback_rd" }, + { NUM_THREADS * 32, "writeback_data" }, { 32, "bank_addr_st0" }, { 32, "bank_addr_st1" }, @@ -112,13 +111,9 @@ static const scope_signal_t scope_signals[] = { { 1, "dcache_rsp_ready" }, { NUM_THREADS, "decode_valid" }, - { NUM_THREADS, "execute_valid" }, - { NUM_THREADS, "writeback_valid" }, + { NUM_THREADS, "alu_req_valid" }, + { NUM_THREADS, "writeback_valid" }, - { 1, "schedule_delay" }, - { 1, "mem_delay" }, - { 1, "exec_delay" }, - { 1, "gpr_delay" }, { 1, "busy" }, { 1, "bank_valid_st0" }, diff --git a/driver/rtlsim/Makefile b/driver/rtlsim/Makefile index 73e64d64..ea4f3c22 100644 --- a/driver/rtlsim/Makefile +++ b/driver/rtlsim/Makefile @@ -62,8 +62,8 @@ ifdef AFU TOP = vortex_afu_sim VL_FLAGS += -DNOPAE CFLAGS += -DNOPAE - #VL_FLAGS += -DSCOPE - #CFLAGS += -DSCOPE + VL_FLAGS += -DSCOPE + CFLAGS += -DSCOPE RTL_INCLUDE += -I../../hw/opae -I../../hw/opae/ccip endif diff --git a/hw/opae/vortex_afu.sv b/hw/opae/vortex_afu.sv index 1730eedb..a21d6a26 100644 --- a/hw/opae/vortex_afu.sv +++ b/hw/opae/vortex_afu.sv @@ -916,7 +916,7 @@ Vortex #() vortex ( `SCOPE_SIGNALS_CORE_BIND `SCOPE_SIGNALS_CACHE_BIND `SCOPE_SIGNALS_PIPELINE_BIND - `SCOPE_SIGNALS_BE_BIND + `SCOPE_SIGNALS_EX_BIND .clk (clk), .reset (SoftReset | vx_reset), @@ -1017,8 +1017,8 @@ localparam SCOPE_SR_DEPTH = 2; wire scope_changed = (scope_icache_req_valid && scope_icache_req_ready) || (scope_icache_rsp_valid && scope_icache_rsp_ready) - || (scope_dcache_req_valid && scope_dcache_req_ready) - || (scope_dcache_rsp_valid && scope_dcache_rsp_ready) + || ((| scope_dcache_req_valid) && scope_dcache_req_ready) + || ((| scope_dcache_rsp_valid) && scope_dcache_rsp_ready) || (scope_dram_req_valid && scope_dram_req_ready) || (scope_dram_rsp_valid && scope_dram_rsp_ready) || (scope_snp_req_valid && scope_snp_req_ready) diff --git a/hw/rtl/VX_cluster.v b/hw/rtl/VX_cluster.v index f1cba93d..a39fda95 100644 --- a/hw/rtl/VX_cluster.v +++ b/hw/rtl/VX_cluster.v @@ -8,7 +8,7 @@ module VX_cluster #( `SCOPE_SIGNALS_CORE_IO `SCOPE_SIGNALS_CACHE_IO `SCOPE_SIGNALS_PIPELINE_IO - `SCOPE_SIGNALS_BE_IO + `SCOPE_SIGNALS_EX_IO // Clock input wire clk, @@ -144,7 +144,7 @@ module VX_cluster #( `SCOPE_SIGNALS_CORE_BIND `SCOPE_SIGNALS_CACHE_BIND `SCOPE_SIGNALS_PIPELINE_BIND - `SCOPE_SIGNALS_BE_BIND + `SCOPE_SIGNALS_EX_BIND .clk (clk), .reset (reset), diff --git a/hw/rtl/VX_core.v b/hw/rtl/VX_core.v index 8e4fff92..c5d20b83 100644 --- a/hw/rtl/VX_core.v +++ b/hw/rtl/VX_core.v @@ -8,7 +8,7 @@ module VX_core #( `SCOPE_SIGNALS_CORE_IO `SCOPE_SIGNALS_CACHE_IO `SCOPE_SIGNALS_PIPELINE_IO - `SCOPE_SIGNALS_BE_IO + `SCOPE_SIGNALS_EX_IO // Clock input wire clk, @@ -183,7 +183,7 @@ module VX_core #( `SCOPE_SIGNALS_ISTAGE_BIND `SCOPE_SIGNALS_LSU_BIND `SCOPE_SIGNALS_PIPELINE_BIND - `SCOPE_SIGNALS_BE_BIND + `SCOPE_SIGNALS_EX_BIND .clk(clk), .reset(reset), diff --git a/hw/rtl/VX_execute.v b/hw/rtl/VX_execute.v index 9c55de7c..5f8f312f 100644 --- a/hw/rtl/VX_execute.v +++ b/hw/rtl/VX_execute.v @@ -4,7 +4,7 @@ module VX_execute #( parameter CORE_ID = 0 ) ( `SCOPE_SIGNALS_LSU_IO - `SCOPE_SIGNALS_BE_IO + `SCOPE_SIGNALS_EX_IO input wire clk, input wire reset, @@ -126,24 +126,16 @@ module VX_execute #( && (`BR_OP(alu_req_if.op_type) == `BR_EBREAK || `BR_OP(alu_req_if.op_type) == `BR_ECALL); - `SCOPE_ASSIGN (scope_decode_valid, decode_if.valid); - `SCOPE_ASSIGN (scope_decode_wid, decode_if.wid); - `SCOPE_ASSIGN (scope_decode_curr_PC, decode_if.curr_PC); - `SCOPE_ASSIGN (scope_decode_is_jal, decode_if.is_jal); - `SCOPE_ASSIGN (scope_decode_rs1, decode_if.rs1); - `SCOPE_ASSIGN (scope_decode_rs2, decode_if.rs2); - - `SCOPE_ASSIGN (scope_execute_valid, alu_req_if.valid); - `SCOPE_ASSIGN (scope_execute_wid, alu_req_if.wid); - `SCOPE_ASSIGN (scope_execute_curr_PC, alu_req_if.curr_PC); - `SCOPE_ASSIGN (scope_execute_rd, alu_req_if.rd); - `SCOPE_ASSIGN (scope_execute_a, alu_req_if.rs1_data); - `SCOPE_ASSIGN (scope_execute_b, alu_req_if.rs2_data); + `SCOPE_ASSIGN (scope_alu_req_valid, alu_req_if.valid); + `SCOPE_ASSIGN (scope_alu_req_wid, alu_req_if.wid); + `SCOPE_ASSIGN (scope_alu_req_PC, alu_req_if.curr_PC); + `SCOPE_ASSIGN (scope_alu_req_rd, alu_req_if.rd); + `SCOPE_ASSIGN (scope_alu_req_a, alu_req_if.rs1_data); + `SCOPE_ASSIGN (scope_alu_req_b, alu_req_if.rs2_data); `SCOPE_ASSIGN (scope_writeback_valid, writeback_if.valid); `SCOPE_ASSIGN (scope_writeback_wid, writeback_if.wid); - `SCOPE_ASSIGN (scope_writeback_curr_PC, writeback_if.curr_PC); - `SCOPE_ASSIGN (scope_writeback_wb, writeback_if.wb); + `SCOPE_ASSIGN (scope_writeback_PC, writeback_if.curr_PC); `SCOPE_ASSIGN (scope_writeback_rd, writeback_if.rd); `SCOPE_ASSIGN (scope_writeback_data, writeback_if.data); diff --git a/hw/rtl/VX_fetch.v b/hw/rtl/VX_fetch.v index 88ac1e54..cf0c2e45 100644 --- a/hw/rtl/VX_fetch.v +++ b/hw/rtl/VX_fetch.v @@ -3,6 +3,8 @@ module VX_fetch #( parameter CORE_ID = 0 ) ( + `SCOPE_SIGNALS_ISTAGE_IO + input wire clk, input wire reset, diff --git a/hw/rtl/VX_lsu_unit.v b/hw/rtl/VX_lsu_unit.v index 0f68f381..2401d559 100644 --- a/hw/rtl/VX_lsu_unit.v +++ b/hw/rtl/VX_lsu_unit.v @@ -194,13 +194,13 @@ module VX_lsu_unit #( // scope registration `SCOPE_ASSIGN (scope_dcache_req_valid, dcache_req_if.valid); `SCOPE_ASSIGN (scope_dcache_req_addr, req_address); - `SCOPE_ASSIGN (scope_dcache_req_rw, dcache_req_if.rw ); + `SCOPE_ASSIGN (scope_dcache_req_rw, req_rw); `SCOPE_ASSIGN (scope_dcache_req_byteen,dcache_req_if.byteen); `SCOPE_ASSIGN (scope_dcache_req_data, dcache_req_if.data); `SCOPE_ASSIGN (scope_dcache_req_tag, dcache_req_if.tag); `SCOPE_ASSIGN (scope_dcache_req_ready, dcache_req_if.ready); `SCOPE_ASSIGN (scope_dcache_req_wid, req_wid); - `SCOPE_ASSIGN (scope_dcache_req_curr_PC, req_pc); + `SCOPE_ASSIGN (scope_dcache_req_PC, req_curr_PC); `SCOPE_ASSIGN (scope_dcache_rsp_valid, dcache_rsp_if.valid); `SCOPE_ASSIGN (scope_dcache_rsp_data, dcache_rsp_if.data); diff --git a/hw/rtl/VX_pipeline.v b/hw/rtl/VX_pipeline.v index bd8df46d..00b2c5c3 100644 --- a/hw/rtl/VX_pipeline.v +++ b/hw/rtl/VX_pipeline.v @@ -6,7 +6,7 @@ module VX_pipeline #( `SCOPE_SIGNALS_ISTAGE_IO `SCOPE_SIGNALS_LSU_IO `SCOPE_SIGNALS_PIPELINE_IO - `SCOPE_SIGNALS_BE_IO + `SCOPE_SIGNALS_EX_IO // Clock input wire clk, @@ -126,6 +126,7 @@ module VX_pipeline #( VX_fetch #( .CORE_ID(CORE_ID) ) fetch ( + `SCOPE_SIGNALS_ISTAGE_BIND .clk (clk), .reset (reset), .icache_req_if (core_icache_req_if), @@ -171,6 +172,7 @@ module VX_pipeline #( .CORE_ID(CORE_ID) ) execute ( `SCOPE_SIGNALS_LSU_BIND + `SCOPE_SIGNALS_EX_BIND .clk (clk), .reset (reset), @@ -245,10 +247,6 @@ module VX_pipeline #( assign core_icache_rsp_if.tag = icache_rsp_tag; assign icache_rsp_ready = core_icache_rsp_if.ready; - `SCOPE_ASSIGN (scope_busy, busy); - `SCOPE_ASSIGN (scope_schedule_delay, schedule_delay); - `SCOPE_ASSIGN (scope_mem_delay, mem_delay); - `SCOPE_ASSIGN (scope_exec_delay, exec_delay); - `SCOPE_ASSIGN (scope_gpr_stage_delay, gpr_delay); + `SCOPE_ASSIGN (scope_busy, busy); endmodule diff --git a/hw/rtl/VX_scope.vh b/hw/rtl/VX_scope.vh index 29f522e3..aef5eb95 100644 --- a/hw/rtl/VX_scope.vh +++ b/hw/rtl/VX_scope.vh @@ -21,7 +21,7 @@ scope_icache_rsp_data, \ scope_icache_rsp_tag, \ scope_dcache_req_wid, \ - scope_dcache_req_curr_PC, \ + scope_dcache_req_PC, \ scope_dcache_req_addr, \ scope_dcache_req_rw, \ scope_dcache_req_byteen, \ @@ -29,19 +29,13 @@ scope_dcache_req_tag, \ scope_dcache_rsp_data, \ scope_dcache_rsp_tag, \ - scope_decode_wid, \ - scope_decode_curr_PC, \ - scope_decode_is_jal, \ - scope_decode_rs1, \ - scope_decode_rs2, \ - scope_execute_wid, \ - scope_execute_curr_PC, \ - scope_execute_rd, \ - scope_execute_a, \ - scope_execute_b, \ + scope_alu_req_wid, \ + scope_alu_req_PC, \ + scope_alu_req_rd, \ + scope_alu_req_a, \ + scope_alu_req_b, \ scope_writeback_wid, \ - scope_writeback_curr_PC, \ - scope_writeback_wb, \ + scope_writeback_PC, \ scope_writeback_rd, \ scope_writeback_data, \ scope_bank_addr_st0, \ @@ -70,13 +64,8 @@ scope_dcache_req_ready, \ scope_dcache_rsp_valid, \ scope_dcache_rsp_ready, \ - scope_decode_valid, \ - scope_execute_valid, \ + scope_alu_req_valid, \ scope_writeback_valid, \ - scope_schedule_delay, \ - scope_mem_delay, \ - scope_exec_delay, \ - scope_gpr_stage_delay, \ scope_busy, \ scope_bank_valid_st0, \ scope_bank_valid_st1, \ @@ -113,41 +102,30 @@ wire scope_icache_rsp_ready; \ wire [`NUM_THREADS-1:0] scope_dcache_req_valid; \ wire [`NW_BITS-1:0] scope_dcache_req_wid; \ - wire [31:0] scope_dcache_req_curr_PC; \ - wire [63:0] scope_dcache_req_addr; \ + wire [31:0] scope_dcache_req_PC; \ + wire [`NUM_THREADS-1:0][31:0] scope_dcache_req_addr; \ wire scope_dcache_req_rw; \ - wire [7:0] scope_dcache_req_byteen; \ - wire [63:0] scope_dcache_req_data; \ + wire [`NUM_THREADS-1:0][3:0] scope_dcache_req_byteen; \ + wire [`NUM_THREADS-1:0][31:0] scope_dcache_req_data; \ wire [`DCORE_TAG_WIDTH-1:0] scope_dcache_req_tag; \ wire scope_dcache_req_ready; \ wire [`NUM_THREADS-1:0] scope_dcache_rsp_valid; \ - wire [63:0] scope_dcache_rsp_data; \ + wire [`NUM_THREADS-1:0][31:0] scope_dcache_rsp_data; \ wire [`DCORE_TAG_WIDTH-1:0] scope_dcache_rsp_tag; \ wire scope_dcache_rsp_ready; \ wire scope_busy; \ wire scope_snp_rsp_ready; \ - wire scope_schedule_delay; \ - wire scope_mem_delay; \ - wire scope_exec_delay; \ - wire scope_gpr_stage_delay; \ - wire [`NUM_THREADS-1:0] scope_decode_valid; \ - wire [`NW_BITS-1:0] scope_decode_wid; \ - wire [31:0] scope_decode_curr_PC; \ - wire scope_decode_is_jal; \ - wire [`NR_BITS-1:0] scope_decode_rs1; \ - wire [`NR_BITS-1:0] scope_decode_rs2; \ - wire [`NUM_THREADS-1:0] scope_execute_valid; \ - wire [`NW_BITS-1:0] scope_execute_wid; \ - wire [31:0] scope_execute_curr_PC; \ - wire [`NR_BITS-1:0] scope_execute_rd; \ - wire [63:0] scope_execute_a; \ - wire [63:0] scope_execute_b; \ - wire [`NUM_THREADS-1:0] scope_writeback_valid; \ - wire [`NW_BITS-1:0] scope_writeback_wid; \ - wire [31:0] scope_writeback_curr_PC; \ - wire scope_writeback_wb; \ + wire scope_alu_req_valid; \ + wire [`NW_BITS-1:0] scope_alu_req_wid; \ + wire [31:0] scope_alu_req_PC; \ + wire [`NR_BITS-1:0] scope_alu_req_rd; \ + wire [`NUM_THREADS-1:0][31:0] scope_alu_req_a; \ + wire [`NUM_THREADS-1:0][31:0] scope_alu_req_b; \ + wire scope_writeback_valid; \ + wire [`NW_BITS-1:0] scope_writeback_wid; \ + wire [31:0] scope_writeback_PC; \ wire [`NR_BITS-1:0] scope_writeback_rd; \ - wire [63:0] scope_writeback_data; \ + wire [`NUM_THREADS-1:0][31:0] scope_writeback_data; \ wire scope_bank_valid_st0; \ wire scope_bank_valid_st1; \ wire scope_bank_valid_st2; \ @@ -174,15 +152,15 @@ `define SCOPE_SIGNALS_LSU_IO \ output wire [`NUM_THREADS-1:0] scope_dcache_req_valid, \ output wire [`NW_BITS-1:0] scope_dcache_req_wid, \ - output wire [31:0] scope_dcache_req_curr_PC, \ - output wire [63:0] scope_dcache_req_addr, \ + output wire [31:0] scope_dcache_req_PC, \ + output wire [`NUM_THREADS-1:0][31:0] scope_dcache_req_addr, \ output wire scope_dcache_req_rw, \ - output wire [7:0] scope_dcache_req_byteen, \ - output wire [63:0] scope_dcache_req_data, \ + output wire [`NUM_THREADS-1:0][3:0] scope_dcache_req_byteen, \ + output wire [`NUM_THREADS-1:0][31:0] scope_dcache_req_data, \ output wire [`DCORE_TAG_WIDTH-1:0] scope_dcache_req_tag, \ output wire scope_dcache_req_ready, \ output wire [`NUM_THREADS-1:0] scope_dcache_rsp_valid, \ - output wire [63:0] scope_dcache_rsp_data, \ + output wire [`NUM_THREADS-1:0][31:0] scope_dcache_rsp_data, \ output wire [`DCORE_TAG_WIDTH-1:0] scope_dcache_rsp_tag, \ output wire scope_dcache_rsp_ready, @@ -202,35 +180,24 @@ output wire scope_bank_stall_pipe, `define SCOPE_SIGNALS_PIPELINE_IO \ - output wire scope_busy, \ - output wire scope_schedule_delay, \ - output wire scope_mem_delay, \ - output wire scope_exec_delay, \ - output wire scope_gpr_stage_delay, + output wire scope_busy, - `define SCOPE_SIGNALS_BE_IO \ - output wire [`NUM_THREADS-1:0] scope_decode_valid, \ - output wire [`NW_BITS-1:0] scope_decode_wid, \ - output wire [31:0] scope_decode_curr_PC, \ - output wire scope_decode_is_jal, \ - output wire [`NR_BITS-1:0] scope_decode_rs1, \ - output wire [`NR_BITS-1:0] scope_decode_rs2, \ - output wire [`NUM_THREADS-1:0] scope_execute_valid, \ - output wire [`NW_BITS-1:0] scope_execute_wid, \ - output wire [31:0] scope_execute_curr_PC, \ - output wire [`NR_BITS-1:0] scope_execute_rd, \ - output wire [63:0] scope_execute_a, \ - output wire [63:0] scope_execute_b, \ - output wire [`NUM_THREADS-1:0] scope_writeback_valid, \ - output wire [`NW_BITS-1:0] scope_writeback_wid, \ - output wire [31:0] scope_writeback_curr_PC, \ - output wire scope_writeback_wb, \ - output wire [`NR_BITS-1:0] scope_writeback_rd, \ - output wire [63:0] scope_writeback_data, + `define SCOPE_SIGNALS_EX_IO \ + output wire scope_alu_req_valid, \ + output wire [`NW_BITS-1:0] scope_alu_req_wid, \ + output wire [31:0] scope_alu_req_PC, \ + output wire [`NR_BITS-1:0] scope_alu_req_rd, \ + output wire [`NUM_THREADS-1:0][31:0] scope_alu_req_a, \ + output wire [`NUM_THREADS-1:0][31:0] scope_alu_req_b, \ + output wire scope_writeback_valid, \ + output wire [`NW_BITS-1:0] scope_writeback_wid, \ + output wire [31:0] scope_writeback_PC, \ + output wire [`NR_BITS-1:0] scope_writeback_rd, \ + output wire [`NUM_THREADS-1:0][31:0] scope_writeback_data, `define SCOPE_SIGNALS_ISTAGE_BIND \ .scope_icache_req_valid (scope_icache_req_valid), \ - .scope_icache_req_wid (scope_icache_req_wid), \ + .scope_icache_req_wid (scope_icache_req_wid), \ .scope_icache_req_addr (scope_icache_req_addr), \ .scope_icache_req_tag (scope_icache_req_tag), \ .scope_icache_req_ready (scope_icache_req_ready), \ @@ -241,8 +208,8 @@ `define SCOPE_SIGNALS_LSU_BIND \ .scope_dcache_req_valid (scope_dcache_req_valid), \ - .scope_dcache_req_wid (scope_dcache_req_wid), \ - .scope_dcache_req_curr_PC (scope_dcache_req_curr_PC), \ + .scope_dcache_req_wid (scope_dcache_req_wid), \ + .scope_dcache_req_PC (scope_dcache_req_PC), \ .scope_dcache_req_addr (scope_dcache_req_addr), \ .scope_dcache_req_rw (scope_dcache_req_rw), \ .scope_dcache_req_byteen(scope_dcache_req_byteen), \ @@ -311,42 +278,31 @@ assign scope_bank_stall_pipe = scope_per_bank_stall_pipe[0]; `define SCOPE_SIGNALS_CACHE_BANK_BIND \ - .scope_bank_valid_st0 (scope_per_bank_valid_st0[i]), \ - .scope_bank_valid_st1 (scope_per_bank_valid_st1[i]), \ - .scope_bank_valid_st2 (scope_per_bank_valid_st2[i]), \ - .scope_bank_addr_st0 (scope_per_bank_addr_st0[i]), \ - .scope_bank_addr_st1 (scope_per_bank_addr_st1[i]), \ - .scope_bank_addr_st2 (scope_per_bank_addr_st2[i]), \ + .scope_bank_valid_st0 (scope_per_bank_valid_st0[i]), \ + .scope_bank_valid_st1 (scope_per_bank_valid_st1[i]), \ + .scope_bank_valid_st2 (scope_per_bank_valid_st2[i]), \ + .scope_bank_addr_st0 (scope_per_bank_addr_st0[i]), \ + .scope_bank_addr_st1 (scope_per_bank_addr_st1[i]), \ + .scope_bank_addr_st2 (scope_per_bank_addr_st2[i]), \ .scope_bank_is_mrvq_st1 (scope_per_bank_is_mrvq_st1[i]), \ - .scope_bank_miss_st1 (scope_per_bank_miss_st1[i]), \ - .scope_bank_dirty_st1 (scope_per_bank_dirty_st1[i]), \ + .scope_bank_miss_st1 (scope_per_bank_miss_st1[i]), \ + .scope_bank_dirty_st1 (scope_per_bank_dirty_st1[i]), \ .scope_bank_force_miss_st1 (scope_per_bank_force_miss_st1[i]), \ - .scope_bank_stall_pipe (scope_per_bank_stall_pipe[i]), + .scope_bank_stall_pipe (scope_per_bank_stall_pipe[i]), `define SCOPE_SIGNALS_PIPELINE_BIND \ - .scope_busy (scope_busy), \ - .scope_schedule_delay (scope_schedule_delay), \ - .scope_mem_delay (scope_mem_delay), \ - .scope_exec_delay (scope_exec_delay), \ - .scope_gpr_stage_delay (scope_gpr_stage_delay), + .scope_busy (scope_busy), - `define SCOPE_SIGNALS_BE_BIND \ - .scope_decode_valid (scope_decode_valid), \ - .scope_decode_wid (scope_decode_wid), \ - .scope_decode_curr_PC (scope_decode_curr_PC), \ - .scope_decode_is_jal (scope_decode_is_jal), \ - .scope_decode_rs1 (scope_decode_rs1), \ - .scope_decode_rs2 (scope_decode_rs2), \ - .scope_execute_valid (scope_execute_valid), \ - .scope_execute_wid (scope_execute_wid), \ - .scope_execute_curr_PC (scope_execute_curr_PC), \ - .scope_execute_rd (scope_execute_rd), \ - .scope_execute_a (scope_execute_a), \ - .scope_execute_b (scope_execute_b), \ + `define SCOPE_SIGNALS_EX_BIND \ + .scope_alu_req_valid (scope_alu_req_valid), \ + .scope_alu_req_wid (scope_alu_req_wid), \ + .scope_alu_req_PC (scope_alu_req_PC), \ + .scope_alu_req_rd (scope_alu_req_rd), \ + .scope_alu_req_a (scope_alu_req_a), \ + .scope_alu_req_b (scope_alu_req_b), \ .scope_writeback_valid (scope_writeback_valid), \ - .scope_writeback_wid (scope_writeback_wid), \ - .scope_writeback_curr_PC(scope_writeback_curr_PC), \ - .scope_writeback_wb (scope_writeback_wb), \ + .scope_writeback_wid (scope_writeback_wid), \ + .scope_writeback_PC (scope_writeback_PC), \ .scope_writeback_rd (scope_writeback_rd), \ .scope_writeback_data (scope_writeback_data), @@ -357,14 +313,14 @@ `define SCOPE_SIGNALS_CORE_IO `define SCOPE_SIGNALS_CACHE_IO `define SCOPE_SIGNALS_PIPELINE_IO - `define SCOPE_SIGNALS_BE_IO + `define SCOPE_SIGNALS_EX_IO `define SCOPE_SIGNALS_ISTAGE_BIND `define SCOPE_SIGNALS_LSU_BIND `define SCOPE_SIGNALS_CORE_BIND `define SCOPE_SIGNALS_CACHE_BIND `define SCOPE_SIGNALS_PIPELINE_BIND - `define SCOPE_SIGNALS_BE_BIND + `define SCOPE_SIGNALS_EX_BIND `define SCOPE_SIGNALS_CACHE_UNBIND `define SCOPE_SIGNALS_CACHE_BANK_SELECT diff --git a/hw/rtl/Vortex.v b/hw/rtl/Vortex.v index 8e11428d..3fd90221 100644 --- a/hw/rtl/Vortex.v +++ b/hw/rtl/Vortex.v @@ -6,7 +6,7 @@ module Vortex ( `SCOPE_SIGNALS_CORE_IO `SCOPE_SIGNALS_CACHE_IO `SCOPE_SIGNALS_PIPELINE_IO - `SCOPE_SIGNALS_BE_IO + `SCOPE_SIGNALS_EX_IO // Clock input wire clk, @@ -81,7 +81,7 @@ module Vortex ( `SCOPE_SIGNALS_CORE_BIND `SCOPE_SIGNALS_CACHE_BIND `SCOPE_SIGNALS_PIPELINE_BIND - `SCOPE_SIGNALS_BE_BIND + `SCOPE_SIGNALS_EX_BIND .clk (clk), .reset (reset), @@ -200,7 +200,7 @@ module Vortex ( `SCOPE_SIGNALS_CORE_BIND `SCOPE_SIGNALS_CACHE_BIND `SCOPE_SIGNALS_PIPELINE_BIND - `SCOPE_SIGNALS_BE_BIND + `SCOPE_SIGNALS_EX_BIND .clk (clk), .reset (reset),