cache bindings and memory perf refactory
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@@ -228,9 +228,6 @@
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`define INST_SFU_CSRRS 4'h7
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`define INST_SFU_CSRRC 4'h8
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`define INST_SFU_TEX 4'h9
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`define INST_SFU_RASTER 4'hA
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`define INST_SFU_ROP 4'hB
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`define INST_SFU_CMOV 4'hC
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`define INST_SFU_BITS 4
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`define INST_SFU_CSR(f3) (4'h6 + 4'(f3) - 4'h1)
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`define INST_SFU_IS_WCTL(op) (op <= 5)
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@@ -238,10 +235,6 @@
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///////////////////////////////////////////////////////////////////////////////
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`define NUM_SOCKETS `UP(`NUM_CORES / `SOCKET_SIZE)
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///////////////////////////////////////////////////////////////////////////////
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// non-cacheable tag bits
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`define NC_TAG_BITS 1
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@@ -396,7 +389,7 @@
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end \
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assign ``dst.``field = __reduce_add_r_``dst``field
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`define PERF_CACHE_ADD(dst, src, count) \
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`define PERF_CACHE_REDUCE(dst, src, count) \
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`PERF_REDUCE (dst, src, reads, `PERF_CTR_BITS, count); \
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`PERF_REDUCE (dst, src, writes, `PERF_CTR_BITS, count); \
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`PERF_REDUCE (dst, src, read_misses, `PERF_CTR_BITS, count); \
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