cache bindings and memory perf refactory
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@@ -47,10 +47,12 @@ typedef void* vx_device_h;
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#define VX_ISA_STD_Q (1ull << 16)
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#define VX_ISA_STD_S (1ull << 18)
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#define VX_ISA_STD_U (1ull << 20)
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#define VX_ISA_BASE(flags) (1 << (((flags >> 30) & 0x3) + 4))
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#define VX_ISA_EXT_TEX (1ull << 32)
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#define VX_ISA_EXT_RASTER (1ull << 33)
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#define VX_ISA_EXT_ROP (1ull << 34)
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#define VX_ISA_ARCH(flags) (1 << (((flags >> 30) & 0x3) + 4))
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#define VX_ISA_EXT_ICACHE (1ull << 32)
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#define VX_ISA_EXT_DCACHE (1ull << 33)
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#define VX_ISA_EXT_L2CACHE (1ull << 34)
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#define VX_ISA_EXT_L3CACHE (1ull << 35)
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#define VX_ISA_EXT_SMEM (1ull << 36)
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// device memory types
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#define VX_MEM_TYPE_GLOBAL 0
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