diff --git a/hw/rtl/VX_ibuffer.v b/hw/rtl/VX_ibuffer.v index 358a6d2e..4bc65591 100644 --- a/hw/rtl/VX_ibuffer.v +++ b/hw/rtl/VX_ibuffer.v @@ -38,9 +38,9 @@ module VX_ibuffer #( wire going_empty = empty_r[i] || (alm_empty_r[i] && reading); VX_elastic_buffer #( - .DATAW (DATAW), - .SIZE (`IBUF_SIZE), - .OUTPUT_REG (1) + .DATAW (DATAW), + .SIZE (`IBUF_SIZE), + .OUT_REG (1) ) queue ( .clk (clk), .reset (reset), diff --git a/hw/rtl/VX_icache_stage.v b/hw/rtl/VX_icache_stage.v index 1d48bf3e..59dc1970 100644 --- a/hw/rtl/VX_icache_stage.v +++ b/hw/rtl/VX_icache_stage.v @@ -22,7 +22,7 @@ module VX_icache_stage #( `UNUSED_PARAM (CORE_ID) `UNUSED_VAR (reset) - localparam OUTPUT_REG = 0; + localparam OUT_REG = 0; wire icache_req_fire = icache_req_if.valid && icache_req_if.ready; @@ -64,12 +64,12 @@ module VX_icache_stage #( wire [`NW_BITS-1:0] rsp_wid = rsp_tag; - wire stall_out = ~ifetch_rsp_if.ready && (0 == OUTPUT_REG && ifetch_rsp_if.valid); + wire stall_out = ~ifetch_rsp_if.ready && (0 == OUT_REG && ifetch_rsp_if.valid); VX_pipe_register #( .DATAW (1 + `NW_BITS + `NUM_THREADS + 32 + 32), .RESETW (1), - .DEPTH (OUTPUT_REG) + .DEPTH (OUT_REG) ) pipe_reg ( .clk (clk), .reset (reset), diff --git a/hw/rtl/afu/VX_avs_wrapper.v b/hw/rtl/afu/VX_avs_wrapper.v index 211aff00..34431b91 100644 --- a/hw/rtl/afu/VX_avs_wrapper.v +++ b/hw/rtl/afu/VX_avs_wrapper.v @@ -42,7 +42,7 @@ module VX_avs_wrapper #( ); localparam BANK_ADDRW = `LOG2UP(AVS_BANKS); - localparam OUTPUT_REG = (AVS_BANKS > 2); + localparam OUT_REG = (AVS_BANKS > 2); // Requests handling @@ -78,9 +78,9 @@ module VX_avs_wrapper #( `UNUSED_VAR (req_queue_size) VX_fifo_queue #( - .DATAW (REQ_TAG_WIDTH), - .SIZE (RD_QUEUE_SIZE), - .OUTPUT_REG (!OUTPUT_REG) + .DATAW (REQ_TAG_WIDTH), + .SIZE (RD_QUEUE_SIZE), + .OUT_REG (!OUT_REG) ) rd_req_queue ( .clk (clk), .reset (reset), @@ -122,9 +122,9 @@ module VX_avs_wrapper #( for (genvar i = 0; i < AVS_BANKS; i++) begin VX_fifo_queue #( - .DATAW (AVS_DATA_WIDTH), - .SIZE (RD_QUEUE_SIZE), - .OUTPUT_REG (!OUTPUT_REG) + .DATAW (AVS_DATA_WIDTH), + .SIZE (RD_QUEUE_SIZE), + .OUT_REG (!OUT_REG) ) rd_rsp_queue ( .clk (clk), .reset (reset), @@ -150,7 +150,7 @@ module VX_avs_wrapper #( .NUM_REQS (AVS_BANKS), .DATAW (AVS_DATA_WIDTH + REQ_TAG_WIDTH), .TYPE ("R"), - .BUFFERED (OUTPUT_REG ? 1 : 0) + .BUFFERED (OUT_REG ? 1 : 0) ) rsp_arb ( .clk (clk), .reset (reset), diff --git a/hw/rtl/afu/vortex_afu.sv b/hw/rtl/afu/vortex_afu.sv index b46a3804..6e728b06 100644 --- a/hw/rtl/afu/vortex_afu.sv +++ b/hw/rtl/afu/vortex_afu.sv @@ -520,8 +520,8 @@ VX_mem_arb #( .ADDR_WIDTH (LMEM_ADDR_WIDTH), .TAG_IN_WIDTH (AVS_REQ_TAGW), .TYPE ("P"), - .BUFFERED_REQ (0), - .BUFFERED_RSP (0) + .BUFFERED_REQ (1), + .BUFFERED_RSP (1) ) mem_arb ( .clk (clk), .reset (mem_arb_reset), @@ -731,9 +731,9 @@ end `RESET_RELAY (cci_rdq_reset); VX_fifo_queue #( - .DATAW (CCI_RD_QUEUE_DATAW), - .SIZE (CCI_RD_QUEUE_SIZE), - .OUTPUT_REG (1) + .DATAW (CCI_RD_QUEUE_DATAW), + .SIZE (CCI_RD_QUEUE_SIZE), + .OUT_REG (1) ) cci_rd_req_queue ( .clk (clk), .reset (cci_rdq_reset), diff --git a/hw/rtl/cache/VX_bank.v b/hw/rtl/cache/VX_bank.v index 22db87f1..f1ece0e3 100644 --- a/hw/rtl/cache/VX_bank.v +++ b/hw/rtl/cache/VX_bank.v @@ -465,9 +465,9 @@ module VX_bank #( end VX_elastic_buffer #( - .DATAW (NUM_PORTS * (CORE_TAG_WIDTH + 1 + `WORD_WIDTH + `REQS_BITS)), - .SIZE (CRSQ_SIZE), - .OUTPUT_REG (1 == NUM_BANKS) + .DATAW (NUM_PORTS * (CORE_TAG_WIDTH + 1 + `WORD_WIDTH + `REQS_BITS)), + .SIZE (CRSQ_SIZE), + .OUT_REG (1 == NUM_BANKS) ) core_rsp_req ( .clk (clk), .reset (reset), diff --git a/hw/rtl/cache/VX_cache.v b/hw/rtl/cache/VX_cache.v index b8644b1e..138b452f 100644 --- a/hw/rtl/cache/VX_cache.v +++ b/hw/rtl/cache/VX_cache.v @@ -314,9 +314,9 @@ module VX_cache #( `RESET_RELAY (mrsq_reset); VX_elastic_buffer #( - .DATAW (MEM_TAG_IN_WIDTH + `CACHE_LINE_WIDTH), - .SIZE (MRSQ_SIZE), - .OUTPUT_REG (MRSQ_SIZE > 2) + .DATAW (MEM_TAG_IN_WIDTH + `CACHE_LINE_WIDTH), + .SIZE (MRSQ_SIZE), + .OUT_REG (MRSQ_SIZE > 2) ) mem_rsp_queue ( .clk (clk), .reset (mrsq_reset), diff --git a/hw/rtl/cache/VX_shared_mem.v b/hw/rtl/cache/VX_shared_mem.v index 23f7d8bd..8bcdfda2 100644 --- a/hw/rtl/cache/VX_shared_mem.v +++ b/hw/rtl/cache/VX_shared_mem.v @@ -127,9 +127,9 @@ module VX_shared_mem #( assign core_req_writeonly_unqual = ~(| core_req_read_mask_unqual); VX_elastic_buffer #( - .DATAW (NUM_BANKS * (1 + 1 + `LINE_ADDR_WIDTH + WORD_SIZE + `WORD_WIDTH + CORE_TAG_WIDTH + `REQS_BITS) + NUM_BANKS + 1), - .SIZE (CREQ_SIZE), - .OUTPUT_REG (1) // output should be registered for the data_store addr port + .DATAW (NUM_BANKS * (1 + 1 + `LINE_ADDR_WIDTH + WORD_SIZE + `WORD_WIDTH + CORE_TAG_WIDTH + `REQS_BITS) + NUM_BANKS + 1), + .SIZE (CREQ_SIZE), + .OUT_REG (1) // output should be registered for the data_store addr port ) core_req_queue ( .clk (clk), .reset (reset), diff --git a/hw/rtl/libs/VX_dp_ram.v b/hw/rtl/libs/VX_dp_ram.v index db8e99b8..0e14fa54 100644 --- a/hw/rtl/libs/VX_dp_ram.v +++ b/hw/rtl/libs/VX_dp_ram.v @@ -5,7 +5,7 @@ module VX_dp_ram #( parameter DATAW = 1, parameter SIZE = 1, parameter BYTEENW = 1, - parameter OUTPUT_REG = 0, + parameter OUT_REG = 0, parameter NO_RWCHECK = 0, parameter ADDRW = $clog2(SIZE), parameter LUTRAM = 0, @@ -35,7 +35,7 @@ module VX_dp_ram #( `ifdef SYNTHESIS if (LUTRAM) begin - if (OUTPUT_REG) begin + if (OUT_REG) begin reg [DATAW-1:0] rdata_r; if (BYTEENW > 1) begin `USE_FAST_BRAM reg [BYTEENW-1:0][7:0] ram [SIZE-1:0]; @@ -90,7 +90,7 @@ module VX_dp_ram #( end end end else begin - if (OUTPUT_REG) begin + if (OUT_REG) begin reg [DATAW-1:0] rdata_r; if (BYTEENW > 1) begin @@ -173,7 +173,7 @@ module VX_dp_ram #( end end `else - if (OUTPUT_REG) begin + if (OUT_REG) begin reg [DATAW-1:0] rdata_r; if (BYTEENW > 1) begin reg [BYTEENW-1:0][7:0] ram [SIZE-1:0]; diff --git a/hw/rtl/libs/VX_elastic_buffer.v b/hw/rtl/libs/VX_elastic_buffer.v index 66e8f7ef..ac36fc62 100644 --- a/hw/rtl/libs/VX_elastic_buffer.v +++ b/hw/rtl/libs/VX_elastic_buffer.v @@ -4,7 +4,7 @@ module VX_elastic_buffer #( parameter DATAW = 1, parameter SIZE = 2, - parameter OUTPUT_REG = 0, + parameter OUT_REG = 0, parameter LUTRAM = 0 ) ( input wire clk, @@ -32,8 +32,8 @@ module VX_elastic_buffer #( end else if (SIZE == 2) begin VX_skid_buffer #( - .DATAW (DATAW), - .OUTPUT_REG (OUTPUT_REG) + .DATAW (DATAW), + .OUT_REG (OUT_REG) ) queue ( .clk (clk), .reset (reset), @@ -53,10 +53,10 @@ module VX_elastic_buffer #( wire pop = valid_out && ready_out; VX_fifo_queue #( - .DATAW (DATAW), - .SIZE (SIZE), - .OUTPUT_REG (OUTPUT_REG), - .LUTRAM (LUTRAM) + .DATAW (DATAW), + .SIZE (SIZE), + .OUT_REG (OUT_REG), + .LUTRAM (LUTRAM) ) queue ( .clk (clk), .reset (reset), diff --git a/hw/rtl/libs/VX_fifo_queue.v b/hw/rtl/libs/VX_fifo_queue.v index 5a6e63ae..cc812cfc 100644 --- a/hw/rtl/libs/VX_fifo_queue.v +++ b/hw/rtl/libs/VX_fifo_queue.v @@ -8,7 +8,7 @@ module VX_fifo_queue #( parameter ALM_EMPTY = 1, parameter ADDRW = $clog2(SIZE), parameter SIZEW = $clog2(SIZE+1), - parameter OUTPUT_REG = 0, + parameter OUT_REG = 0, parameter LUTRAM = 1 ) ( input wire clk, @@ -103,7 +103,7 @@ module VX_fifo_queue #( if (SIZE == 2) begin - if (0 == OUTPUT_REG) begin + if (0 == OUT_REG) begin reg [DATAW-1:0] shift_reg [1:0]; @@ -138,7 +138,7 @@ module VX_fifo_queue #( end else begin - if (0 == OUTPUT_REG) begin + if (0 == OUT_REG) begin reg [ADDRW-1:0] rd_ptr_r; reg [ADDRW-1:0] wr_ptr_r; @@ -154,10 +154,10 @@ module VX_fifo_queue #( end VX_dp_ram #( - .DATAW (DATAW), - .SIZE (SIZE), - .OUTPUT_REG (0), - .LUTRAM (LUTRAM) + .DATAW (DATAW), + .SIZE (SIZE), + .OUT_REG (0), + .LUTRAM (LUTRAM) ) dp_ram ( .clk(clk), .wren (push), @@ -197,10 +197,10 @@ module VX_fifo_queue #( end VX_dp_ram #( - .DATAW (DATAW), - .SIZE (SIZE), - .OUTPUT_REG (0), - .LUTRAM (LUTRAM) + .DATAW (DATAW), + .SIZE (SIZE), + .OUT_REG (0), + .LUTRAM (LUTRAM) ) dp_ram ( .clk (clk), .wren (push), diff --git a/hw/rtl/libs/VX_skid_buffer.v b/hw/rtl/libs/VX_skid_buffer.v index 67fd2cd0..d295db55 100644 --- a/hw/rtl/libs/VX_skid_buffer.v +++ b/hw/rtl/libs/VX_skid_buffer.v @@ -5,7 +5,7 @@ module VX_skid_buffer #( parameter DATAW = 1, parameter PASSTHRU = 0, parameter NOBACKPRESSURE = 0, - parameter OUTPUT_REG = 0 + parameter OUT_REG = 0 ) ( input wire clk, input wire reset, @@ -51,7 +51,7 @@ module VX_skid_buffer #( end else begin - if (OUTPUT_REG) begin + if (OUT_REG) begin reg [DATAW-1:0] data_out_r; reg [DATAW-1:0] buffer; diff --git a/hw/rtl/libs/VX_sp_ram.v b/hw/rtl/libs/VX_sp_ram.v index 65ec0837..2cf7bff0 100644 --- a/hw/rtl/libs/VX_sp_ram.v +++ b/hw/rtl/libs/VX_sp_ram.v @@ -5,7 +5,7 @@ module VX_sp_ram #( parameter DATAW = 1, parameter SIZE = 1, parameter BYTEENW = 1, - parameter OUTPUT_REG = 0, + parameter OUT_REG = 0, parameter NO_RWCHECK = 0, parameter ADDRW = $clog2(SIZE), parameter LUTRAM = 0, @@ -34,7 +34,7 @@ module VX_sp_ram #( `ifdef SYNTHESIS if (LUTRAM) begin - if (OUTPUT_REG) begin + if (OUT_REG) begin reg [DATAW-1:0] rdata_r; if (BYTEENW > 1) begin @@ -90,7 +90,7 @@ module VX_sp_ram #( end end end else begin - if (OUTPUT_REG) begin + if (OUT_REG) begin reg [DATAW-1:0] rdata_r; if (BYTEENW > 1) begin @@ -173,7 +173,7 @@ module VX_sp_ram #( end end `else - if (OUTPUT_REG) begin + if (OUT_REG) begin reg [DATAW-1:0] rdata_r; if (BYTEENW > 1) begin reg [BYTEENW-1:0][7:0] ram [SIZE-1:0]; diff --git a/hw/rtl/libs/VX_stream_arbiter.v b/hw/rtl/libs/VX_stream_arbiter.v index f1d89b60..0f23b25d 100644 --- a/hw/rtl/libs/VX_stream_arbiter.v +++ b/hw/rtl/libs/VX_stream_arbiter.v @@ -132,9 +132,9 @@ module VX_stream_arbiter #( for (genvar i = 0; i < LANES; ++i) begin VX_skid_buffer #( - .DATAW (DATAW), - .PASSTHRU (0 == BUFFERED), - .OUTPUT_REG (2 == BUFFERED) + .DATAW (DATAW), + .PASSTHRU (0 == BUFFERED), + .OUT_REG (2 == BUFFERED) ) out_buffer ( .clk (clk), .reset (reset), diff --git a/hw/rtl/libs/VX_stream_demux.v b/hw/rtl/libs/VX_stream_demux.v index e50d7a7c..e55007b8 100644 --- a/hw/rtl/libs/VX_stream_demux.v +++ b/hw/rtl/libs/VX_stream_demux.v @@ -37,9 +37,9 @@ module VX_stream_demux #( for (genvar i = 0; i < NUM_REQS; i++) begin VX_skid_buffer #( - .DATAW (DATAW), - .PASSTHRU (0 == BUFFERED), - .OUTPUT_REG (2 == BUFFERED) + .DATAW (DATAW), + .PASSTHRU (0 == BUFFERED), + .OUT_REG (2 == BUFFERED) ) out_buffer ( .clk (clk), .reset (reset),