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fix quartus build

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This commit is contained in:
Blaise Tine
2020-04-21 00:55:18 -07:00
parent d6255f0445
commit cb0afd3eec
6 changed files with 67 additions and 80 deletions
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2
hw/rtl/VX_gpr.v
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@@ -15,7 +15,7 @@ module VX_gpr (
`ifndef ASIC
assign write_enable = valid_write_request && ((writeback_if.wb != 0)) && (writeback_if.rd != 0);
byte_enabled_simple_dual_port_ram first_ram(
VX_byte_enabled_dual_port_ram be_dp_ram (
.we (write_enable),
.clk (clk),
.reset (reset),

53
hw/rtl/byte_enabled_simple_dual_port_ram.v
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@@ -1,53 +0,0 @@
`include "VX_define.vh"
module byte_enabled_simple_dual_port_ram
(
input clk;
input wire reset;
input wire we;
input wire[4:0] waddr,
input wire[4:0] raddr1,
input wire[4:0] raddr2,
input wire[`NUM_THREADS-1:0] be,
input wire[`NUM_THREADS-1:0][31:0] wdata,
output reg[`NUM_THREADS-1:0][31:0] q1
output reg[`NUM_THREADS-1:0][31:0] q2
);
// integer regi;
// integer threadi;
// Thread Byte Bit
logic [`NUM_THREADS-1:0][3:0][7:0] GPR[31:0];
always @(posedge clk) begin
if (reset) begin
//--
end else begin
if (we) begin
integer thread_ind;
for (thread_ind = 0; thread_ind < `NUM_THREADS; thread_ind = thread_ind + 1) begin
if (be[thread_ind]) begin
GPR[waddr][thread_ind][0] <= wdata[thread_ind][7:0];
GPR[waddr][thread_ind][1] <= wdata[thread_ind][15:8];
GPR[waddr][thread_ind][2] <= wdata[thread_ind][23:16];
GPR[waddr][thread_ind][3] <= wdata[thread_ind][31:24];
end
end
end
// $display("^^^^^^^^^^^^^^^^^^^^^^^");
// for (regi = 0; regi <= 31; regi = regi + 1) begin
// for (threadi = 0; threadi < `NUM_THREADS; threadi = threadi + 1) begin
// if (GPR[regi][threadi] != 0) $display("$%d: %h",regi, GPR[regi][threadi]);
// end
// end
end
end
assign q1 = GPR[raddr1];
assign q2 = GPR[raddr2];
// assign q1 = (raddr1 == waddr && (we)) ? wdata : GPR[raddr1];
// assign q2 = (raddr2 == waddr && (we)) ? wdata : GPR[raddr2];
endmodule

51
hw/rtl/libs/VX_byte_enabled_dual_port_ram.v Normal file
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@@ -0,0 +1,51 @@
`include "VX_define.vh"
module VX_byte_enabled_dual_port_ram (
input wire clk,
input wire reset,
input wire we,
input wire [4:0] waddr,
input wire [4:0] raddr1,
input wire [4:0] raddr2,
input wire [`NUM_THREADS-1:0] be,
input wire [`NUM_THREADS-1:0][31:0] wdata,
output reg [`NUM_THREADS-1:0][31:0] q1,
output reg [`NUM_THREADS-1:0][31:0] q2
);
// integer regi;
// integer threadi;
// Thread Byte Bit
logic [`NUM_THREADS-1:0][3:0][7:0] ram[31:0];
always @(posedge clk) begin
if (reset) begin
//--
end else begin
if (we) begin
integer thread_ind;
for (thread_ind = 0; thread_ind < `NUM_THREADS; thread_ind = thread_ind + 1) begin
if (be[thread_ind]) begin
ram[waddr][thread_ind][0] <= wdata[thread_ind][7:0];
ram[waddr][thread_ind][1] <= wdata[thread_ind][15:8];
ram[waddr][thread_ind][2] <= wdata[thread_ind][23:16];
ram[waddr][thread_ind][3] <= wdata[thread_ind][31:24];
end
end
end
// $display("^^^^^^^^^^^^^^^^^^^^^^^");
// for (regi = 0; regi <= 31; regi = regi + 1) begin
// for (threadi = 0; threadi < `NUM_THREADS; threadi = threadi + 1) begin
// if (ram[regi][threadi] != 0) $display("$%d: %h",regi, ram[regi][threadi]);
// end
// end
end
end
assign q1 = ram[raddr1];
assign q2 = ram[raddr2];
// assign q1 = (raddr1 == waddr && (we)) ? wdata : ram[raddr1];
// assign q2 = (raddr2 == waddr && (we)) ? wdata : ram[raddr2];
endmodule

6
hw/rtl/libs/VX_mult.v
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@@ -9,9 +9,9 @@ module VX_mult #(
parameter PIPELINE=0,
parameter FORCE_LE="NO"
) (
input clock;
input aclr;
input clken;
input clock,
input aclr,
input clken,
input [WIDTHA-1:0] dataa,
input [WIDTHB-1:0] datab,