diff --git a/.DS_Store b/.DS_Store index ea8a9c95..884dee55 100644 Binary files a/.DS_Store and b/.DS_Store differ diff --git a/rtl/Makefile b/rtl/Makefile index 8dd8f16d..af01b177 100644 --- a/rtl/Makefile +++ b/rtl/Makefile @@ -10,8 +10,6 @@ VERILATOR: RUNFILE: VERILATOR (cd obj_dir && make -j -f VVortex.mk) - - clean: rm ./obj_dir/* diff --git a/rtl/VX_decode.v b/rtl/VX_decode.v index c8bc6e2b..93440281 100644 --- a/rtl/VX_decode.v +++ b/rtl/VX_decode.v @@ -11,6 +11,7 @@ module VX_decode( input wire[31:0] in_write_data, input wire[4:0] in_rd, input wire[1:0] in_wb, + input wire in_wb_valid, // FORWARDING INPUTS input wire in_src1_fwd, @@ -106,6 +107,7 @@ module VX_decode( VX_register_file vx_register_file( .clk(clk), + .in_valid(in_wb_valid), .in_write_register(write_register), .in_rd(in_rd), .in_data(in_write_data), diff --git a/rtl/VX_memory.v b/rtl/VX_memory.v index 06de357f..c09e9049 100644 --- a/rtl/VX_memory.v +++ b/rtl/VX_memory.v @@ -32,6 +32,7 @@ module VX_memory ( output wire[31:0] out_cache_driver_in_address, output wire[2:0] out_cache_driver_in_mem_read, output wire[2:0] out_cache_driver_in_mem_write, + output wire out_cache_driver_in_valid, output wire[31:0] out_cache_driver_in_data ); @@ -47,22 +48,20 @@ module VX_memory ( assign out_cache_driver_in_mem_read = in_mem_read; assign out_cache_driver_in_mem_write = in_mem_write; assign out_cache_driver_in_data = in_rd2; - + assign out_cache_driver_in_valid = in_valid; assign out_mem_result = in_cache_driver_out_data; assign out_alu_result = in_alu_result; - assign out_rd = in_rd; - assign out_wb = in_wb; - assign out_rs1 = in_rs1; - assign out_rs2 = in_rs2; - assign out_PC_next = in_PC_next; - - assign out_valid = in_valid; + assign out_rd = in_rd; + assign out_wb = in_wb; + assign out_rs1 = in_rs1; + assign out_rs2 = in_rs2; + assign out_PC_next = in_PC_next; + assign out_valid = in_valid; assign out_branch_dest = $signed(in_curr_PC) + ($signed(in_branch_offset) << 1); - - + always @(*) begin case(in_branch_type) `BEQ: out_branch_dir = (in_alu_result == 0) ? `TAKEN : `NOT_TAKEN; diff --git a/rtl/VX_register_file.v b/rtl/VX_register_file.v index ca7e8bf1..d53552ff 100644 --- a/rtl/VX_register_file.v +++ b/rtl/VX_register_file.v @@ -2,6 +2,7 @@ module VX_register_file ( input wire clk, + input wire in_valid, input wire in_write_register, input wire[4:0] in_rd, input wire[31:0] in_data, @@ -30,7 +31,7 @@ module VX_register_file ( assign write_data = in_data; assign write_register = in_rd; - assign write_enable = in_write_register && (in_rd != 5'h0); + assign write_enable = in_write_register && (in_rd != 5'h0) && in_valid; always @(posedge clk) begin if(write_enable) begin diff --git a/rtl/Vortex.v b/rtl/Vortex.v index 3497ce99..297806c2 100644 --- a/rtl/Vortex.v +++ b/rtl/Vortex.v @@ -8,7 +8,8 @@ module Vortex( output wire[31:0] out_cache_driver_in_address, output wire[2:0] out_cache_driver_in_mem_read, output wire[2:0] out_cache_driver_in_mem_write, - output wire[31:0] out_cache_driver_in_data + output wire out_cache_driver_in_valid, + output wire[31:0] out_cache_driver_in_data ); @@ -213,7 +214,7 @@ VX_decode vx_decode( .in_write_data(writeback_write_data), .in_rd(writeback_rd), .in_wb(writeback_wb), - + .in_wb_valid(m_w_valid), .in_src1_fwd(forwarding_src1_fwd), .in_src1_fwd_data(forwarding_src1_fwd_data), .in_src2_fwd(forwarding_src2_fwd), @@ -406,7 +407,8 @@ VX_memory vx_memory( .out_cache_driver_in_address(out_cache_driver_in_address), .out_cache_driver_in_mem_read(out_cache_driver_in_mem_read), .out_cache_driver_in_mem_write(out_cache_driver_in_mem_write), - .out_cache_driver_in_data(out_cache_driver_in_data) + .out_cache_driver_in_data(out_cache_driver_in_data), + .out_cache_driver_in_valid(out_cache_driver_in_valid) ); VX_m_w_reg vx_m_w_reg( diff --git a/rtl/obj_dir/VVortex b/rtl/obj_dir/VVortex index 280450a5..d5d4f191 100755 Binary files a/rtl/obj_dir/VVortex and b/rtl/obj_dir/VVortex differ diff --git a/rtl/obj_dir/VVortex.cpp b/rtl/obj_dir/VVortex.cpp index f60841cb..955fcce1 100644 --- a/rtl/obj_dir/VVortex.cpp +++ b/rtl/obj_dir/VVortex.cpp @@ -176,8 +176,8 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) VL_SIG(__Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__reg_data__v0,31,0); VL_SIG(__Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__reg_data__v1,31,0); // Body - __Vdlyvset__Vortex__DOT__vx_decode__DOT__vx_register_file__DOT__registers__v0 = 0U; __Vdlyvset__Vortex__DOT__vx_csr_handler__DOT__csr__v0 = 0U; + __Vdlyvset__Vortex__DOT__vx_decode__DOT__vx_register_file__DOT__registers__v0 = 0U; // ALWAYS at VX_e_m_reg.v:113 __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__reg_data__v0 = vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_reg_data @@ -235,9 +235,18 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal_dest = (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data [0U] + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__jal_offset); - // ALWAYS at VX_register_file.v:35 - if (((0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) - & (0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd)))) { + // ALWAYS at VX_csr_handler.v:43 + if (vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__is_csr) { + __Vdlyvval__Vortex__DOT__vx_csr_handler__DOT__csr__v0 + = (0xfffU & vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__csr_result); + __Vdlyvset__Vortex__DOT__vx_csr_handler__DOT__csr__v0 = 1U; + __Vdlyvdim0__Vortex__DOT__vx_csr_handler__DOT__csr__v0 + = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__csr_address; + } + // ALWAYS at VX_register_file.v:36 + if ((((0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + & (0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd))) + & (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid))) { __Vdlyvval__Vortex__DOT__vx_decode__DOT__vx_register_file__DOT__registers__v0 = ((3U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) ? vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next @@ -248,14 +257,6 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) __Vdlyvdim0__Vortex__DOT__vx_decode__DOT__vx_register_file__DOT__registers__v0 = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd; } - // ALWAYS at VX_csr_handler.v:43 - if (vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__is_csr) { - __Vdlyvval__Vortex__DOT__vx_csr_handler__DOT__csr__v0 - = (0xfffU & vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__csr_result); - __Vdlyvset__Vortex__DOT__vx_csr_handler__DOT__csr__v0 = 1U; - __Vdlyvdim0__Vortex__DOT__vx_csr_handler__DOT__csr__v0 - = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__csr_address; - } // ALWAYS at VX_d_e_reg.v:132 __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__reg_data__v0 = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) @@ -272,16 +273,16 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) = __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__reg_data__v0; vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__reg_data[0U] = __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__reg_data__v1; - // ALWAYSPOST at VX_register_file.v:38 - if (__Vdlyvset__Vortex__DOT__vx_decode__DOT__vx_register_file__DOT__registers__v0) { - vlTOPp->Vortex__DOT__vx_decode__DOT__vx_register_file__DOT__registers[__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__vx_register_file__DOT__registers__v0] - = __Vdlyvval__Vortex__DOT__vx_decode__DOT__vx_register_file__DOT__registers__v0; - } // ALWAYSPOST at VX_csr_handler.v:45 if (__Vdlyvset__Vortex__DOT__vx_csr_handler__DOT__csr__v0) { vlTOPp->Vortex__DOT__vx_csr_handler__DOT__csr[__Vdlyvdim0__Vortex__DOT__vx_csr_handler__DOT__csr__v0] = __Vdlyvval__Vortex__DOT__vx_csr_handler__DOT__csr__v0; } + // ALWAYSPOST at VX_register_file.v:39 + if (__Vdlyvset__Vortex__DOT__vx_decode__DOT__vx_register_file__DOT__registers__v0) { + vlTOPp->Vortex__DOT__vx_decode__DOT__vx_register_file__DOT__registers[__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__vx_register_file__DOT__registers__v0] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__vx_register_file__DOT__registers__v0; + } // ALWAYSPOST at VX_d_e_reg.v:137 vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data[1U] = __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__reg_data__v0; @@ -308,8 +309,6 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__itype_immed = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) ? 0xdeadbeefU : vlTOPp->Vortex__DOT__decode_itype_immed); - // ALWAYS at VX_m_w_reg.v:60 - vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid; vlTOPp->out_cache_driver_in_mem_write = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__mem_write; // ALWAYS at VX_d_e_reg.v:132 vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__mem_write @@ -380,18 +379,6 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) >> 0x14U)))) ? 0xb0000000U : 0xdeadbeefU) : 0xdeadbeefU)))); - // ALWAYS at VX_m_w_reg.v:60 - vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__mem_result - = vlTOPp->in_cache_driver_out_data; - // ALWAYS at VX_m_w_reg.v:60 - vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result - = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result; - // ALWAYS at VX_m_w_reg.v:60 - vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next; - // ALWAYS at VX_m_w_reg.v:60 - vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__rd; - // ALWAYS at VX_m_w_reg.v:60 - vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb; // ALWAYS at VX_e_m_reg.v:113 vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__csr_address = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__csr_address; @@ -408,6 +395,20 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) ? (vlTOPp->Vortex__DOT__csr_decode_csr_data & ((IData)(0xffffffffU) - vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__csr_mask)) : 0xdeadbeefU))); + // ALWAYS at VX_m_w_reg.v:60 + vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__mem_result + = vlTOPp->in_cache_driver_out_data; + // ALWAYS at VX_m_w_reg.v:60 + vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result + = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result; + // ALWAYS at VX_m_w_reg.v:60 + vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid; + // ALWAYS at VX_m_w_reg.v:60 + vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next; + // ALWAYS at VX_m_w_reg.v:60 + vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__rd; + // ALWAYS at VX_m_w_reg.v:60 + vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb; vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data[1U] = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data [1U]; @@ -446,20 +447,9 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) [0U]; vlTOPp->out_cache_driver_in_data = vlTOPp->Vortex__DOT__e_m_reg_data [1U]; - // ALWAYS at VX_e_m_reg.v:113 - vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid; vlTOPp->Vortex__DOT__execute_branch_stall = ((0U != (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__branch_type)) | (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__jal)); - // ALWAYS at VX_e_m_reg.v:113 - vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result - = vlTOPp->Vortex__DOT__execute_alu_result; - // ALWAYS at VX_e_m_reg.v:113 - vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out; - // ALWAYS at VX_e_m_reg.v:113 - vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__rd = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd; - // ALWAYS at VX_e_m_reg.v:113 - vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb; // ALWAYS at VX_d_e_reg.v:132 vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__csr_address = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) @@ -484,6 +474,17 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction))) ? (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__mul_alu) : (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__temp_final_alu))); + // ALWAYS at VX_e_m_reg.v:113 + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result + = vlTOPp->Vortex__DOT__execute_alu_result; + // ALWAYS at VX_e_m_reg.v:113 + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid; + // ALWAYS at VX_e_m_reg.v:113 + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out; + // ALWAYS at VX_e_m_reg.v:113 + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__rd = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd; + // ALWAYS at VX_e_m_reg.v:113 + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb; vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data[1U] = vlTOPp->Vortex__DOT__d_e_reg_data[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data[0U] @@ -500,12 +501,8 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu__in_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data [0U]; - // ALWAYS at VX_d_e_reg.v:132 - vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid = ( - (~ (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling)) - & (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid)); vlTOPp->out_cache_driver_in_address = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result; - // ALWAYS at VX_memory.v:66 + // ALWAYS at VX_memory.v:65 vlTOPp->Vortex__DOT__memory_branch_dir = (1U & ((4U & (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type)) @@ -543,6 +540,11 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) ((IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type) & (0U == vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result))))); + vlTOPp->out_cache_driver_in_valid = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid; + // ALWAYS at VX_d_e_reg.v:132 + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid = ( + (~ (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling)) + & (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid)); // ALWAYS at VX_d_e_reg.v:132 vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) @@ -818,12 +820,12 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__3(VVortex__Syms* __restrict vlSymsp) VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex::_sequent__TOP__3\n"); ); VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; // Body - // ALWAYS at VX_register_file.v:42 + // ALWAYS at VX_register_file.v:43 vlTOPp->Vortex__DOT__vx_decode__DOT__rd2_register = vlTOPp->Vortex__DOT__vx_decode__DOT__vx_register_file__DOT__registers [(0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction >> 0x14U))]; - // ALWAYS at VX_register_file.v:42 + // ALWAYS at VX_register_file.v:43 vlTOPp->Vortex__DOT__vx_decode__DOT__rd1_register = vlTOPp->Vortex__DOT__vx_decode__DOT__vx_register_file__DOT__registers [(0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction @@ -854,7 +856,7 @@ void VVortex::_settle__TOP__4(VVortex__Syms* __restrict vlSymsp) { (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction >> 0x14U) : 0x55U)); - // ALWAYS at VX_decode.v:314 + // ALWAYS at VX_decode.v:316 vlTOPp->__Vtableidx1 = (7U & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction >> 0xcU)); vlTOPp->Vortex__DOT__vx_decode__DOT__mul_alu = @@ -880,7 +882,7 @@ void VVortex::_settle__TOP__4(VVortex__Syms* __restrict vlSymsp) { (7U & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction >> 0xcU)))); - // ALWAYS at VX_decode.v:264 + // ALWAYS at VX_decode.v:266 vlTOPp->Vortex__DOT__decode_branch_type = ((0x63U == (0x7fU @@ -911,7 +913,7 @@ void VVortex::_settle__TOP__4(VVortex__Syms* __restrict vlSymsp) { ? 2U : 1U))) : 0U); - // ALWAYS at VX_decode.v:253 + // ALWAYS at VX_decode.v:255 vlTOPp->Vortex__DOT__decode_itype_immed = ((0x40U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) ? ( @@ -1254,7 +1256,7 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__6(VVortex__Syms* __restrict vlSymsp) (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction >> 0x14U) : 0x55U)); - // ALWAYS at VX_decode.v:314 + // ALWAYS at VX_decode.v:316 vlTOPp->__Vtableidx1 = (7U & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction >> 0xcU)); vlTOPp->Vortex__DOT__vx_decode__DOT__mul_alu = @@ -1280,7 +1282,7 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__6(VVortex__Syms* __restrict vlSymsp) (7U & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction >> 0xcU)))); - // ALWAYS at VX_decode.v:264 + // ALWAYS at VX_decode.v:266 vlTOPp->Vortex__DOT__decode_branch_type = ((0x63U == (0x7fU @@ -1321,7 +1323,7 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__6(VVortex__Syms* __restrict vlSymsp) >> 0xfU)) == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd)) & (0U != (0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction >> 0xfU)))) & (0U != (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb))); - // ALWAYS at VX_decode.v:253 + // ALWAYS at VX_decode.v:255 vlTOPp->Vortex__DOT__decode_itype_immed = ((0x40U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) ? ( @@ -1652,8 +1654,9 @@ void VVortex::_settle__TOP__7(VVortex__Syms* __restrict vlSymsp) { vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data[0U] = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__reg_data [0U]; + vlTOPp->out_cache_driver_in_valid = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid; vlTOPp->out_cache_driver_in_address = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result; - // ALWAYS at VX_memory.v:66 + // ALWAYS at VX_memory.v:65 vlTOPp->Vortex__DOT__memory_branch_dir = (1U & ((4U & (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type)) @@ -2210,6 +2213,7 @@ void VVortex::_ctor_var_reset() { out_cache_driver_in_address = VL_RAND_RESET_I(32); out_cache_driver_in_mem_read = VL_RAND_RESET_I(3); out_cache_driver_in_mem_write = VL_RAND_RESET_I(3); + out_cache_driver_in_valid = VL_RAND_RESET_I(1); out_cache_driver_in_data = VL_RAND_RESET_I(32); Vortex__DOT__decode_csr_address = VL_RAND_RESET_I(12); { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { diff --git a/rtl/obj_dir/VVortex.h b/rtl/obj_dir/VVortex.h index e319e4b6..e831cf88 100644 --- a/rtl/obj_dir/VVortex.h +++ b/rtl/obj_dir/VVortex.h @@ -25,6 +25,7 @@ VL_MODULE(VVortex) { VL_IN8(reset,0,0); VL_OUT8(out_cache_driver_in_mem_read,2,0); VL_OUT8(out_cache_driver_in_mem_write,2,0); + VL_OUT8(out_cache_driver_in_valid,0,0); VL_IN(fe_instruction,31,0); VL_IN(in_cache_driver_out_data,31,0); VL_OUT(curr_PC,31,0); diff --git a/rtl/obj_dir/VVortex.mk b/rtl/obj_dir/VVortex.mk index eedf8cab..edc5fcca 100644 --- a/rtl/obj_dir/VVortex.mk +++ b/rtl/obj_dir/VVortex.mk @@ -10,7 +10,7 @@ default: VVortex # Perl executable (from $PERL) PERL = perl # Path to Verilator kit (from $VERILATOR_ROOT) -VERILATOR_ROOT = /usr/local/share/verilator +VERILATOR_ROOT = /usr/local/Cellar/verilator/4.010/share/verilator # SystemC include directory with systemc.h (from $SYSTEMC_INCLUDE) SYSTEMC_INCLUDE ?= # SystemC library directory with libsystemc.a (from $SYSTEMC_LIBDIR) diff --git a/rtl/obj_dir/VVortex__ALL.a b/rtl/obj_dir/VVortex__ALL.a index 0bd211bd..d77cb3e5 100644 Binary files a/rtl/obj_dir/VVortex__ALL.a and b/rtl/obj_dir/VVortex__ALL.a differ diff --git a/rtl/obj_dir/VVortex__ALLcls.d b/rtl/obj_dir/VVortex__ALLcls.d index 94b032eb..1e080335 100644 --- a/rtl/obj_dir/VVortex__ALLcls.d +++ b/rtl/obj_dir/VVortex__ALLcls.d @@ -1,3 +1,4 @@ VVortex__ALLcls.o: VVortex__ALLcls.cpp VVortex.cpp VVortex.h \ - /usr/local/share/verilator/include/verilated.h \ - /usr/local/share/verilator/include/verilatedos.h VVortex__Syms.h + /usr/local/Cellar/verilator/4.010/share/verilator/include/verilated.h \ + /usr/local/Cellar/verilator/4.010/share/verilator/include/verilatedos.h \ + VVortex__Syms.h diff --git a/rtl/obj_dir/VVortex__ALLcls.o b/rtl/obj_dir/VVortex__ALLcls.o index 69e981f3..0056da2f 100644 Binary files a/rtl/obj_dir/VVortex__ALLcls.o and b/rtl/obj_dir/VVortex__ALLcls.o differ diff --git a/rtl/obj_dir/VVortex__ALLsup.d b/rtl/obj_dir/VVortex__ALLsup.d index 8cbbb061..41db4492 100644 --- a/rtl/obj_dir/VVortex__ALLsup.d +++ b/rtl/obj_dir/VVortex__ALLsup.d @@ -1,3 +1,4 @@ VVortex__ALLsup.o: VVortex__ALLsup.cpp VVortex__Syms.cpp VVortex__Syms.h \ - /usr/local/share/verilator/include/verilated.h \ - /usr/local/share/verilator/include/verilatedos.h VVortex.h + /usr/local/Cellar/verilator/4.010/share/verilator/include/verilated.h \ + /usr/local/Cellar/verilator/4.010/share/verilator/include/verilatedos.h \ + VVortex.h diff --git a/rtl/obj_dir/VVortex__ALLsup.o b/rtl/obj_dir/VVortex__ALLsup.o index 93a2deb0..646b75f2 100644 Binary files a/rtl/obj_dir/VVortex__ALLsup.o and b/rtl/obj_dir/VVortex__ALLsup.o differ diff --git a/rtl/obj_dir/VVortex__ver.d b/rtl/obj_dir/VVortex__ver.d index e8d44c41..7c599475 100644 --- a/rtl/obj_dir/VVortex__ver.d +++ b/rtl/obj_dir/VVortex__ver.d @@ -1 +1 @@ -obj_dir/VVortex.cpp obj_dir/VVortex.h obj_dir/VVortex.mk obj_dir/VVortex__Syms.cpp obj_dir/VVortex__Syms.h obj_dir/VVortex__ver.d obj_dir/VVortex_classes.mk : /usr/local/bin/verilator_bin /usr/local/bin/verilator_bin VX_alu.v VX_csr_handler.v VX_d_e_reg.v VX_decode.v VX_define.v VX_e_m_reg.v VX_execute.v VX_f_d_reg.v VX_fetch.v VX_forwarding.v VX_m_w_reg.v VX_memory.v VX_register_file.v VX_writeback.v Vortex.v +obj_dir/VVortex.cpp obj_dir/VVortex.h obj_dir/VVortex.mk obj_dir/VVortex__Syms.cpp obj_dir/VVortex__Syms.h obj_dir/VVortex__ver.d obj_dir/VVortex_classes.mk : /usr/local/Cellar/verilator/4.010/bin/verilator_bin /usr/local/Cellar/verilator/4.010/bin/verilator_bin VX_alu.v VX_csr_handler.v VX_d_e_reg.v VX_decode.v VX_define.v VX_e_m_reg.v VX_execute.v VX_f_d_reg.v VX_fetch.v VX_forwarding.v VX_m_w_reg.v VX_memory.v VX_register_file.v VX_writeback.v Vortex.v diff --git a/rtl/obj_dir/VVortex__verFiles.dat b/rtl/obj_dir/VVortex__verFiles.dat index b6f7c66c..ad661920 100644 --- a/rtl/obj_dir/VVortex__verFiles.dat +++ b/rtl/obj_dir/VVortex__verFiles.dat @@ -1,26 +1,26 @@ # DESCRIPTION: Verilator output: Timestamp data for --skip-identical. Delete at will. C "-Wall -cc Vortex.v VX_alu.v VX_fetch.v VX_f_d_reg.v VX_decode.v VX_register_file.v VX_d_e_reg.v VX_execute.v VX_e_m_reg.v VX_memory.v VX_m_w_reg.v VX_writeback.v VX_csr_handler.v VX_forwarding.v --exe test_bench.cpp" -S 5163137 401094 1553636247 412576209 1553636247 412576209 "/usr/local/bin/verilator_bin" -S 2782 5518365 1553641993 611294425 1553641993 611294425 "VX_alu.v" -S 1495 5518326 1553635490 361093288 1553635490 361093288 "VX_csr_handler.v" -S 4603 5518327 1553640386 543770135 1553640386 543770135 "VX_d_e_reg.v" -S 9287 5518328 1553639887 889455624 1553639887 889455624 "VX_decode.v" -S 1503 5518330 1553635490 361093288 1553635490 361093288 "VX_define.v" -S 3547 5518331 1553641200 263546964 1553641200 263546964 "VX_e_m_reg.v" -S 2645 5518332 1553641998 83315687 1553641998 83315687 "VX_execute.v" -S 1120 5518333 1553635490 361093288 1553635490 361093288 "VX_f_d_reg.v" -S 3537 5518334 1553635490 361093288 1553635490 361093288 "VX_fetch.v" -S 5020 5518335 1553635490 361093288 1553635490 361093288 "VX_forwarding.v" -S 1578 5518336 1553635490 361093288 1553635490 361093288 "VX_m_w_reg.v" -S 2606 5518337 1553635490 361093288 1553635490 361093288 "VX_memory.v" -S 958 5518338 1553635490 361093288 1553635490 361093288 "VX_register_file.v" -S 806 5518339 1553635490 361093288 1553635490 361093288 "VX_writeback.v" -S 12732 5518364 1553641238 871726160 1553641238 871726160 "Vortex.v" -T 100811 5518343 1553642016 159401627 1553642016 159401627 "obj_dir/VVortex.cpp" -T 8941 5518342 1553642016 159401627 1553642016 159401627 "obj_dir/VVortex.h" -T 1777 5518345 1553642016 159401627 1553642016 159401627 "obj_dir/VVortex.mk" -T 530 5518341 1553642016 159401627 1553642016 159401627 "obj_dir/VVortex__Syms.cpp" -T 711 5518340 1553642016 159401627 1553642016 159401627 "obj_dir/VVortex__Syms.h" -T 418 5518346 1553642016 159401627 1553642016 159401627 "obj_dir/VVortex__ver.d" -T 0 0 1553642016 163401646 1553642016 163401646 "obj_dir/VVortex__verFiles.dat" -T 1159 5518344 1553642016 159401627 1553642016 159401627 "obj_dir/VVortex_classes.mk" +S 4608404 12889046060 1553037052 0 1548678579 0 "/usr/local/Cellar/verilator/4.010/bin/verilator_bin" +S 2782 12889318286 1553658869 0 1553658869 0 "VX_alu.v" +S 1495 12889087229 1553211178 0 1553211178 0 "VX_csr_handler.v" +S 4603 12889318287 1553658869 0 1553658869 0 "VX_d_e_reg.v" +S 9346 12889318288 1553659302 0 1553659302 0 "VX_decode.v" +S 1503 12889079483 1553237629 0 1553237629 0 "VX_define.v" +S 3547 12889318289 1553658869 0 1553658869 0 "VX_e_m_reg.v" +S 2653 12889318290 1553658869 0 1553658869 0 "VX_execute.v" +S 1120 12889050060 1553236935 0 1553236935 0 "VX_f_d_reg.v" +S 3537 12889047675 1553236929 0 1553236929 0 "VX_fetch.v" +S 5020 12889086478 1553236985 0 1553236985 0 "VX_forwarding.v" +S 1578 12889085814 1553211072 0 1553211072 0 "VX_m_w_reg.v" +S 2741 12889084513 1553659625 0 1553659625 0 "VX_memory.v" +S 1000 12889070228 1553659195 0 1553659195 0 "VX_register_file.v" +S 806 12889086287 1553236964 0 1553236964 0 "VX_writeback.v" +S 12860 12889318291 1553659648 0 1553659648 0 "Vortex.v" +T 101094 12889318706 1553659652 0 1553659652 0 "obj_dir/VVortex.cpp" +T 8985 12889318705 1553659652 0 1553659652 0 "obj_dir/VVortex.h" +T 1800 12889318708 1553659652 0 1553659652 0 "obj_dir/VVortex.mk" +T 530 12889318704 1553659652 0 1553659652 0 "obj_dir/VVortex__Syms.cpp" +T 711 12889318703 1553659652 0 1553659652 0 "obj_dir/VVortex__Syms.h" +T 464 12889318709 1553659652 0 1553659652 0 "obj_dir/VVortex__ver.d" +T 0 0 1553659652 0 1553659652 0 "obj_dir/VVortex__verFiles.dat" +T 1159 12889318707 1553659652 0 1553659652 0 "obj_dir/VVortex_classes.mk" diff --git a/rtl/obj_dir/test_bench.d b/rtl/obj_dir/test_bench.d index e70b646c..b918f78f 100644 --- a/rtl/obj_dir/test_bench.d +++ b/rtl/obj_dir/test_bench.d @@ -1,3 +1,4 @@ test_bench.o: ../test_bench.cpp ../test_bench.h ../VX_define.h ../ram.h \ - VVortex.h /usr/local/share/verilator/include/verilated.h \ - /usr/local/share/verilator/include/verilatedos.h + VVortex.h \ + /usr/local/Cellar/verilator/4.010/share/verilator/include/verilated.h \ + /usr/local/Cellar/verilator/4.010/share/verilator/include/verilatedos.h diff --git a/rtl/obj_dir/test_bench.o b/rtl/obj_dir/test_bench.o index be0134dc..2f052a38 100644 Binary files a/rtl/obj_dir/test_bench.o and b/rtl/obj_dir/test_bench.o differ diff --git a/rtl/obj_dir/verilated.d b/rtl/obj_dir/verilated.d index 4f8241f8..8fb42837 100644 --- a/rtl/obj_dir/verilated.d +++ b/rtl/obj_dir/verilated.d @@ -1,8 +1,9 @@ -verilated.o: /usr/local/share/verilator/include/verilated.cpp \ - /usr/local/share/verilator/include/verilatedos.h \ - /usr/local/share/verilator/include/verilated_imp.h \ - /usr/local/share/verilator/include/verilated.h \ - /usr/local/share/verilator/include/verilated_heavy.h \ - /usr/local/share/verilator/include/verilated_syms.h \ - /usr/local/share/verilator/include/verilated_sym_props.h \ - /usr/local/share/verilator/include/verilated_config.h +verilated.o: \ + /usr/local/Cellar/verilator/4.010/share/verilator/include/verilated.cpp \ + /usr/local/Cellar/verilator/4.010/share/verilator/include/verilatedos.h \ + /usr/local/Cellar/verilator/4.010/share/verilator/include/verilated_imp.h \ + /usr/local/Cellar/verilator/4.010/share/verilator/include/verilated.h \ + /usr/local/Cellar/verilator/4.010/share/verilator/include/verilated_heavy.h \ + /usr/local/Cellar/verilator/4.010/share/verilator/include/verilated_syms.h \ + /usr/local/Cellar/verilator/4.010/share/verilator/include/verilated_sym_props.h \ + /usr/local/Cellar/verilator/4.010/share/verilator/include/verilated_config.h diff --git a/rtl/obj_dir/verilated.o b/rtl/obj_dir/verilated.o index 021e7b7b..7edd40bb 100644 Binary files a/rtl/obj_dir/verilated.o and b/rtl/obj_dir/verilated.o differ diff --git a/rtl/results.txt b/rtl/results.txt index 5f5d1d80..67713507 100644 --- a/rtl/results.txt +++ b/rtl/results.txt @@ -5,7 +5,7 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.01843 -# time to simulate: 6.12641e-322 milliseconds +# time to simulate: 6.95312e-310 milliseconds # GRADE: PASSING **************** ../../emulator/riscv_tests/rv32ui-p-addi.hex **************** @@ -14,7 +14,7 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.03526 -# time to simulate: 6.12641e-322 milliseconds +# time to simulate: 6.95312e-310 milliseconds # GRADE: PASSING **************** ../../emulator/riscv_tests/rv32ui-p-and.hex **************** @@ -23,7 +23,7 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.01849 -# time to simulate: 6.12641e-322 milliseconds +# time to simulate: 6.95312e-310 milliseconds # GRADE: PASSING **************** ../../emulator/riscv_tests/rv32ui-p-andi.hex **************** @@ -32,7 +32,7 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.04472 -# time to simulate: 6.12641e-322 milliseconds +# time to simulate: 6.95312e-310 milliseconds # GRADE: PASSING **************** ../../emulator/riscv_tests/rv32ui-p-auipc.hex **************** @@ -41,7 +41,7 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.16923 -# time to simulate: 6.12641e-322 milliseconds +# time to simulate: 6.95312e-310 milliseconds # GRADE: PASSING **************** ../../emulator/riscv_tests/rv32ui-p-beq.hex **************** @@ -50,7 +50,7 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.02552 -# time to simulate: 6.12641e-322 milliseconds +# time to simulate: 6.95312e-310 milliseconds # GRADE: PASSING **************** ../../emulator/riscv_tests/rv32ui-p-bge.hex **************** @@ -59,7 +59,7 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.02355 -# time to simulate: 6.12641e-322 milliseconds +# time to simulate: 6.95312e-310 milliseconds # GRADE: PASSING **************** ../../emulator/riscv_tests/rv32ui-p-bgeu.hex **************** @@ -68,7 +68,7 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.02236 -# time to simulate: 6.12641e-322 milliseconds +# time to simulate: 6.95312e-310 milliseconds # GRADE: PASSING **************** ../../emulator/riscv_tests/rv32ui-p-blt.hex **************** @@ -77,7 +77,7 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.02552 -# time to simulate: 6.12641e-322 milliseconds +# time to simulate: 6.95312e-310 milliseconds # GRADE: PASSING **************** ../../emulator/riscv_tests/rv32ui-p-bltu.hex **************** @@ -86,7 +86,7 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.02412 -# time to simulate: 6.12641e-322 milliseconds +# time to simulate: 6.95312e-310 milliseconds # GRADE: PASSING **************** ../../emulator/riscv_tests/rv32ui-p-bne.hex **************** @@ -95,7 +95,7 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.02552 -# time to simulate: 6.12641e-322 milliseconds +# time to simulate: 6.95312e-310 milliseconds # GRADE: PASSING **************** ../../emulator/riscv_tests/rv32ui-p-jal.hex **************** @@ -104,7 +104,7 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.18033 -# time to simulate: 6.12641e-322 milliseconds +# time to simulate: 6.95312e-310 milliseconds # GRADE: PASSING **************** ../../emulator/riscv_tests/rv32ui-p-jalr.hex **************** @@ -113,7 +113,7 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.07971 -# time to simulate: 6.12641e-322 milliseconds +# time to simulate: 6.95312e-310 milliseconds # GRADE: PASSING **************** ../../emulator/riscv_tests/rv32ui-p-lb.hex **************** @@ -122,7 +122,7 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.03323 -# time to simulate: 6.12641e-322 milliseconds +# time to simulate: 6.95312e-310 milliseconds # GRADE: PASSING **************** ../../emulator/riscv_tests/rv32ui-p-lbu.hex **************** @@ -131,7 +131,7 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.03323 -# time to simulate: 6.12641e-322 milliseconds +# time to simulate: 6.95312e-310 milliseconds # GRADE: PASSING **************** ../../emulator/riscv_tests/rv32ui-p-lh.hex **************** @@ -140,7 +140,7 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.03245 -# time to simulate: 6.12641e-322 milliseconds +# time to simulate: 6.95312e-310 milliseconds # GRADE: PASSING **************** ../../emulator/riscv_tests/rv32ui-p-lhu.hex **************** @@ -149,7 +149,7 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.03207 -# time to simulate: 6.12641e-322 milliseconds +# time to simulate: 6.95312e-310 milliseconds # GRADE: PASSING **************** ../../emulator/riscv_tests/rv32ui-p-lui.hex **************** @@ -158,7 +158,7 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.15068 -# time to simulate: 6.12641e-322 milliseconds +# time to simulate: 6.95312e-310 milliseconds # GRADE: PASSING **************** ../../emulator/riscv_tests/rv32ui-p-lw.hex **************** @@ -167,7 +167,7 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.03179 -# time to simulate: 6.12641e-322 milliseconds +# time to simulate: 6.95312e-310 milliseconds # GRADE: PASSING **************** ../../emulator/riscv_tests/rv32ui-p-or.hex **************** @@ -176,7 +176,7 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.01839 -# time to simulate: 6.12641e-322 milliseconds +# time to simulate: 6.95312e-310 milliseconds # GRADE: PASSING **************** ../../emulator/riscv_tests/rv32ui-p-ori.hex **************** @@ -185,7 +185,7 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.04348 -# time to simulate: 6.12641e-322 milliseconds +# time to simulate: 6.95312e-310 milliseconds # GRADE: PASSING **************** ../../emulator/riscv_tests/rv32ui-p-sb.hex **************** @@ -194,7 +194,7 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.01926 -# time to simulate: 6.12641e-322 milliseconds +# time to simulate: 6.95312e-310 milliseconds # GRADE: PASSING **************** ../../emulator/riscv_tests/rv32ui-p-sh.hex **************** @@ -203,7 +203,7 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.01824 -# time to simulate: 6.12641e-322 milliseconds +# time to simulate: 6.95312e-310 milliseconds # GRADE: PASSING **************** ../../emulator/riscv_tests/rv32ui-p-simple.hex **************** @@ -212,7 +212,7 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.2973 -# time to simulate: 6.12641e-322 milliseconds +# time to simulate: 6.95312e-310 milliseconds # GRADE: PASSING **************** ../../emulator/riscv_tests/rv32ui-p-sll.hex **************** @@ -221,7 +221,7 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.01738 -# time to simulate: 6.12641e-322 milliseconds +# time to simulate: 6.95312e-310 milliseconds # GRADE: PASSING **************** ../../emulator/riscv_tests/rv32ui-p-slli.hex **************** @@ -230,7 +230,7 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.03537 -# time to simulate: 6.12641e-322 milliseconds +# time to simulate: 6.95312e-310 milliseconds # GRADE: PASSING **************** ../../emulator/riscv_tests/rv32ui-p-slt.hex **************** @@ -239,7 +239,7 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.01861 -# time to simulate: 6.12641e-322 milliseconds +# time to simulate: 6.95312e-310 milliseconds # GRADE: PASSING **************** ../../emulator/riscv_tests/rv32ui-p-slti.hex **************** @@ -248,7 +248,7 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.03583 -# time to simulate: 6.12641e-322 milliseconds +# time to simulate: 6.95312e-310 milliseconds # GRADE: PASSING **************** ../../emulator/riscv_tests/rv32ui-p-sltiu.hex **************** @@ -257,7 +257,7 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.03583 -# time to simulate: 6.12641e-322 milliseconds +# time to simulate: 6.95312e-310 milliseconds # GRADE: PASSING **************** ../../emulator/riscv_tests/rv32ui-p-sltu.hex **************** @@ -266,7 +266,7 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.01861 -# time to simulate: 6.12641e-322 milliseconds +# time to simulate: 6.95312e-310 milliseconds # GRADE: PASSING **************** ../../emulator/riscv_tests/rv32ui-p-sra.hex **************** @@ -275,7 +275,7 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.01682 -# time to simulate: 6.12641e-322 milliseconds +# time to simulate: 6.95312e-310 milliseconds # GRADE: PASSING **************** ../../emulator/riscv_tests/rv32ui-p-srai.hex **************** @@ -284,7 +284,7 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.03374 -# time to simulate: 6.12641e-322 milliseconds +# time to simulate: 6.95312e-310 milliseconds # GRADE: PASSING **************** ../../emulator/riscv_tests/rv32ui-p-srl.hex **************** @@ -293,7 +293,7 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.01698 -# time to simulate: 6.12641e-322 milliseconds +# time to simulate: 6.95312e-310 milliseconds # GRADE: PASSING **************** ../../emulator/riscv_tests/rv32ui-p-srli.hex **************** @@ -302,7 +302,7 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.03438 -# time to simulate: 6.12641e-322 milliseconds +# time to simulate: 6.95312e-310 milliseconds # GRADE: PASSING **************** ../../emulator/riscv_tests/rv32ui-p-sub.hex **************** @@ -311,7 +311,7 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.01874 -# time to simulate: 6.12641e-322 milliseconds +# time to simulate: 6.95312e-310 milliseconds # GRADE: PASSING **************** ../../emulator/riscv_tests/rv32ui-p-sw.hex **************** @@ -320,7 +320,7 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.01797 -# time to simulate: 6.12641e-322 milliseconds +# time to simulate: 6.95312e-310 milliseconds # GRADE: PASSING **************** ../../emulator/riscv_tests/rv32ui-p-xor.hex **************** @@ -329,7 +329,7 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.01843 -# time to simulate: 6.12641e-322 milliseconds +# time to simulate: 6.95312e-310 milliseconds # GRADE: PASSING **************** ../../emulator/riscv_tests/rv32ui-p-xori.hex **************** @@ -338,7 +338,7 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.04314 -# time to simulate: 6.12641e-322 milliseconds +# time to simulate: 6.95312e-310 milliseconds # GRADE: PASSING **************** ../../emulator/riscv_tests/rv32um-p-div.hex **************** @@ -347,7 +347,7 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.09821 -# time to simulate: 6.12641e-322 milliseconds +# time to simulate: 6.95312e-310 milliseconds # GRADE: PASSING **************** ../../emulator/riscv_tests/rv32um-p-divu.hex **************** @@ -356,7 +356,7 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.09735 -# time to simulate: 6.12641e-322 milliseconds +# time to simulate: 6.95312e-310 milliseconds # GRADE: PASSING **************** ../../emulator/riscv_tests/rv32um-p-mul.hex **************** @@ -365,7 +365,7 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.01868 -# time to simulate: 6.12641e-322 milliseconds +# time to simulate: 6.95312e-310 milliseconds # GRADE: PASSING **************** ../../emulator/riscv_tests/rv32um-p-mulh.hex **************** @@ -374,7 +374,7 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.0188 -# time to simulate: 6.12641e-322 milliseconds +# time to simulate: 6.95312e-310 milliseconds # GRADE: PASSING **************** ../../emulator/riscv_tests/rv32um-p-mulhsu.hex **************** @@ -383,7 +383,7 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.0188 -# time to simulate: 6.12641e-322 milliseconds +# time to simulate: 6.95312e-310 milliseconds # GRADE: PASSING **************** ../../emulator/riscv_tests/rv32um-p-mulhu.hex **************** @@ -392,7 +392,7 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.0188 -# time to simulate: 6.12641e-322 milliseconds +# time to simulate: 6.95312e-310 milliseconds # GRADE: PASSING **************** ../../emulator/riscv_tests/rv32um-p-rem.hex **************** @@ -401,7 +401,7 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.09821 -# time to simulate: 6.12641e-322 milliseconds +# time to simulate: 6.95312e-310 milliseconds # GRADE: PASSING **************** ../../emulator/riscv_tests/rv32um-p-remu.hex **************** @@ -410,5 +410,5 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.09821 -# time to simulate: 6.12641e-322 milliseconds +# time to simulate: 6.95312e-310 milliseconds # GRADE: PASSING diff --git a/rtl/test_bench.h b/rtl/test_bench.h index b550542c..123d11a2 100644 --- a/rtl/test_bench.h +++ b/rtl/test_bench.h @@ -173,7 +173,7 @@ bool Vortex::dbus_driver() ////////////////////// DBUS ////////////////////// - if (vortex->out_cache_driver_in_mem_write != NO_MEM_WRITE) + if ((vortex->out_cache_driver_in_mem_write != NO_MEM_WRITE) && vortex->out_cache_driver_in_valid) { data_write = (uint32_t) vortex->out_cache_driver_in_data; addr = (uint32_t) vortex->out_cache_driver_in_address; @@ -195,7 +195,7 @@ bool Vortex::dbus_driver() } - if (vortex->out_cache_driver_in_mem_read != NO_MEM_READ) + if ((vortex->out_cache_driver_in_mem_read != NO_MEM_READ) && vortex->out_cache_driver_in_valid) { addr = (uint32_t) vortex->out_cache_driver_in_address;