fixed FPU handshake, optimized writeback's critical path
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2
hw/rtl/cache/VX_tag_data_access.v
vendored
2
hw/rtl/cache/VX_tag_data_access.v
vendored
@@ -26,11 +26,13 @@ module VX_tag_data_access #(
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input wire reset,
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`ifdef DBG_CORE_REQ_INFO
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`IGNORE_WARNINGS_BEGIN
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input wire[31:0] debug_pc_st1e,
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input wire debug_wb_st1e,
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input wire[`NR_BITS-1:0] debug_rd_st1e,
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input wire[`NW_BITS-1:0] debug_warp_num_st1e,
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input wire[`UP(CORE_TAG_ID_BITS)-1:0] debug_tagid_st1e,
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`IGNORE_WARNINGS_END
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`endif
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input wire stall,
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