From ce9ef840d6308e250e0ce394ce91b16bfa09ae35 Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Mon, 18 Jan 2021 04:22:40 -0800 Subject: [PATCH] minor updates --- benchmarks/riscv_tests/isa/Makefile | 2 +- hw/rtl/VX_config.vh | 12 +- hw/rtl/fp_cores/altera/arria10/acl_fdiv.sv | 2850 ++++++------------- hw/rtl/fp_cores/altera/arria10/acl_fmadd.sv | 2 +- hw/rtl/fp_cores/altera/arria10/acl_fsqrt.sv | 1593 ++++------- hw/rtl/fp_cores/altera/arria10/acl_gen.log | 246 +- hw/rtl/fp_cores/altera/arria10/acl_gen.sh | 2 +- hw/simulate/testbench.cpp | 296 +- runtime/tests/dev/Makefile | 2 +- runtime/tests/hello/Makefile | 2 +- runtime/tests/nlTest/Makefile | 2 +- runtime/tests/simple/Makefile | 2 +- 12 files changed, 1714 insertions(+), 3297 deletions(-) diff --git a/benchmarks/riscv_tests/isa/Makefile b/benchmarks/riscv_tests/isa/Makefile index 05837666..d5a064cf 100644 --- a/benchmarks/riscv_tests/isa/Makefile +++ b/benchmarks/riscv_tests/isa/Makefile @@ -3,4 +3,4 @@ VTESTS := $(wildcard *-v-*.hex) TESTS := $(filter-out $(VTESTS) rv32si-p-scall.hex rv32si-p-sbreak.hex rv32mi-p-breakpoint.hex rv32ud-p-fclass.hex rv32ua-p-amomax_w.hex rv32ua-p-amoxor_w.hex rv32ud-p-ldst.hex rv32ua-p-amoor_w.hex rv32mi-p-ma_addr.hex rv32ud-p-fdiv.hex rv32ud-p-fcmp.hex rv32mi-p-mcsr.hex rv32ua-p-amoswap_w.hex rv32mi-p-ma_fetch.hex rv32mi-p-csr.hex rv32ua-p-amoadd_w.hex rv32si-p-dirty.hex rv32ud-p-fcvt.hex rv32ui-p-fence_i.hex rv32si-p-csr.hex rv32mi-p-shamt.hex rv32ua-p-amomin_w.hex rv32ua-p-lrsc.hex rv32ud-p-fmadd.hex rv32ud-p-fadd.hex rv32si-p-wfi.hex rv32ua-p-amomaxu_w.hex rv32si-p-ma_fetch.hex rv32ud-p-fmin.hex rv32mi-p-illegal.hex rv32uc-p-rvc.hex rv32mi-p-sbreak.hex rv32ua-p-amominu_w.hex rv32ua-p-amoand_w.hex, $(TESTS)) run: - cd ../../../hw/simulate/obj_dir && ./VVortex -f $(foreach test,$(TESTS),../../../benchmarks/riscv_tests/isa/$(test)) + cd ../../../hw/simulate/obj_dir && ./VVortex -r $(foreach test,$(TESTS),../../../benchmarks/riscv_tests/isa/$(test)) diff --git a/hw/rtl/VX_config.vh b/hw/rtl/VX_config.vh index fb246b05..3005a78d 100644 --- a/hw/rtl/VX_config.vh +++ b/hw/rtl/VX_config.vh @@ -108,7 +108,7 @@ `ifdef ALTERA_S10 `define LATENCY_FDIV 34 `else -`define LATENCY_FDIV 20 +`define LATENCY_FDIV 15 `endif `endif @@ -116,18 +116,10 @@ `ifdef ALTERA_S10 `define LATENCY_FSQRT 25 `else -`define LATENCY_FSQRT 15 +`define LATENCY_FSQRT 10 `endif `endif -`ifndef LATENCY_ITOF -`define LATENCY_ITOF 7 -`endif - -`ifndef LATENCY_FTOI -`define LATENCY_FTOI 3 -`endif - `ifndef LATENCY_FDIVSQRT `define LATENCY_FDIVSQRT 32 `endif diff --git a/hw/rtl/fp_cores/altera/arria10/acl_fdiv.sv b/hw/rtl/fp_cores/altera/arria10/acl_fdiv.sv index a01558bd..b9b44742 100644 --- a/hw/rtl/fp_cores/altera/arria10/acl_fdiv.sv +++ b/hw/rtl/fp_cores/altera/arria10/acl_fdiv.sv @@ -16,7 +16,7 @@ // --------------------------------------------------------------------------- // SystemVerilog created from acl_fdiv -// SystemVerilog created on Sun Dec 27 09:47:21 2020 +// SystemVerilog created on Mon Jan 18 04:15:46 2021 (* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *) @@ -32,7 +32,6 @@ module acl_fdiv ( wire [0:0] GND_q; wire [0:0] VCC_q; wire [7:0] cstBiasM1_uid6_fpDivTest_q; - wire [7:0] cstBias_uid7_fpDivTest_q; wire [7:0] expX_uid9_fpDivTest_b; wire [22:0] fracX_uid10_fpDivTest_b; wire [0:0] signX_uid11_fpDivTest_b; @@ -46,18 +45,24 @@ module acl_fdiv ( reg [0:0] fracYZero_uid15_fpDivTest_q; wire [7:0] cstAllOWE_uid18_fpDivTest_q; wire [7:0] cstAllZWE_uid20_fpDivTest_q; - wire [0:0] excZ_x_uid23_fpDivTest_q; - wire [0:0] expXIsMax_uid24_fpDivTest_q; - wire [0:0] fracXIsZero_uid25_fpDivTest_q; + wire [0:0] excZ_x_uid23_fpDivTest_qi; + reg [0:0] excZ_x_uid23_fpDivTest_q; + wire [0:0] expXIsMax_uid24_fpDivTest_qi; + reg [0:0] expXIsMax_uid24_fpDivTest_q; + wire [0:0] fracXIsZero_uid25_fpDivTest_qi; + reg [0:0] fracXIsZero_uid25_fpDivTest_q; wire [0:0] fracXIsNotZero_uid26_fpDivTest_q; wire [0:0] excI_x_uid27_fpDivTest_q; wire [0:0] excN_x_uid28_fpDivTest_q; wire [0:0] invExpXIsMax_uid29_fpDivTest_q; wire [0:0] InvExpXIsZero_uid30_fpDivTest_q; wire [0:0] excR_x_uid31_fpDivTest_q; - wire [0:0] excZ_y_uid37_fpDivTest_q; - wire [0:0] expXIsMax_uid38_fpDivTest_q; - wire [0:0] fracXIsZero_uid39_fpDivTest_q; + wire [0:0] excZ_y_uid37_fpDivTest_qi; + reg [0:0] excZ_y_uid37_fpDivTest_q; + wire [0:0] expXIsMax_uid38_fpDivTest_qi; + reg [0:0] expXIsMax_uid38_fpDivTest_q; + wire [0:0] fracXIsZero_uid39_fpDivTest_qi; + reg [0:0] fracXIsZero_uid39_fpDivTest_q; wire [0:0] fracXIsNotZero_uid40_fpDivTest_q; wire [0:0] excI_y_uid41_fpDivTest_q; wire [0:0] excN_y_uid42_fpDivTest_q; @@ -76,849 +81,381 @@ module acl_fdiv ( wire [9:0] expR_uid48_fpDivTest_q; wire [8:0] yAddr_uid51_fpDivTest_b; wire [13:0] yPE_uid52_fpDivTest_b; - wire [31:0] invY_uid54_fpDivTest_in; - wire [26:0] invY_uid54_fpDivTest_b; - wire [32:0] invYO_uid55_fpDivTest_in; - wire [0:0] invYO_uid55_fpDivTest_b; - wire [23:0] lOAdded_uid57_fpDivTest_q; - wire [3:0] z4_uid60_fpDivTest_q; - wire [27:0] oFracXZ4_uid61_fpDivTest_q; - wire [0:0] divValPreNormYPow2Exc_uid63_fpDivTest_s; - reg [27:0] divValPreNormYPow2Exc_uid63_fpDivTest_q; - wire [0:0] norm_uid64_fpDivTest_b; - wire [26:0] divValPreNormHigh_uid65_fpDivTest_in; - wire [24:0] divValPreNormHigh_uid65_fpDivTest_b; - wire [25:0] divValPreNormLow_uid66_fpDivTest_in; - wire [24:0] divValPreNormLow_uid66_fpDivTest_b; - wire [0:0] normFracRnd_uid67_fpDivTest_s; - reg [24:0] normFracRnd_uid67_fpDivTest_q; - wire [34:0] expFracRnd_uid68_fpDivTest_q; - wire [23:0] zeroPaddingInAddition_uid74_fpDivTest_q; - wire [25:0] expFracPostRnd_uid75_fpDivTest_q; - wire [36:0] expFracPostRnd_uid76_fpDivTest_a; - wire [36:0] expFracPostRnd_uid76_fpDivTest_b; - logic [36:0] expFracPostRnd_uid76_fpDivTest_o; - wire [35:0] expFracPostRnd_uid76_fpDivTest_q; - wire [23:0] fracXExt_uid77_fpDivTest_q; - wire [24:0] fracPostRndF_uid79_fpDivTest_in; - wire [23:0] fracPostRndF_uid79_fpDivTest_b; - wire [0:0] fracPostRndF_uid80_fpDivTest_s; - reg [23:0] fracPostRndF_uid80_fpDivTest_q; - wire [32:0] expPostRndFR_uid81_fpDivTest_in; - wire [7:0] expPostRndFR_uid81_fpDivTest_b; - wire [0:0] expPostRndF_uid82_fpDivTest_s; - reg [7:0] expPostRndF_uid82_fpDivTest_q; - wire [24:0] lOAdded_uid84_fpDivTest_q; - wire [23:0] lOAdded_uid87_fpDivTest_q; - wire [0:0] qDivProdNorm_uid90_fpDivTest_b; - wire [47:0] qDivProdFracHigh_uid91_fpDivTest_in; - wire [23:0] qDivProdFracHigh_uid91_fpDivTest_b; - wire [46:0] qDivProdFracLow_uid92_fpDivTest_in; - wire [23:0] qDivProdFracLow_uid92_fpDivTest_b; - wire [0:0] qDivProdFrac_uid93_fpDivTest_s; - reg [23:0] qDivProdFrac_uid93_fpDivTest_q; - wire [8:0] qDivProdExp_opA_uid94_fpDivTest_a; - wire [8:0] qDivProdExp_opA_uid94_fpDivTest_b; - logic [8:0] qDivProdExp_opA_uid94_fpDivTest_o; - wire [8:0] qDivProdExp_opA_uid94_fpDivTest_q; - wire [8:0] qDivProdExp_opBs_uid95_fpDivTest_a; - wire [8:0] qDivProdExp_opBs_uid95_fpDivTest_b; - logic [8:0] qDivProdExp_opBs_uid95_fpDivTest_o; - wire [8:0] qDivProdExp_opBs_uid95_fpDivTest_q; - wire [11:0] qDivProdExp_uid96_fpDivTest_a; - wire [11:0] qDivProdExp_uid96_fpDivTest_b; - logic [11:0] qDivProdExp_uid96_fpDivTest_o; - wire [10:0] qDivProdExp_uid96_fpDivTest_q; - wire [22:0] qDivProdFracWF_uid97_fpDivTest_b; - wire [7:0] qDivProdLTX_opA_uid98_fpDivTest_in; - wire [7:0] qDivProdLTX_opA_uid98_fpDivTest_b; - wire [30:0] qDivProdLTX_opA_uid99_fpDivTest_q; - wire [30:0] qDivProdLTX_opB_uid100_fpDivTest_q; - wire [32:0] qDividerProdLTX_uid101_fpDivTest_a; - wire [32:0] qDividerProdLTX_uid101_fpDivTest_b; - logic [32:0] qDividerProdLTX_uid101_fpDivTest_o; - wire [0:0] qDividerProdLTX_uid101_fpDivTest_c; - wire [0:0] betweenFPwF_uid102_fpDivTest_in; - wire [0:0] betweenFPwF_uid102_fpDivTest_b; - wire [0:0] extraUlp_uid103_fpDivTest_q; - wire [22:0] fracPostRndFT_uid104_fpDivTest_b; - wire [23:0] fracRPreExcExt_uid105_fpDivTest_a; - wire [23:0] fracRPreExcExt_uid105_fpDivTest_b; - logic [23:0] fracRPreExcExt_uid105_fpDivTest_o; - wire [23:0] fracRPreExcExt_uid105_fpDivTest_q; - wire [22:0] fracPostRndFPostUlp_uid106_fpDivTest_in; - wire [22:0] fracPostRndFPostUlp_uid106_fpDivTest_b; - wire [0:0] fracRPreExc_uid107_fpDivTest_s; - reg [22:0] fracRPreExc_uid107_fpDivTest_q; - wire [0:0] ovfIncRnd_uid109_fpDivTest_b; - wire [8:0] expFracPostRndInc_uid110_fpDivTest_a; - wire [8:0] expFracPostRndInc_uid110_fpDivTest_b; - logic [8:0] expFracPostRndInc_uid110_fpDivTest_o; - wire [8:0] expFracPostRndInc_uid110_fpDivTest_q; - wire [7:0] expFracPostRndR_uid111_fpDivTest_in; - wire [7:0] expFracPostRndR_uid111_fpDivTest_b; - wire [0:0] expRPreExc_uid112_fpDivTest_s; - reg [7:0] expRPreExc_uid112_fpDivTest_q; - wire [10:0] expRExt_uid114_fpDivTest_b; - wire [12:0] expUdf_uid115_fpDivTest_a; - wire [12:0] expUdf_uid115_fpDivTest_b; - logic [12:0] expUdf_uid115_fpDivTest_o; - wire [0:0] expUdf_uid115_fpDivTest_n; - wire [12:0] expOvf_uid118_fpDivTest_a; - wire [12:0] expOvf_uid118_fpDivTest_b; - logic [12:0] expOvf_uid118_fpDivTest_o; - wire [0:0] expOvf_uid118_fpDivTest_n; - wire [0:0] zeroOverReg_uid119_fpDivTest_qi; - reg [0:0] zeroOverReg_uid119_fpDivTest_q; - wire [0:0] regOverRegWithUf_uid120_fpDivTest_qi; - reg [0:0] regOverRegWithUf_uid120_fpDivTest_q; - wire [0:0] xRegOrZero_uid121_fpDivTest_q; - wire [0:0] regOrZeroOverInf_uid122_fpDivTest_qi; - reg [0:0] regOrZeroOverInf_uid122_fpDivTest_q; - wire [0:0] excRZero_uid123_fpDivTest_q; - wire [0:0] excXRYZ_uid124_fpDivTest_q; - wire [0:0] excXRYROvf_uid125_fpDivTest_q; - wire [0:0] excXIYZ_uid126_fpDivTest_q; - wire [0:0] excXIYR_uid127_fpDivTest_q; - wire [0:0] excRInf_uid128_fpDivTest_qi; - reg [0:0] excRInf_uid128_fpDivTest_q; - wire [0:0] excXZYZ_uid129_fpDivTest_q; - wire [0:0] excXIYI_uid130_fpDivTest_q; - wire [0:0] excRNaN_uid131_fpDivTest_qi; - reg [0:0] excRNaN_uid131_fpDivTest_q; - wire [2:0] concExc_uid132_fpDivTest_q; - reg [1:0] excREnc_uid133_fpDivTest_q; - wire [22:0] oneFracRPostExc2_uid134_fpDivTest_q; - wire [1:0] fracRPostExc_uid137_fpDivTest_s; - reg [22:0] fracRPostExc_uid137_fpDivTest_q; - wire [1:0] expRPostExc_uid141_fpDivTest_s; - reg [7:0] expRPostExc_uid141_fpDivTest_q; - wire [0:0] invExcRNaN_uid142_fpDivTest_q; - wire [0:0] sRPostExc_uid143_fpDivTest_qi; - reg [0:0] sRPostExc_uid143_fpDivTest_q; - wire [31:0] divR_uid144_fpDivTest_q; - wire [12:0] yT1_uid158_invPolyEval_b; - wire [0:0] lowRangeB_uid160_invPolyEval_in; - wire [0:0] lowRangeB_uid160_invPolyEval_b; - wire [12:0] highBBits_uid161_invPolyEval_b; - wire [22:0] s1sumAHighB_uid162_invPolyEval_a; - wire [22:0] s1sumAHighB_uid162_invPolyEval_b; - logic [22:0] s1sumAHighB_uid162_invPolyEval_o; - wire [22:0] s1sumAHighB_uid162_invPolyEval_q; - wire [23:0] s1_uid163_invPolyEval_q; - wire [1:0] lowRangeB_uid166_invPolyEval_in; - wire [1:0] lowRangeB_uid166_invPolyEval_b; - wire [22:0] highBBits_uid167_invPolyEval_b; - wire [32:0] s2sumAHighB_uid168_invPolyEval_a; - wire [32:0] s2sumAHighB_uid168_invPolyEval_b; - logic [32:0] s2sumAHighB_uid168_invPolyEval_o; - wire [32:0] s2sumAHighB_uid168_invPolyEval_q; - wire [34:0] s2_uid169_invPolyEval_q; - wire [27:0] osig_uid172_divValPreNorm_uid59_fpDivTest_b; - wire [13:0] osig_uid175_pT1_uid159_invPolyEval_b; - wire [24:0] osig_uid178_pT2_uid165_invPolyEval_b; - wire memoryC0_uid146_invTables_lutmem_reset0; - wire [31:0] memoryC0_uid146_invTables_lutmem_ia; - wire [8:0] memoryC0_uid146_invTables_lutmem_aa; - wire [8:0] memoryC0_uid146_invTables_lutmem_ab; - wire [31:0] memoryC0_uid146_invTables_lutmem_ir; - wire [31:0] memoryC0_uid146_invTables_lutmem_r; - wire memoryC1_uid149_invTables_lutmem_reset0; - wire [21:0] memoryC1_uid149_invTables_lutmem_ia; - wire [8:0] memoryC1_uid149_invTables_lutmem_aa; - wire [8:0] memoryC1_uid149_invTables_lutmem_ab; - wire [21:0] memoryC1_uid149_invTables_lutmem_ir; - wire [21:0] memoryC1_uid149_invTables_lutmem_r; - wire memoryC2_uid152_invTables_lutmem_reset0; - wire [12:0] memoryC2_uid152_invTables_lutmem_ia; - wire [8:0] memoryC2_uid152_invTables_lutmem_aa; - wire [8:0] memoryC2_uid152_invTables_lutmem_ab; - wire [12:0] memoryC2_uid152_invTables_lutmem_ir; - wire [12:0] memoryC2_uid152_invTables_lutmem_r; - wire qDivProd_uid89_fpDivTest_cma_reset; - (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [24:0] qDivProd_uid89_fpDivTest_cma_a0 [0:0]; - (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [24:0] qDivProd_uid89_fpDivTest_cma_a1 [0:0]; - (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [23:0] qDivProd_uid89_fpDivTest_cma_c0 [0:0]; - (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [23:0] qDivProd_uid89_fpDivTest_cma_c1 [0:0]; - wire [48:0] qDivProd_uid89_fpDivTest_cma_p [0:0]; - wire [48:0] qDivProd_uid89_fpDivTest_cma_u [0:0]; - wire [48:0] qDivProd_uid89_fpDivTest_cma_w [0:0]; - wire [48:0] qDivProd_uid89_fpDivTest_cma_x [0:0]; - wire [48:0] qDivProd_uid89_fpDivTest_cma_y [0:0]; - reg [48:0] qDivProd_uid89_fpDivTest_cma_s [0:0]; - wire [48:0] qDivProd_uid89_fpDivTest_cma_qq; - wire [48:0] qDivProd_uid89_fpDivTest_cma_q; - wire qDivProd_uid89_fpDivTest_cma_ena0; - wire qDivProd_uid89_fpDivTest_cma_ena1; - wire qDivProd_uid89_fpDivTest_cma_ena2; - wire prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_reset; - (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [26:0] prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_a0 [0:0]; - (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [26:0] prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_a1 [0:0]; - (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [23:0] prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_c0 [0:0]; - (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [23:0] prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_c1 [0:0]; - wire [50:0] prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_p [0:0]; - wire [50:0] prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_u [0:0]; - wire [50:0] prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_w [0:0]; - wire [50:0] prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_x [0:0]; - wire [50:0] prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_y [0:0]; - reg [50:0] prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_s [0:0]; - wire [50:0] prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_qq; - wire [50:0] prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_q; - wire prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_ena0; - wire prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_ena1; - wire prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_ena2; - wire prodXY_uid174_pT1_uid159_invPolyEval_cma_reset; - (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [12:0] prodXY_uid174_pT1_uid159_invPolyEval_cma_a0 [0:0]; - (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [12:0] prodXY_uid174_pT1_uid159_invPolyEval_cma_a1 [0:0]; - (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg signed [12:0] prodXY_uid174_pT1_uid159_invPolyEval_cma_c0 [0:0]; - (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg signed [12:0] prodXY_uid174_pT1_uid159_invPolyEval_cma_c1 [0:0]; - wire signed [13:0] prodXY_uid174_pT1_uid159_invPolyEval_cma_l [0:0]; - wire signed [26:0] prodXY_uid174_pT1_uid159_invPolyEval_cma_p [0:0]; - wire signed [26:0] prodXY_uid174_pT1_uid159_invPolyEval_cma_u [0:0]; - wire signed [26:0] prodXY_uid174_pT1_uid159_invPolyEval_cma_w [0:0]; - wire signed [26:0] prodXY_uid174_pT1_uid159_invPolyEval_cma_x [0:0]; - wire signed [26:0] prodXY_uid174_pT1_uid159_invPolyEval_cma_y [0:0]; - reg signed [26:0] prodXY_uid174_pT1_uid159_invPolyEval_cma_s [0:0]; - wire [25:0] prodXY_uid174_pT1_uid159_invPolyEval_cma_qq; - wire [25:0] prodXY_uid174_pT1_uid159_invPolyEval_cma_q; - wire prodXY_uid174_pT1_uid159_invPolyEval_cma_ena0; - wire prodXY_uid174_pT1_uid159_invPolyEval_cma_ena1; - wire prodXY_uid174_pT1_uid159_invPolyEval_cma_ena2; - wire prodXY_uid177_pT2_uid165_invPolyEval_cma_reset; - (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [13:0] prodXY_uid177_pT2_uid165_invPolyEval_cma_a0 [0:0]; - (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [13:0] prodXY_uid177_pT2_uid165_invPolyEval_cma_a1 [0:0]; - (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg signed [23:0] prodXY_uid177_pT2_uid165_invPolyEval_cma_c0 [0:0]; - (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg signed [23:0] prodXY_uid177_pT2_uid165_invPolyEval_cma_c1 [0:0]; - wire signed [14:0] prodXY_uid177_pT2_uid165_invPolyEval_cma_l [0:0]; - wire signed [38:0] prodXY_uid177_pT2_uid165_invPolyEval_cma_p [0:0]; - wire signed [38:0] prodXY_uid177_pT2_uid165_invPolyEval_cma_u [0:0]; - wire signed [38:0] prodXY_uid177_pT2_uid165_invPolyEval_cma_w [0:0]; - wire signed [38:0] prodXY_uid177_pT2_uid165_invPolyEval_cma_x [0:0]; - wire signed [38:0] prodXY_uid177_pT2_uid165_invPolyEval_cma_y [0:0]; - reg signed [38:0] prodXY_uid177_pT2_uid165_invPolyEval_cma_s [0:0]; - wire [37:0] prodXY_uid177_pT2_uid165_invPolyEval_cma_qq; - wire [37:0] prodXY_uid177_pT2_uid165_invPolyEval_cma_q; - wire prodXY_uid177_pT2_uid165_invPolyEval_cma_ena0; - wire prodXY_uid177_pT2_uid165_invPolyEval_cma_ena1; - wire prodXY_uid177_pT2_uid165_invPolyEval_cma_ena2; - reg [0:0] redist0_lowRangeB_uid160_invPolyEval_b_1_q; - reg [0:0] redist1_sRPostExc_uid143_fpDivTest_q_5_q; - reg [1:0] redist2_excREnc_uid133_fpDivTest_q_5_q; - reg [0:0] redist3_ovfIncRnd_uid109_fpDivTest_b_1_q; - reg [0:0] redist4_extraUlp_uid103_fpDivTest_q_1_q; - reg [22:0] redist5_qDivProdFracWF_uid97_fpDivTest_b_1_q; - reg [8:0] redist6_qDivProdExp_opA_uid94_fpDivTest_q_4_q; - reg [23:0] redist9_lOAdded_uid57_fpDivTest_q_3_q; - reg [0:0] redist10_invYO_uid55_fpDivTest_b_5_q; - reg [26:0] redist11_invY_uid54_fpDivTest_b_1_q; - reg [13:0] redist12_yPE_uid52_fpDivTest_b_2_q; - reg [8:0] redist14_yAddr_uid51_fpDivTest_b_3_q; - reg [8:0] redist15_yAddr_uid51_fpDivTest_b_7_q; - reg [0:0] redist16_signR_uid46_fpDivTest_q_15_q; - reg [22:0] redist18_fracY_uid13_fpDivTest_b_14_q; - reg [7:0] redist20_expY_uid12_fpDivTest_b_14_q; - reg [22:0] redist22_fracX_uid10_fpDivTest_b_14_q; - reg [22:0] redist23_fracX_uid10_fpDivTest_b_18_q; - reg [7:0] redist25_expX_uid9_fpDivTest_b_14_q; - reg [7:0] redist26_expX_uid9_fpDivTest_b_18_q; - reg [7:0] redist7_expPostRndFR_uid81_fpDivTest_b_6_outputreg_q; - wire redist7_expPostRndFR_uid81_fpDivTest_b_6_mem_reset0; - wire [7:0] redist7_expPostRndFR_uid81_fpDivTest_b_6_mem_ia; - wire [1:0] redist7_expPostRndFR_uid81_fpDivTest_b_6_mem_aa; - wire [1:0] redist7_expPostRndFR_uid81_fpDivTest_b_6_mem_ab; - wire [7:0] redist7_expPostRndFR_uid81_fpDivTest_b_6_mem_iq; - wire [7:0] redist7_expPostRndFR_uid81_fpDivTest_b_6_mem_q; - wire [1:0] redist7_expPostRndFR_uid81_fpDivTest_b_6_rdcnt_q; - (* preserve *) reg [1:0] redist7_expPostRndFR_uid81_fpDivTest_b_6_rdcnt_i; - wire [0:0] redist7_expPostRndFR_uid81_fpDivTest_b_6_rdmux_s; - reg [1:0] redist7_expPostRndFR_uid81_fpDivTest_b_6_rdmux_q; - reg [1:0] redist7_expPostRndFR_uid81_fpDivTest_b_6_wraddr_q; - wire [2:0] redist7_expPostRndFR_uid81_fpDivTest_b_6_mem_last_q; - wire [2:0] redist7_expPostRndFR_uid81_fpDivTest_b_6_cmp_b; - wire [0:0] redist7_expPostRndFR_uid81_fpDivTest_b_6_cmp_q; - reg [0:0] redist7_expPostRndFR_uid81_fpDivTest_b_6_cmpReg_q; - wire [0:0] redist7_expPostRndFR_uid81_fpDivTest_b_6_notEnable_q; - wire [0:0] redist7_expPostRndFR_uid81_fpDivTest_b_6_nor_q; - (* preserve_syn_only *) reg [0:0] redist7_expPostRndFR_uid81_fpDivTest_b_6_sticky_ena_q; - wire [0:0] redist7_expPostRndFR_uid81_fpDivTest_b_6_enaAnd_q; - reg [23:0] redist8_fracPostRndF_uid80_fpDivTest_q_5_outputreg_q; - wire redist8_fracPostRndF_uid80_fpDivTest_q_5_mem_reset0; - wire [23:0] redist8_fracPostRndF_uid80_fpDivTest_q_5_mem_ia; - wire [1:0] redist8_fracPostRndF_uid80_fpDivTest_q_5_mem_aa; - wire [1:0] redist8_fracPostRndF_uid80_fpDivTest_q_5_mem_ab; - wire [23:0] redist8_fracPostRndF_uid80_fpDivTest_q_5_mem_iq; - wire [23:0] redist8_fracPostRndF_uid80_fpDivTest_q_5_mem_q; - wire [1:0] redist8_fracPostRndF_uid80_fpDivTest_q_5_rdcnt_q; - (* preserve *) reg [1:0] redist8_fracPostRndF_uid80_fpDivTest_q_5_rdcnt_i; - (* preserve *) reg redist8_fracPostRndF_uid80_fpDivTest_q_5_rdcnt_eq; - wire [0:0] redist8_fracPostRndF_uid80_fpDivTest_q_5_rdmux_s; - reg [1:0] redist8_fracPostRndF_uid80_fpDivTest_q_5_rdmux_q; - reg [1:0] redist8_fracPostRndF_uid80_fpDivTest_q_5_wraddr_q; - wire [1:0] redist8_fracPostRndF_uid80_fpDivTest_q_5_mem_last_q; - wire [0:0] redist8_fracPostRndF_uid80_fpDivTest_q_5_cmp_q; - reg [0:0] redist8_fracPostRndF_uid80_fpDivTest_q_5_cmpReg_q; - wire [0:0] redist8_fracPostRndF_uid80_fpDivTest_q_5_notEnable_q; - wire [0:0] redist8_fracPostRndF_uid80_fpDivTest_q_5_nor_q; - (* preserve_syn_only *) reg [0:0] redist8_fracPostRndF_uid80_fpDivTest_q_5_sticky_ena_q; - wire [0:0] redist8_fracPostRndF_uid80_fpDivTest_q_5_enaAnd_q; - wire redist13_yPE_uid52_fpDivTest_b_6_mem_reset0; - wire [13:0] redist13_yPE_uid52_fpDivTest_b_6_mem_ia; - wire [1:0] redist13_yPE_uid52_fpDivTest_b_6_mem_aa; - wire [1:0] redist13_yPE_uid52_fpDivTest_b_6_mem_ab; - wire [13:0] redist13_yPE_uid52_fpDivTest_b_6_mem_iq; - wire [13:0] redist13_yPE_uid52_fpDivTest_b_6_mem_q; - wire [1:0] redist13_yPE_uid52_fpDivTest_b_6_rdcnt_q; - (* preserve *) reg [1:0] redist13_yPE_uid52_fpDivTest_b_6_rdcnt_i; - (* preserve *) reg redist13_yPE_uid52_fpDivTest_b_6_rdcnt_eq; - wire [0:0] redist13_yPE_uid52_fpDivTest_b_6_rdmux_s; - reg [1:0] redist13_yPE_uid52_fpDivTest_b_6_rdmux_q; - reg [1:0] redist13_yPE_uid52_fpDivTest_b_6_wraddr_q; - wire [1:0] redist13_yPE_uid52_fpDivTest_b_6_mem_last_q; - wire [0:0] redist13_yPE_uid52_fpDivTest_b_6_cmp_q; - reg [0:0] redist13_yPE_uid52_fpDivTest_b_6_cmpReg_q; - wire [0:0] redist13_yPE_uid52_fpDivTest_b_6_notEnable_q; - wire [0:0] redist13_yPE_uid52_fpDivTest_b_6_nor_q; - (* preserve_syn_only *) reg [0:0] redist13_yPE_uid52_fpDivTest_b_6_sticky_ena_q; - wire [0:0] redist13_yPE_uid52_fpDivTest_b_6_enaAnd_q; - reg [22:0] redist17_fracY_uid13_fpDivTest_b_12_outputreg_q; - wire redist17_fracY_uid13_fpDivTest_b_12_mem_reset0; - wire [22:0] redist17_fracY_uid13_fpDivTest_b_12_mem_ia; - wire [3:0] redist17_fracY_uid13_fpDivTest_b_12_mem_aa; - wire [3:0] redist17_fracY_uid13_fpDivTest_b_12_mem_ab; - wire [22:0] redist17_fracY_uid13_fpDivTest_b_12_mem_iq; - wire [22:0] redist17_fracY_uid13_fpDivTest_b_12_mem_q; - wire [3:0] redist17_fracY_uid13_fpDivTest_b_12_rdcnt_q; - (* preserve *) reg [3:0] redist17_fracY_uid13_fpDivTest_b_12_rdcnt_i; - (* preserve *) reg redist17_fracY_uid13_fpDivTest_b_12_rdcnt_eq; - wire [0:0] redist17_fracY_uid13_fpDivTest_b_12_rdmux_s; - reg [3:0] redist17_fracY_uid13_fpDivTest_b_12_rdmux_q; - reg [3:0] redist17_fracY_uid13_fpDivTest_b_12_wraddr_q; - wire [4:0] redist17_fracY_uid13_fpDivTest_b_12_mem_last_q; - wire [4:0] redist17_fracY_uid13_fpDivTest_b_12_cmp_b; - wire [0:0] redist17_fracY_uid13_fpDivTest_b_12_cmp_q; - reg [0:0] redist17_fracY_uid13_fpDivTest_b_12_cmpReg_q; - wire [0:0] redist17_fracY_uid13_fpDivTest_b_12_notEnable_q; - wire [0:0] redist17_fracY_uid13_fpDivTest_b_12_nor_q; - (* preserve_syn_only *) reg [0:0] redist17_fracY_uid13_fpDivTest_b_12_sticky_ena_q; - wire [0:0] redist17_fracY_uid13_fpDivTest_b_12_enaAnd_q; - reg [7:0] redist19_expY_uid12_fpDivTest_b_12_outputreg_q; - wire redist19_expY_uid12_fpDivTest_b_12_mem_reset0; - wire [7:0] redist19_expY_uid12_fpDivTest_b_12_mem_ia; - wire [3:0] redist19_expY_uid12_fpDivTest_b_12_mem_aa; - wire [3:0] redist19_expY_uid12_fpDivTest_b_12_mem_ab; - wire [7:0] redist19_expY_uid12_fpDivTest_b_12_mem_iq; - wire [7:0] redist19_expY_uid12_fpDivTest_b_12_mem_q; - wire [3:0] redist19_expY_uid12_fpDivTest_b_12_rdcnt_q; - (* preserve *) reg [3:0] redist19_expY_uid12_fpDivTest_b_12_rdcnt_i; - (* preserve *) reg redist19_expY_uid12_fpDivTest_b_12_rdcnt_eq; - wire [0:0] redist19_expY_uid12_fpDivTest_b_12_rdmux_s; - reg [3:0] redist19_expY_uid12_fpDivTest_b_12_rdmux_q; - reg [3:0] redist19_expY_uid12_fpDivTest_b_12_wraddr_q; - wire [4:0] redist19_expY_uid12_fpDivTest_b_12_mem_last_q; - wire [4:0] redist19_expY_uid12_fpDivTest_b_12_cmp_b; - wire [0:0] redist19_expY_uid12_fpDivTest_b_12_cmp_q; - reg [0:0] redist19_expY_uid12_fpDivTest_b_12_cmpReg_q; - wire [0:0] redist19_expY_uid12_fpDivTest_b_12_notEnable_q; - wire [0:0] redist19_expY_uid12_fpDivTest_b_12_nor_q; - (* preserve_syn_only *) reg [0:0] redist19_expY_uid12_fpDivTest_b_12_sticky_ena_q; - wire [0:0] redist19_expY_uid12_fpDivTest_b_12_enaAnd_q; - reg [22:0] redist21_fracX_uid10_fpDivTest_b_10_outputreg_q; - wire redist21_fracX_uid10_fpDivTest_b_10_mem_reset0; - wire [22:0] redist21_fracX_uid10_fpDivTest_b_10_mem_ia; - wire [2:0] redist21_fracX_uid10_fpDivTest_b_10_mem_aa; - wire [2:0] redist21_fracX_uid10_fpDivTest_b_10_mem_ab; - wire [22:0] redist21_fracX_uid10_fpDivTest_b_10_mem_iq; - wire [22:0] redist21_fracX_uid10_fpDivTest_b_10_mem_q; - wire [2:0] redist21_fracX_uid10_fpDivTest_b_10_rdcnt_q; - (* preserve *) reg [2:0] redist21_fracX_uid10_fpDivTest_b_10_rdcnt_i; - wire [0:0] redist21_fracX_uid10_fpDivTest_b_10_rdmux_s; - reg [2:0] redist21_fracX_uid10_fpDivTest_b_10_rdmux_q; - reg [2:0] redist21_fracX_uid10_fpDivTest_b_10_wraddr_q; - wire [3:0] redist21_fracX_uid10_fpDivTest_b_10_mem_last_q; - wire [3:0] redist21_fracX_uid10_fpDivTest_b_10_cmp_b; - wire [0:0] redist21_fracX_uid10_fpDivTest_b_10_cmp_q; - reg [0:0] redist21_fracX_uid10_fpDivTest_b_10_cmpReg_q; - wire [0:0] redist21_fracX_uid10_fpDivTest_b_10_notEnable_q; - wire [0:0] redist21_fracX_uid10_fpDivTest_b_10_nor_q; - (* preserve_syn_only *) reg [0:0] redist21_fracX_uid10_fpDivTest_b_10_sticky_ena_q; - wire [0:0] redist21_fracX_uid10_fpDivTest_b_10_enaAnd_q; - reg [22:0] redist22_fracX_uid10_fpDivTest_b_14_inputreg_q; - reg [22:0] redist23_fracX_uid10_fpDivTest_b_18_inputreg_q; - reg [7:0] redist24_expX_uid9_fpDivTest_b_12_outputreg_q; - wire redist24_expX_uid9_fpDivTest_b_12_mem_reset0; - wire [7:0] redist24_expX_uid9_fpDivTest_b_12_mem_ia; - wire [3:0] redist24_expX_uid9_fpDivTest_b_12_mem_aa; - wire [3:0] redist24_expX_uid9_fpDivTest_b_12_mem_ab; - wire [7:0] redist24_expX_uid9_fpDivTest_b_12_mem_iq; - wire [7:0] redist24_expX_uid9_fpDivTest_b_12_mem_q; - wire [3:0] redist24_expX_uid9_fpDivTest_b_12_rdcnt_q; - (* preserve *) reg [3:0] redist24_expX_uid9_fpDivTest_b_12_rdcnt_i; - (* preserve *) reg redist24_expX_uid9_fpDivTest_b_12_rdcnt_eq; - wire [0:0] redist24_expX_uid9_fpDivTest_b_12_rdmux_s; - reg [3:0] redist24_expX_uid9_fpDivTest_b_12_rdmux_q; - reg [3:0] redist24_expX_uid9_fpDivTest_b_12_wraddr_q; - wire [4:0] redist24_expX_uid9_fpDivTest_b_12_mem_last_q; - wire [4:0] redist24_expX_uid9_fpDivTest_b_12_cmp_b; - wire [0:0] redist24_expX_uid9_fpDivTest_b_12_cmp_q; - reg [0:0] redist24_expX_uid9_fpDivTest_b_12_cmpReg_q; - wire [0:0] redist24_expX_uid9_fpDivTest_b_12_notEnable_q; - wire [0:0] redist24_expX_uid9_fpDivTest_b_12_nor_q; - (* preserve_syn_only *) reg [0:0] redist24_expX_uid9_fpDivTest_b_12_sticky_ena_q; - wire [0:0] redist24_expX_uid9_fpDivTest_b_12_enaAnd_q; + wire [0:0] fracYPostZ_uid56_fpDivTest_qi; + reg [0:0] fracYPostZ_uid56_fpDivTest_q; + wire [23:0] lOAdded_uid58_fpDivTest_q; + wire [1:0] oFracXSE_bottomExtension_uid61_fpDivTest_q; + wire [25:0] oFracXSE_mergedSignalTM_uid63_fpDivTest_q; + wire [0:0] divValPreNormTrunc_uid66_fpDivTest_s; + reg [25:0] divValPreNormTrunc_uid66_fpDivTest_q; + wire [0:0] norm_uid67_fpDivTest_b; + wire [24:0] divValPreNormHigh_uid68_fpDivTest_in; + wire [23:0] divValPreNormHigh_uid68_fpDivTest_b; + wire [23:0] divValPreNormLow_uid69_fpDivTest_in; + wire [23:0] divValPreNormLow_uid69_fpDivTest_b; + wire [0:0] normFracRnd_uid70_fpDivTest_s; + reg [23:0] normFracRnd_uid70_fpDivTest_q; + wire [33:0] expFracRnd_uid71_fpDivTest_q; + wire [24:0] rndOp_uid75_fpDivTest_q; + wire [35:0] expFracPostRnd_uid76_fpDivTest_a; + wire [35:0] expFracPostRnd_uid76_fpDivTest_b; + logic [35:0] expFracPostRnd_uid76_fpDivTest_o; + wire [34:0] expFracPostRnd_uid76_fpDivTest_q; + wire [23:0] fracRPreExc_uid78_fpDivTest_in; + wire [22:0] fracRPreExc_uid78_fpDivTest_b; + wire [31:0] excRPreExc_uid79_fpDivTest_in; + wire [7:0] excRPreExc_uid79_fpDivTest_b; + wire [10:0] expRExt_uid80_fpDivTest_b; + wire [12:0] expUdf_uid81_fpDivTest_a; + wire [12:0] expUdf_uid81_fpDivTest_b; + logic [12:0] expUdf_uid81_fpDivTest_o; + wire [0:0] expUdf_uid81_fpDivTest_n; + wire [12:0] expOvf_uid84_fpDivTest_a; + wire [12:0] expOvf_uid84_fpDivTest_b; + logic [12:0] expOvf_uid84_fpDivTest_o; + wire [0:0] expOvf_uid84_fpDivTest_n; + wire [0:0] zeroOverReg_uid85_fpDivTest_q; + wire [0:0] regOverRegWithUf_uid86_fpDivTest_q; + wire [0:0] xRegOrZero_uid87_fpDivTest_q; + wire [0:0] regOrZeroOverInf_uid88_fpDivTest_q; + wire [0:0] excRZero_uid89_fpDivTest_q; + wire [0:0] excXRYZ_uid90_fpDivTest_q; + wire [0:0] excXRYROvf_uid91_fpDivTest_q; + wire [0:0] excXIYZ_uid92_fpDivTest_q; + wire [0:0] excXIYR_uid93_fpDivTest_q; + wire [0:0] excRInf_uid94_fpDivTest_q; + wire [0:0] excXZYZ_uid95_fpDivTest_q; + wire [0:0] excXIYI_uid96_fpDivTest_q; + wire [0:0] excRNaN_uid97_fpDivTest_q; + wire [2:0] concExc_uid98_fpDivTest_q; + reg [1:0] excREnc_uid99_fpDivTest_q; + wire [22:0] oneFracRPostExc2_uid100_fpDivTest_q; + wire [1:0] fracRPostExc_uid103_fpDivTest_s; + reg [22:0] fracRPostExc_uid103_fpDivTest_q; + wire [1:0] expRPostExc_uid107_fpDivTest_s; + reg [7:0] expRPostExc_uid107_fpDivTest_q; + wire [0:0] invExcRNaN_uid108_fpDivTest_q; + wire [0:0] sRPostExc_uid109_fpDivTest_qi; + reg [0:0] sRPostExc_uid109_fpDivTest_q; + wire [31:0] divR_uid110_fpDivTest_q; + wire [11:0] yT1_uid124_invPolyEval_b; + wire [0:0] lowRangeB_uid126_invPolyEval_in; + wire [0:0] lowRangeB_uid126_invPolyEval_b; + wire [11:0] highBBits_uid127_invPolyEval_b; + wire [21:0] s1sumAHighB_uid128_invPolyEval_a; + wire [21:0] s1sumAHighB_uid128_invPolyEval_b; + logic [21:0] s1sumAHighB_uid128_invPolyEval_o; + wire [21:0] s1sumAHighB_uid128_invPolyEval_q; + wire [22:0] s1_uid129_invPolyEval_q; + wire [1:0] lowRangeB_uid132_invPolyEval_in; + wire [1:0] lowRangeB_uid132_invPolyEval_b; + wire [21:0] highBBits_uid133_invPolyEval_b; + wire [31:0] s2sumAHighB_uid134_invPolyEval_a; + wire [31:0] s2sumAHighB_uid134_invPolyEval_b; + logic [31:0] s2sumAHighB_uid134_invPolyEval_o; + wire [31:0] s2sumAHighB_uid134_invPolyEval_q; + wire [33:0] s2_uid135_invPolyEval_q; + wire [25:0] osig_uid138_prodDivPreNormProd_uid60_fpDivTest_b; + wire [12:0] osig_uid141_pT1_uid125_invPolyEval_b; + wire [23:0] osig_uid144_pT2_uid131_invPolyEval_b; + wire memoryC0_uid112_invTables_lutmem_reset0; + wire [30:0] memoryC0_uid112_invTables_lutmem_ia; + wire [8:0] memoryC0_uid112_invTables_lutmem_aa; + wire [8:0] memoryC0_uid112_invTables_lutmem_ab; + wire [30:0] memoryC0_uid112_invTables_lutmem_ir; + wire [30:0] memoryC0_uid112_invTables_lutmem_r; + wire memoryC1_uid115_invTables_lutmem_reset0; + wire [20:0] memoryC1_uid115_invTables_lutmem_ia; + wire [8:0] memoryC1_uid115_invTables_lutmem_aa; + wire [8:0] memoryC1_uid115_invTables_lutmem_ab; + wire [20:0] memoryC1_uid115_invTables_lutmem_ir; + wire [20:0] memoryC1_uid115_invTables_lutmem_r; + wire memoryC2_uid118_invTables_lutmem_reset0; + wire [11:0] memoryC2_uid118_invTables_lutmem_ia; + wire [8:0] memoryC2_uid118_invTables_lutmem_aa; + wire [8:0] memoryC2_uid118_invTables_lutmem_ab; + wire [11:0] memoryC2_uid118_invTables_lutmem_ir; + wire [11:0] memoryC2_uid118_invTables_lutmem_r; + wire prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_reset; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [25:0] prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_a0 [0:0]; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [25:0] prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_a1 [0:0]; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [23:0] prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_c0 [0:0]; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [23:0] prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_c1 [0:0]; + wire [49:0] prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_p [0:0]; + wire [49:0] prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_u [0:0]; + wire [49:0] prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_w [0:0]; + wire [49:0] prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_x [0:0]; + wire [49:0] prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_y [0:0]; + reg [49:0] prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_s [0:0]; + wire [49:0] prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_qq; + wire [49:0] prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_q; + wire prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_ena0; + wire prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_ena1; + wire prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_ena2; + wire prodXY_uid140_pT1_uid125_invPolyEval_cma_reset; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [11:0] prodXY_uid140_pT1_uid125_invPolyEval_cma_a0 [0:0]; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [11:0] prodXY_uid140_pT1_uid125_invPolyEval_cma_a1 [0:0]; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg signed [11:0] prodXY_uid140_pT1_uid125_invPolyEval_cma_c0 [0:0]; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg signed [11:0] prodXY_uid140_pT1_uid125_invPolyEval_cma_c1 [0:0]; + wire signed [12:0] prodXY_uid140_pT1_uid125_invPolyEval_cma_l [0:0]; + wire signed [24:0] prodXY_uid140_pT1_uid125_invPolyEval_cma_p [0:0]; + wire signed [24:0] prodXY_uid140_pT1_uid125_invPolyEval_cma_u [0:0]; + wire signed [24:0] prodXY_uid140_pT1_uid125_invPolyEval_cma_w [0:0]; + wire signed [24:0] prodXY_uid140_pT1_uid125_invPolyEval_cma_x [0:0]; + wire signed [24:0] prodXY_uid140_pT1_uid125_invPolyEval_cma_y [0:0]; + reg signed [24:0] prodXY_uid140_pT1_uid125_invPolyEval_cma_s [0:0]; + wire [23:0] prodXY_uid140_pT1_uid125_invPolyEval_cma_qq; + wire [23:0] prodXY_uid140_pT1_uid125_invPolyEval_cma_q; + wire prodXY_uid140_pT1_uid125_invPolyEval_cma_ena0; + wire prodXY_uid140_pT1_uid125_invPolyEval_cma_ena1; + wire prodXY_uid140_pT1_uid125_invPolyEval_cma_ena2; + wire prodXY_uid143_pT2_uid131_invPolyEval_cma_reset; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [13:0] prodXY_uid143_pT2_uid131_invPolyEval_cma_a0 [0:0]; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [13:0] prodXY_uid143_pT2_uid131_invPolyEval_cma_a1 [0:0]; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg signed [22:0] prodXY_uid143_pT2_uid131_invPolyEval_cma_c0 [0:0]; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg signed [22:0] prodXY_uid143_pT2_uid131_invPolyEval_cma_c1 [0:0]; + wire signed [14:0] prodXY_uid143_pT2_uid131_invPolyEval_cma_l [0:0]; + wire signed [37:0] prodXY_uid143_pT2_uid131_invPolyEval_cma_p [0:0]; + wire signed [37:0] prodXY_uid143_pT2_uid131_invPolyEval_cma_u [0:0]; + wire signed [37:0] prodXY_uid143_pT2_uid131_invPolyEval_cma_w [0:0]; + wire signed [37:0] prodXY_uid143_pT2_uid131_invPolyEval_cma_x [0:0]; + wire signed [37:0] prodXY_uid143_pT2_uid131_invPolyEval_cma_y [0:0]; + reg signed [37:0] prodXY_uid143_pT2_uid131_invPolyEval_cma_s [0:0]; + wire [36:0] prodXY_uid143_pT2_uid131_invPolyEval_cma_qq; + wire [36:0] prodXY_uid143_pT2_uid131_invPolyEval_cma_q; + wire prodXY_uid143_pT2_uid131_invPolyEval_cma_ena0; + wire prodXY_uid143_pT2_uid131_invPolyEval_cma_ena1; + wire prodXY_uid143_pT2_uid131_invPolyEval_cma_ena2; + wire [31:0] invY_uid54_fpDivTest_merged_bit_select_in; + wire [25:0] invY_uid54_fpDivTest_merged_bit_select_b; + wire [0:0] invY_uid54_fpDivTest_merged_bit_select_c; + reg [25:0] redist0_invY_uid54_fpDivTest_merged_bit_select_b_1_q; + reg [0:0] redist1_lowRangeB_uid126_invPolyEval_b_1_q; + reg [7:0] redist2_excRPreExc_uid79_fpDivTest_b_1_q; + reg [22:0] redist3_fracRPreExc_uid78_fpDivTest_b_1_q; + reg [23:0] redist4_lOAdded_uid58_fpDivTest_q_3_q; + reg [0:0] redist5_fracYPostZ_uid56_fpDivTest_q_4_q; + reg [13:0] redist6_yPE_uid52_fpDivTest_b_2_q; + reg [8:0] redist8_yAddr_uid51_fpDivTest_b_3_q; + reg [8:0] redist9_yAddr_uid51_fpDivTest_b_7_q; + reg [0:0] redist11_signR_uid46_fpDivTest_q_14_q; + reg [0:0] redist12_fracXIsZero_uid39_fpDivTest_q_14_q; + reg [0:0] redist13_expXIsMax_uid38_fpDivTest_q_14_q; + reg [0:0] redist14_excZ_y_uid37_fpDivTest_q_14_q; + reg [0:0] redist15_fracXIsZero_uid25_fpDivTest_q_4_q; + reg [0:0] redist16_expXIsMax_uid24_fpDivTest_q_14_q; + reg [0:0] redist17_excZ_x_uid23_fpDivTest_q_14_q; + reg [0:0] redist18_fracYZero_uid15_fpDivTest_q_9_q; + wire redist7_yPE_uid52_fpDivTest_b_6_mem_reset0; + wire [13:0] redist7_yPE_uid52_fpDivTest_b_6_mem_ia; + wire [1:0] redist7_yPE_uid52_fpDivTest_b_6_mem_aa; + wire [1:0] redist7_yPE_uid52_fpDivTest_b_6_mem_ab; + wire [13:0] redist7_yPE_uid52_fpDivTest_b_6_mem_iq; + wire [13:0] redist7_yPE_uid52_fpDivTest_b_6_mem_q; + wire [1:0] redist7_yPE_uid52_fpDivTest_b_6_rdcnt_q; + (* preserve *) reg [1:0] redist7_yPE_uid52_fpDivTest_b_6_rdcnt_i; + (* preserve *) reg redist7_yPE_uid52_fpDivTest_b_6_rdcnt_eq; + wire [0:0] redist7_yPE_uid52_fpDivTest_b_6_rdmux_s; + reg [1:0] redist7_yPE_uid52_fpDivTest_b_6_rdmux_q; + reg [1:0] redist7_yPE_uid52_fpDivTest_b_6_wraddr_q; + wire [1:0] redist7_yPE_uid52_fpDivTest_b_6_mem_last_q; + wire [0:0] redist7_yPE_uid52_fpDivTest_b_6_cmp_q; + reg [0:0] redist7_yPE_uid52_fpDivTest_b_6_cmpReg_q; + wire [0:0] redist7_yPE_uid52_fpDivTest_b_6_notEnable_q; + wire [0:0] redist7_yPE_uid52_fpDivTest_b_6_nor_q; + (* preserve_syn_only *) reg [0:0] redist7_yPE_uid52_fpDivTest_b_6_sticky_ena_q; + wire [0:0] redist7_yPE_uid52_fpDivTest_b_6_enaAnd_q; + reg [8:0] redist10_expXmY_uid47_fpDivTest_q_13_outputreg_q; + wire redist10_expXmY_uid47_fpDivTest_q_13_mem_reset0; + wire [8:0] redist10_expXmY_uid47_fpDivTest_q_13_mem_ia; + wire [3:0] redist10_expXmY_uid47_fpDivTest_q_13_mem_aa; + wire [3:0] redist10_expXmY_uid47_fpDivTest_q_13_mem_ab; + wire [8:0] redist10_expXmY_uid47_fpDivTest_q_13_mem_iq; + wire [8:0] redist10_expXmY_uid47_fpDivTest_q_13_mem_q; + wire [3:0] redist10_expXmY_uid47_fpDivTest_q_13_rdcnt_q; + (* preserve *) reg [3:0] redist10_expXmY_uid47_fpDivTest_q_13_rdcnt_i; + (* preserve *) reg redist10_expXmY_uid47_fpDivTest_q_13_rdcnt_eq; + wire [0:0] redist10_expXmY_uid47_fpDivTest_q_13_rdmux_s; + reg [3:0] redist10_expXmY_uid47_fpDivTest_q_13_rdmux_q; + reg [3:0] redist10_expXmY_uid47_fpDivTest_q_13_wraddr_q; + wire [4:0] redist10_expXmY_uid47_fpDivTest_q_13_mem_last_q; + wire [4:0] redist10_expXmY_uid47_fpDivTest_q_13_cmp_b; + wire [0:0] redist10_expXmY_uid47_fpDivTest_q_13_cmp_q; + reg [0:0] redist10_expXmY_uid47_fpDivTest_q_13_cmpReg_q; + wire [0:0] redist10_expXmY_uid47_fpDivTest_q_13_notEnable_q; + wire [0:0] redist10_expXmY_uid47_fpDivTest_q_13_nor_q; + (* preserve_syn_only *) reg [0:0] redist10_expXmY_uid47_fpDivTest_q_13_sticky_ena_q; + wire [0:0] redist10_expXmY_uid47_fpDivTest_q_13_enaAnd_q; + wire redist19_fracX_uid10_fpDivTest_b_10_mem_reset0; + wire [22:0] redist19_fracX_uid10_fpDivTest_b_10_mem_ia; + wire [3:0] redist19_fracX_uid10_fpDivTest_b_10_mem_aa; + wire [3:0] redist19_fracX_uid10_fpDivTest_b_10_mem_ab; + wire [22:0] redist19_fracX_uid10_fpDivTest_b_10_mem_iq; + wire [22:0] redist19_fracX_uid10_fpDivTest_b_10_mem_q; + wire [3:0] redist19_fracX_uid10_fpDivTest_b_10_rdcnt_q; + (* preserve *) reg [3:0] redist19_fracX_uid10_fpDivTest_b_10_rdcnt_i; + (* preserve *) reg redist19_fracX_uid10_fpDivTest_b_10_rdcnt_eq; + wire [0:0] redist19_fracX_uid10_fpDivTest_b_10_rdmux_s; + reg [3:0] redist19_fracX_uid10_fpDivTest_b_10_rdmux_q; + reg [3:0] redist19_fracX_uid10_fpDivTest_b_10_wraddr_q; + wire [3:0] redist19_fracX_uid10_fpDivTest_b_10_mem_last_q; + wire [0:0] redist19_fracX_uid10_fpDivTest_b_10_cmp_q; + reg [0:0] redist19_fracX_uid10_fpDivTest_b_10_cmpReg_q; + wire [0:0] redist19_fracX_uid10_fpDivTest_b_10_notEnable_q; + wire [0:0] redist19_fracX_uid10_fpDivTest_b_10_nor_q; + (* preserve_syn_only *) reg [0:0] redist19_fracX_uid10_fpDivTest_b_10_sticky_ena_q; + wire [0:0] redist19_fracX_uid10_fpDivTest_b_10_enaAnd_q; - // redist17_fracY_uid13_fpDivTest_b_12_notEnable(LOGICAL,256) - assign redist17_fracY_uid13_fpDivTest_b_12_notEnable_q = ~ (en); + // fracY_uid13_fpDivTest(BITSELECT,12)@0 + assign fracY_uid13_fpDivTest_b = b[22:0]; - // redist17_fracY_uid13_fpDivTest_b_12_nor(LOGICAL,257) - assign redist17_fracY_uid13_fpDivTest_b_12_nor_q = ~ (redist17_fracY_uid13_fpDivTest_b_12_notEnable_q | redist17_fracY_uid13_fpDivTest_b_12_sticky_ena_q); + // paddingY_uid15_fpDivTest(CONSTANT,14) + assign paddingY_uid15_fpDivTest_q = 23'b00000000000000000000000; - // redist17_fracY_uid13_fpDivTest_b_12_mem_last(CONSTANT,253) - assign redist17_fracY_uid13_fpDivTest_b_12_mem_last_q = 5'b01000; + // fracXIsZero_uid39_fpDivTest(LOGICAL,38)@0 + 1 + assign fracXIsZero_uid39_fpDivTest_qi = paddingY_uid15_fpDivTest_q == fracY_uid13_fpDivTest_b ? 1'b1 : 1'b0; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + fracXIsZero_uid39_fpDivTest_delay ( .xin(fracXIsZero_uid39_fpDivTest_qi), .xout(fracXIsZero_uid39_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - // redist17_fracY_uid13_fpDivTest_b_12_cmp(LOGICAL,254) - assign redist17_fracY_uid13_fpDivTest_b_12_cmp_b = {1'b0, redist17_fracY_uid13_fpDivTest_b_12_rdmux_q}; - assign redist17_fracY_uid13_fpDivTest_b_12_cmp_q = redist17_fracY_uid13_fpDivTest_b_12_mem_last_q == redist17_fracY_uid13_fpDivTest_b_12_cmp_b ? 1'b1 : 1'b0; + // redist12_fracXIsZero_uid39_fpDivTest_q_14(DELAY,164) + dspba_delay_ver #( .width(1), .depth(13), .reset_kind("ASYNC") ) + redist12_fracXIsZero_uid39_fpDivTest_q_14 ( .xin(fracXIsZero_uid39_fpDivTest_q), .xout(redist12_fracXIsZero_uid39_fpDivTest_q_14_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - // redist17_fracY_uid13_fpDivTest_b_12_cmpReg(REG,255) + // cstAllOWE_uid18_fpDivTest(CONSTANT,17) + assign cstAllOWE_uid18_fpDivTest_q = 8'b11111111; + + // expY_uid12_fpDivTest(BITSELECT,11)@0 + assign expY_uid12_fpDivTest_b = b[30:23]; + + // expXIsMax_uid38_fpDivTest(LOGICAL,37)@0 + 1 + assign expXIsMax_uid38_fpDivTest_qi = expY_uid12_fpDivTest_b == cstAllOWE_uid18_fpDivTest_q ? 1'b1 : 1'b0; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + expXIsMax_uid38_fpDivTest_delay ( .xin(expXIsMax_uid38_fpDivTest_qi), .xout(expXIsMax_uid38_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist13_expXIsMax_uid38_fpDivTest_q_14(DELAY,165) + dspba_delay_ver #( .width(1), .depth(13), .reset_kind("ASYNC") ) + redist13_expXIsMax_uid38_fpDivTest_q_14 ( .xin(expXIsMax_uid38_fpDivTest_q), .xout(redist13_expXIsMax_uid38_fpDivTest_q_14_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // excI_y_uid41_fpDivTest(LOGICAL,40)@14 + assign excI_y_uid41_fpDivTest_q = redist13_expXIsMax_uid38_fpDivTest_q_14_q & redist12_fracXIsZero_uid39_fpDivTest_q_14_q; + + // redist19_fracX_uid10_fpDivTest_b_10_notEnable(LOGICAL,202) + assign redist19_fracX_uid10_fpDivTest_b_10_notEnable_q = ~ (en); + + // redist19_fracX_uid10_fpDivTest_b_10_nor(LOGICAL,203) + assign redist19_fracX_uid10_fpDivTest_b_10_nor_q = ~ (redist19_fracX_uid10_fpDivTest_b_10_notEnable_q | redist19_fracX_uid10_fpDivTest_b_10_sticky_ena_q); + + // redist19_fracX_uid10_fpDivTest_b_10_mem_last(CONSTANT,199) + assign redist19_fracX_uid10_fpDivTest_b_10_mem_last_q = 4'b0111; + + // redist19_fracX_uid10_fpDivTest_b_10_cmp(LOGICAL,200) + assign redist19_fracX_uid10_fpDivTest_b_10_cmp_q = redist19_fracX_uid10_fpDivTest_b_10_mem_last_q == redist19_fracX_uid10_fpDivTest_b_10_rdmux_q ? 1'b1 : 1'b0; + + // redist19_fracX_uid10_fpDivTest_b_10_cmpReg(REG,201) always @ (posedge clk or posedge areset) begin if (areset) begin - redist17_fracY_uid13_fpDivTest_b_12_cmpReg_q <= 1'b0; + redist19_fracX_uid10_fpDivTest_b_10_cmpReg_q <= 1'b0; end else if (en == 1'b1) begin - redist17_fracY_uid13_fpDivTest_b_12_cmpReg_q <= redist17_fracY_uid13_fpDivTest_b_12_cmp_q; + redist19_fracX_uid10_fpDivTest_b_10_cmpReg_q <= redist19_fracX_uid10_fpDivTest_b_10_cmp_q; end end - // redist17_fracY_uid13_fpDivTest_b_12_sticky_ena(REG,258) + // redist19_fracX_uid10_fpDivTest_b_10_sticky_ena(REG,204) always @ (posedge clk or posedge areset) begin if (areset) begin - redist17_fracY_uid13_fpDivTest_b_12_sticky_ena_q <= 1'b0; + redist19_fracX_uid10_fpDivTest_b_10_sticky_ena_q <= 1'b0; end - else if (redist17_fracY_uid13_fpDivTest_b_12_nor_q == 1'b1) + else if (redist19_fracX_uid10_fpDivTest_b_10_nor_q == 1'b1) begin - redist17_fracY_uid13_fpDivTest_b_12_sticky_ena_q <= redist17_fracY_uid13_fpDivTest_b_12_cmpReg_q; + redist19_fracX_uid10_fpDivTest_b_10_sticky_ena_q <= redist19_fracX_uid10_fpDivTest_b_10_cmpReg_q; end end - // redist17_fracY_uid13_fpDivTest_b_12_enaAnd(LOGICAL,259) - assign redist17_fracY_uid13_fpDivTest_b_12_enaAnd_q = redist17_fracY_uid13_fpDivTest_b_12_sticky_ena_q & en; + // redist19_fracX_uid10_fpDivTest_b_10_enaAnd(LOGICAL,205) + assign redist19_fracX_uid10_fpDivTest_b_10_enaAnd_q = redist19_fracX_uid10_fpDivTest_b_10_sticky_ena_q & en; - // redist17_fracY_uid13_fpDivTest_b_12_rdcnt(COUNTER,250) - // low=0, high=9, step=1, init=0 + // redist19_fracX_uid10_fpDivTest_b_10_rdcnt(COUNTER,196) + // low=0, high=8, step=1, init=0 always @ (posedge clk or posedge areset) begin if (areset) begin - redist17_fracY_uid13_fpDivTest_b_12_rdcnt_i <= 4'd0; - redist17_fracY_uid13_fpDivTest_b_12_rdcnt_eq <= 1'b0; + redist19_fracX_uid10_fpDivTest_b_10_rdcnt_i <= 4'd0; + redist19_fracX_uid10_fpDivTest_b_10_rdcnt_eq <= 1'b0; end else if (en == 1'b1) begin - if (redist17_fracY_uid13_fpDivTest_b_12_rdcnt_i == 4'd8) + if (redist19_fracX_uid10_fpDivTest_b_10_rdcnt_i == 4'd7) begin - redist17_fracY_uid13_fpDivTest_b_12_rdcnt_eq <= 1'b1; + redist19_fracX_uid10_fpDivTest_b_10_rdcnt_eq <= 1'b1; end else begin - redist17_fracY_uid13_fpDivTest_b_12_rdcnt_eq <= 1'b0; + redist19_fracX_uid10_fpDivTest_b_10_rdcnt_eq <= 1'b0; end - if (redist17_fracY_uid13_fpDivTest_b_12_rdcnt_eq == 1'b1) + if (redist19_fracX_uid10_fpDivTest_b_10_rdcnt_eq == 1'b1) begin - redist17_fracY_uid13_fpDivTest_b_12_rdcnt_i <= $unsigned(redist17_fracY_uid13_fpDivTest_b_12_rdcnt_i) + $unsigned(4'd7); + redist19_fracX_uid10_fpDivTest_b_10_rdcnt_i <= $unsigned(redist19_fracX_uid10_fpDivTest_b_10_rdcnt_i) + $unsigned(4'd8); end else begin - redist17_fracY_uid13_fpDivTest_b_12_rdcnt_i <= $unsigned(redist17_fracY_uid13_fpDivTest_b_12_rdcnt_i) + $unsigned(4'd1); + redist19_fracX_uid10_fpDivTest_b_10_rdcnt_i <= $unsigned(redist19_fracX_uid10_fpDivTest_b_10_rdcnt_i) + $unsigned(4'd1); end end end - assign redist17_fracY_uid13_fpDivTest_b_12_rdcnt_q = redist17_fracY_uid13_fpDivTest_b_12_rdcnt_i[3:0]; + assign redist19_fracX_uid10_fpDivTest_b_10_rdcnt_q = redist19_fracX_uid10_fpDivTest_b_10_rdcnt_i[3:0]; - // redist17_fracY_uid13_fpDivTest_b_12_rdmux(MUX,251) - assign redist17_fracY_uid13_fpDivTest_b_12_rdmux_s = en; - always @(redist17_fracY_uid13_fpDivTest_b_12_rdmux_s or redist17_fracY_uid13_fpDivTest_b_12_wraddr_q or redist17_fracY_uid13_fpDivTest_b_12_rdcnt_q) + // redist19_fracX_uid10_fpDivTest_b_10_rdmux(MUX,197) + assign redist19_fracX_uid10_fpDivTest_b_10_rdmux_s = en; + always @(redist19_fracX_uid10_fpDivTest_b_10_rdmux_s or redist19_fracX_uid10_fpDivTest_b_10_wraddr_q or redist19_fracX_uid10_fpDivTest_b_10_rdcnt_q) begin - unique case (redist17_fracY_uid13_fpDivTest_b_12_rdmux_s) - 1'b0 : redist17_fracY_uid13_fpDivTest_b_12_rdmux_q = redist17_fracY_uid13_fpDivTest_b_12_wraddr_q; - 1'b1 : redist17_fracY_uid13_fpDivTest_b_12_rdmux_q = redist17_fracY_uid13_fpDivTest_b_12_rdcnt_q; - default : redist17_fracY_uid13_fpDivTest_b_12_rdmux_q = 4'b0; + unique case (redist19_fracX_uid10_fpDivTest_b_10_rdmux_s) + 1'b0 : redist19_fracX_uid10_fpDivTest_b_10_rdmux_q = redist19_fracX_uid10_fpDivTest_b_10_wraddr_q; + 1'b1 : redist19_fracX_uid10_fpDivTest_b_10_rdmux_q = redist19_fracX_uid10_fpDivTest_b_10_rdcnt_q; + default : redist19_fracX_uid10_fpDivTest_b_10_rdmux_q = 4'b0; endcase end // VCC(CONSTANT,1) assign VCC_q = 1'b1; - // fracY_uid13_fpDivTest(BITSELECT,12)@0 - assign fracY_uid13_fpDivTest_b = b[22:0]; - - // redist17_fracY_uid13_fpDivTest_b_12_wraddr(REG,252) - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - redist17_fracY_uid13_fpDivTest_b_12_wraddr_q <= 4'b1001; - end - else - begin - redist17_fracY_uid13_fpDivTest_b_12_wraddr_q <= redist17_fracY_uid13_fpDivTest_b_12_rdmux_q; - end - end - - // redist17_fracY_uid13_fpDivTest_b_12_mem(DUALMEM,249) - assign redist17_fracY_uid13_fpDivTest_b_12_mem_ia = fracY_uid13_fpDivTest_b; - assign redist17_fracY_uid13_fpDivTest_b_12_mem_aa = redist17_fracY_uid13_fpDivTest_b_12_wraddr_q; - assign redist17_fracY_uid13_fpDivTest_b_12_mem_ab = redist17_fracY_uid13_fpDivTest_b_12_rdmux_q; - assign redist17_fracY_uid13_fpDivTest_b_12_mem_reset0 = areset; - altera_syncram #( - .ram_block_type("MLAB"), - .operation_mode("DUAL_PORT"), - .width_a(23), - .widthad_a(4), - .numwords_a(10), - .width_b(23), - .widthad_b(4), - .numwords_b(10), - .lpm_type("altera_syncram"), - .width_byteena_a(1), - .address_reg_b("CLOCK0"), - .indata_reg_b("CLOCK0"), - .rdcontrol_reg_b("CLOCK0"), - .byteena_reg_b("CLOCK0"), - .outdata_reg_b("CLOCK1"), - .outdata_aclr_b("CLEAR1"), - .clock_enable_input_a("NORMAL"), - .clock_enable_input_b("NORMAL"), - .clock_enable_output_b("NORMAL"), - .read_during_write_mode_mixed_ports("DONT_CARE"), - .power_up_uninitialized("TRUE"), - .intended_device_family("Arria 10") - ) redist17_fracY_uid13_fpDivTest_b_12_mem_dmem ( - .clocken1(redist17_fracY_uid13_fpDivTest_b_12_enaAnd_q[0]), - .clocken0(VCC_q[0]), - .clock0(clk), - .aclr1(redist17_fracY_uid13_fpDivTest_b_12_mem_reset0), - .clock1(clk), - .address_a(redist17_fracY_uid13_fpDivTest_b_12_mem_aa), - .data_a(redist17_fracY_uid13_fpDivTest_b_12_mem_ia), - .wren_a(en[0]), - .address_b(redist17_fracY_uid13_fpDivTest_b_12_mem_ab), - .q_b(redist17_fracY_uid13_fpDivTest_b_12_mem_iq), - .wren_b(), - .rden_a(), - .rden_b(), - .data_b(), - .clocken2(), - .clocken3(), - .aclr0(), - .addressstall_a(), - .addressstall_b(), - .byteena_a(), - .byteena_b(), - .eccencbypass(), - .eccencparity(), - .sclr(), - .address2_a(), - .address2_b(), - .q_a(), - .eccstatus() - ); - assign redist17_fracY_uid13_fpDivTest_b_12_mem_q = redist17_fracY_uid13_fpDivTest_b_12_mem_iq[22:0]; - - // redist17_fracY_uid13_fpDivTest_b_12_outputreg(DELAY,248) - dspba_delay_ver #( .width(23), .depth(1), .reset_kind("ASYNC") ) - redist17_fracY_uid13_fpDivTest_b_12_outputreg ( .xin(redist17_fracY_uid13_fpDivTest_b_12_mem_q), .xout(redist17_fracY_uid13_fpDivTest_b_12_outputreg_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // redist18_fracY_uid13_fpDivTest_b_14(DELAY,204) - dspba_delay_ver #( .width(23), .depth(2), .reset_kind("ASYNC") ) - redist18_fracY_uid13_fpDivTest_b_14 ( .xin(redist17_fracY_uid13_fpDivTest_b_12_outputreg_q), .xout(redist18_fracY_uid13_fpDivTest_b_14_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // paddingY_uid15_fpDivTest(CONSTANT,14) - assign paddingY_uid15_fpDivTest_q = 23'b00000000000000000000000; - - // fracXIsZero_uid39_fpDivTest(LOGICAL,38)@14 - assign fracXIsZero_uid39_fpDivTest_q = paddingY_uid15_fpDivTest_q == redist18_fracY_uid13_fpDivTest_b_14_q ? 1'b1 : 1'b0; - - // cstAllOWE_uid18_fpDivTest(CONSTANT,17) - assign cstAllOWE_uid18_fpDivTest_q = 8'b11111111; - - // redist19_expY_uid12_fpDivTest_b_12_notEnable(LOGICAL,268) - assign redist19_expY_uid12_fpDivTest_b_12_notEnable_q = ~ (en); - - // redist19_expY_uid12_fpDivTest_b_12_nor(LOGICAL,269) - assign redist19_expY_uid12_fpDivTest_b_12_nor_q = ~ (redist19_expY_uid12_fpDivTest_b_12_notEnable_q | redist19_expY_uid12_fpDivTest_b_12_sticky_ena_q); - - // redist19_expY_uid12_fpDivTest_b_12_mem_last(CONSTANT,265) - assign redist19_expY_uid12_fpDivTest_b_12_mem_last_q = 5'b01000; - - // redist19_expY_uid12_fpDivTest_b_12_cmp(LOGICAL,266) - assign redist19_expY_uid12_fpDivTest_b_12_cmp_b = {1'b0, redist19_expY_uid12_fpDivTest_b_12_rdmux_q}; - assign redist19_expY_uid12_fpDivTest_b_12_cmp_q = redist19_expY_uid12_fpDivTest_b_12_mem_last_q == redist19_expY_uid12_fpDivTest_b_12_cmp_b ? 1'b1 : 1'b0; - - // redist19_expY_uid12_fpDivTest_b_12_cmpReg(REG,267) - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - redist19_expY_uid12_fpDivTest_b_12_cmpReg_q <= 1'b0; - end - else if (en == 1'b1) - begin - redist19_expY_uid12_fpDivTest_b_12_cmpReg_q <= redist19_expY_uid12_fpDivTest_b_12_cmp_q; - end - end - - // redist19_expY_uid12_fpDivTest_b_12_sticky_ena(REG,270) - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - redist19_expY_uid12_fpDivTest_b_12_sticky_ena_q <= 1'b0; - end - else if (redist19_expY_uid12_fpDivTest_b_12_nor_q == 1'b1) - begin - redist19_expY_uid12_fpDivTest_b_12_sticky_ena_q <= redist19_expY_uid12_fpDivTest_b_12_cmpReg_q; - end - end - - // redist19_expY_uid12_fpDivTest_b_12_enaAnd(LOGICAL,271) - assign redist19_expY_uid12_fpDivTest_b_12_enaAnd_q = redist19_expY_uid12_fpDivTest_b_12_sticky_ena_q & en; - - // redist19_expY_uid12_fpDivTest_b_12_rdcnt(COUNTER,262) - // low=0, high=9, step=1, init=0 - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - redist19_expY_uid12_fpDivTest_b_12_rdcnt_i <= 4'd0; - redist19_expY_uid12_fpDivTest_b_12_rdcnt_eq <= 1'b0; - end - else if (en == 1'b1) - begin - if (redist19_expY_uid12_fpDivTest_b_12_rdcnt_i == 4'd8) - begin - redist19_expY_uid12_fpDivTest_b_12_rdcnt_eq <= 1'b1; - end - else - begin - redist19_expY_uid12_fpDivTest_b_12_rdcnt_eq <= 1'b0; - end - if (redist19_expY_uid12_fpDivTest_b_12_rdcnt_eq == 1'b1) - begin - redist19_expY_uid12_fpDivTest_b_12_rdcnt_i <= $unsigned(redist19_expY_uid12_fpDivTest_b_12_rdcnt_i) + $unsigned(4'd7); - end - else - begin - redist19_expY_uid12_fpDivTest_b_12_rdcnt_i <= $unsigned(redist19_expY_uid12_fpDivTest_b_12_rdcnt_i) + $unsigned(4'd1); - end - end - end - assign redist19_expY_uid12_fpDivTest_b_12_rdcnt_q = redist19_expY_uid12_fpDivTest_b_12_rdcnt_i[3:0]; - - // redist19_expY_uid12_fpDivTest_b_12_rdmux(MUX,263) - assign redist19_expY_uid12_fpDivTest_b_12_rdmux_s = en; - always @(redist19_expY_uid12_fpDivTest_b_12_rdmux_s or redist19_expY_uid12_fpDivTest_b_12_wraddr_q or redist19_expY_uid12_fpDivTest_b_12_rdcnt_q) - begin - unique case (redist19_expY_uid12_fpDivTest_b_12_rdmux_s) - 1'b0 : redist19_expY_uid12_fpDivTest_b_12_rdmux_q = redist19_expY_uid12_fpDivTest_b_12_wraddr_q; - 1'b1 : redist19_expY_uid12_fpDivTest_b_12_rdmux_q = redist19_expY_uid12_fpDivTest_b_12_rdcnt_q; - default : redist19_expY_uid12_fpDivTest_b_12_rdmux_q = 4'b0; - endcase - end - - // expY_uid12_fpDivTest(BITSELECT,11)@0 - assign expY_uid12_fpDivTest_b = b[30:23]; - - // redist19_expY_uid12_fpDivTest_b_12_wraddr(REG,264) - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - redist19_expY_uid12_fpDivTest_b_12_wraddr_q <= 4'b1001; - end - else - begin - redist19_expY_uid12_fpDivTest_b_12_wraddr_q <= redist19_expY_uid12_fpDivTest_b_12_rdmux_q; - end - end - - // redist19_expY_uid12_fpDivTest_b_12_mem(DUALMEM,261) - assign redist19_expY_uid12_fpDivTest_b_12_mem_ia = expY_uid12_fpDivTest_b; - assign redist19_expY_uid12_fpDivTest_b_12_mem_aa = redist19_expY_uid12_fpDivTest_b_12_wraddr_q; - assign redist19_expY_uid12_fpDivTest_b_12_mem_ab = redist19_expY_uid12_fpDivTest_b_12_rdmux_q; - assign redist19_expY_uid12_fpDivTest_b_12_mem_reset0 = areset; - altera_syncram #( - .ram_block_type("MLAB"), - .operation_mode("DUAL_PORT"), - .width_a(8), - .widthad_a(4), - .numwords_a(10), - .width_b(8), - .widthad_b(4), - .numwords_b(10), - .lpm_type("altera_syncram"), - .width_byteena_a(1), - .address_reg_b("CLOCK0"), - .indata_reg_b("CLOCK0"), - .rdcontrol_reg_b("CLOCK0"), - .byteena_reg_b("CLOCK0"), - .outdata_reg_b("CLOCK1"), - .outdata_aclr_b("CLEAR1"), - .clock_enable_input_a("NORMAL"), - .clock_enable_input_b("NORMAL"), - .clock_enable_output_b("NORMAL"), - .read_during_write_mode_mixed_ports("DONT_CARE"), - .power_up_uninitialized("TRUE"), - .intended_device_family("Arria 10") - ) redist19_expY_uid12_fpDivTest_b_12_mem_dmem ( - .clocken1(redist19_expY_uid12_fpDivTest_b_12_enaAnd_q[0]), - .clocken0(VCC_q[0]), - .clock0(clk), - .aclr1(redist19_expY_uid12_fpDivTest_b_12_mem_reset0), - .clock1(clk), - .address_a(redist19_expY_uid12_fpDivTest_b_12_mem_aa), - .data_a(redist19_expY_uid12_fpDivTest_b_12_mem_ia), - .wren_a(en[0]), - .address_b(redist19_expY_uid12_fpDivTest_b_12_mem_ab), - .q_b(redist19_expY_uid12_fpDivTest_b_12_mem_iq), - .wren_b(), - .rden_a(), - .rden_b(), - .data_b(), - .clocken2(), - .clocken3(), - .aclr0(), - .addressstall_a(), - .addressstall_b(), - .byteena_a(), - .byteena_b(), - .eccencbypass(), - .eccencparity(), - .sclr(), - .address2_a(), - .address2_b(), - .q_a(), - .eccstatus() - ); - assign redist19_expY_uid12_fpDivTest_b_12_mem_q = redist19_expY_uid12_fpDivTest_b_12_mem_iq[7:0]; - - // redist19_expY_uid12_fpDivTest_b_12_outputreg(DELAY,260) - dspba_delay_ver #( .width(8), .depth(1), .reset_kind("ASYNC") ) - redist19_expY_uid12_fpDivTest_b_12_outputreg ( .xin(redist19_expY_uid12_fpDivTest_b_12_mem_q), .xout(redist19_expY_uid12_fpDivTest_b_12_outputreg_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // redist20_expY_uid12_fpDivTest_b_14(DELAY,206) - dspba_delay_ver #( .width(8), .depth(2), .reset_kind("ASYNC") ) - redist20_expY_uid12_fpDivTest_b_14 ( .xin(redist19_expY_uid12_fpDivTest_b_12_outputreg_q), .xout(redist20_expY_uid12_fpDivTest_b_14_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // expXIsMax_uid38_fpDivTest(LOGICAL,37)@14 - assign expXIsMax_uid38_fpDivTest_q = redist20_expY_uid12_fpDivTest_b_14_q == cstAllOWE_uid18_fpDivTest_q ? 1'b1 : 1'b0; - - // excI_y_uid41_fpDivTest(LOGICAL,40)@14 - assign excI_y_uid41_fpDivTest_q = expXIsMax_uid38_fpDivTest_q & fracXIsZero_uid39_fpDivTest_q; - - // redist21_fracX_uid10_fpDivTest_b_10_notEnable(LOGICAL,280) - assign redist21_fracX_uid10_fpDivTest_b_10_notEnable_q = ~ (en); - - // redist21_fracX_uid10_fpDivTest_b_10_nor(LOGICAL,281) - assign redist21_fracX_uid10_fpDivTest_b_10_nor_q = ~ (redist21_fracX_uid10_fpDivTest_b_10_notEnable_q | redist21_fracX_uid10_fpDivTest_b_10_sticky_ena_q); - - // redist21_fracX_uid10_fpDivTest_b_10_mem_last(CONSTANT,277) - assign redist21_fracX_uid10_fpDivTest_b_10_mem_last_q = 4'b0110; - - // redist21_fracX_uid10_fpDivTest_b_10_cmp(LOGICAL,278) - assign redist21_fracX_uid10_fpDivTest_b_10_cmp_b = {1'b0, redist21_fracX_uid10_fpDivTest_b_10_rdmux_q}; - assign redist21_fracX_uid10_fpDivTest_b_10_cmp_q = redist21_fracX_uid10_fpDivTest_b_10_mem_last_q == redist21_fracX_uid10_fpDivTest_b_10_cmp_b ? 1'b1 : 1'b0; - - // redist21_fracX_uid10_fpDivTest_b_10_cmpReg(REG,279) - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - redist21_fracX_uid10_fpDivTest_b_10_cmpReg_q <= 1'b0; - end - else if (en == 1'b1) - begin - redist21_fracX_uid10_fpDivTest_b_10_cmpReg_q <= redist21_fracX_uid10_fpDivTest_b_10_cmp_q; - end - end - - // redist21_fracX_uid10_fpDivTest_b_10_sticky_ena(REG,282) - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - redist21_fracX_uid10_fpDivTest_b_10_sticky_ena_q <= 1'b0; - end - else if (redist21_fracX_uid10_fpDivTest_b_10_nor_q == 1'b1) - begin - redist21_fracX_uid10_fpDivTest_b_10_sticky_ena_q <= redist21_fracX_uid10_fpDivTest_b_10_cmpReg_q; - end - end - - // redist21_fracX_uid10_fpDivTest_b_10_enaAnd(LOGICAL,283) - assign redist21_fracX_uid10_fpDivTest_b_10_enaAnd_q = redist21_fracX_uid10_fpDivTest_b_10_sticky_ena_q & en; - - // redist21_fracX_uid10_fpDivTest_b_10_rdcnt(COUNTER,274) - // low=0, high=7, step=1, init=0 - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - redist21_fracX_uid10_fpDivTest_b_10_rdcnt_i <= 3'd0; - end - else if (en == 1'b1) - begin - redist21_fracX_uid10_fpDivTest_b_10_rdcnt_i <= $unsigned(redist21_fracX_uid10_fpDivTest_b_10_rdcnt_i) + $unsigned(3'd1); - end - end - assign redist21_fracX_uid10_fpDivTest_b_10_rdcnt_q = redist21_fracX_uid10_fpDivTest_b_10_rdcnt_i[2:0]; - - // redist21_fracX_uid10_fpDivTest_b_10_rdmux(MUX,275) - assign redist21_fracX_uid10_fpDivTest_b_10_rdmux_s = en; - always @(redist21_fracX_uid10_fpDivTest_b_10_rdmux_s or redist21_fracX_uid10_fpDivTest_b_10_wraddr_q or redist21_fracX_uid10_fpDivTest_b_10_rdcnt_q) - begin - unique case (redist21_fracX_uid10_fpDivTest_b_10_rdmux_s) - 1'b0 : redist21_fracX_uid10_fpDivTest_b_10_rdmux_q = redist21_fracX_uid10_fpDivTest_b_10_wraddr_q; - 1'b1 : redist21_fracX_uid10_fpDivTest_b_10_rdmux_q = redist21_fracX_uid10_fpDivTest_b_10_rdcnt_q; - default : redist21_fracX_uid10_fpDivTest_b_10_rdmux_q = 3'b0; - endcase - end - // fracX_uid10_fpDivTest(BITSELECT,9)@0 assign fracX_uid10_fpDivTest_b = a[22:0]; - // redist21_fracX_uid10_fpDivTest_b_10_wraddr(REG,276) + // redist19_fracX_uid10_fpDivTest_b_10_wraddr(REG,198) always @ (posedge clk or posedge areset) begin if (areset) begin - redist21_fracX_uid10_fpDivTest_b_10_wraddr_q <= 3'b111; + redist19_fracX_uid10_fpDivTest_b_10_wraddr_q <= 4'b1000; end else begin - redist21_fracX_uid10_fpDivTest_b_10_wraddr_q <= redist21_fracX_uid10_fpDivTest_b_10_rdmux_q; + redist19_fracX_uid10_fpDivTest_b_10_wraddr_q <= redist19_fracX_uid10_fpDivTest_b_10_rdmux_q; end end - // redist21_fracX_uid10_fpDivTest_b_10_mem(DUALMEM,273) - assign redist21_fracX_uid10_fpDivTest_b_10_mem_ia = fracX_uid10_fpDivTest_b; - assign redist21_fracX_uid10_fpDivTest_b_10_mem_aa = redist21_fracX_uid10_fpDivTest_b_10_wraddr_q; - assign redist21_fracX_uid10_fpDivTest_b_10_mem_ab = redist21_fracX_uid10_fpDivTest_b_10_rdmux_q; - assign redist21_fracX_uid10_fpDivTest_b_10_mem_reset0 = areset; + // redist19_fracX_uid10_fpDivTest_b_10_mem(DUALMEM,195) + assign redist19_fracX_uid10_fpDivTest_b_10_mem_ia = fracX_uid10_fpDivTest_b; + assign redist19_fracX_uid10_fpDivTest_b_10_mem_aa = redist19_fracX_uid10_fpDivTest_b_10_wraddr_q; + assign redist19_fracX_uid10_fpDivTest_b_10_mem_ab = redist19_fracX_uid10_fpDivTest_b_10_rdmux_q; + assign redist19_fracX_uid10_fpDivTest_b_10_mem_reset0 = areset; altera_syncram #( .ram_block_type("MLAB"), .operation_mode("DUAL_PORT"), .width_a(23), - .widthad_a(3), - .numwords_a(8), + .widthad_a(4), + .numwords_a(9), .width_b(23), - .widthad_b(3), - .numwords_b(8), + .widthad_b(4), + .numwords_b(9), .lpm_type("altera_syncram"), .width_byteena_a(1), .address_reg_b("CLOCK0"), @@ -933,17 +470,17 @@ module acl_fdiv ( .read_during_write_mode_mixed_ports("DONT_CARE"), .power_up_uninitialized("TRUE"), .intended_device_family("Arria 10") - ) redist21_fracX_uid10_fpDivTest_b_10_mem_dmem ( - .clocken1(redist21_fracX_uid10_fpDivTest_b_10_enaAnd_q[0]), + ) redist19_fracX_uid10_fpDivTest_b_10_mem_dmem ( + .clocken1(redist19_fracX_uid10_fpDivTest_b_10_enaAnd_q[0]), .clocken0(VCC_q[0]), .clock0(clk), - .aclr1(redist21_fracX_uid10_fpDivTest_b_10_mem_reset0), + .aclr1(redist19_fracX_uid10_fpDivTest_b_10_mem_reset0), .clock1(clk), - .address_a(redist21_fracX_uid10_fpDivTest_b_10_mem_aa), - .data_a(redist21_fracX_uid10_fpDivTest_b_10_mem_ia), + .address_a(redist19_fracX_uid10_fpDivTest_b_10_mem_aa), + .data_a(redist19_fracX_uid10_fpDivTest_b_10_mem_ia), .wren_a(en[0]), - .address_b(redist21_fracX_uid10_fpDivTest_b_10_mem_ab), - .q_b(redist21_fracX_uid10_fpDivTest_b_10_mem_iq), + .address_b(redist19_fracX_uid10_fpDivTest_b_10_mem_ab), + .q_b(redist19_fracX_uid10_fpDivTest_b_10_mem_iq), .wren_b(), .rden_a(), .rden_b(), @@ -963,231 +500,76 @@ module acl_fdiv ( .q_a(), .eccstatus() ); - assign redist21_fracX_uid10_fpDivTest_b_10_mem_q = redist21_fracX_uid10_fpDivTest_b_10_mem_iq[22:0]; + assign redist19_fracX_uid10_fpDivTest_b_10_mem_q = redist19_fracX_uid10_fpDivTest_b_10_mem_iq[22:0]; - // redist21_fracX_uid10_fpDivTest_b_10_outputreg(DELAY,272) - dspba_delay_ver #( .width(23), .depth(1), .reset_kind("ASYNC") ) - redist21_fracX_uid10_fpDivTest_b_10_outputreg ( .xin(redist21_fracX_uid10_fpDivTest_b_10_mem_q), .xout(redist21_fracX_uid10_fpDivTest_b_10_outputreg_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + // fracXIsZero_uid25_fpDivTest(LOGICAL,24)@10 + 1 + assign fracXIsZero_uid25_fpDivTest_qi = paddingY_uid15_fpDivTest_q == redist19_fracX_uid10_fpDivTest_b_10_mem_q ? 1'b1 : 1'b0; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + fracXIsZero_uid25_fpDivTest_delay ( .xin(fracXIsZero_uid25_fpDivTest_qi), .xout(fracXIsZero_uid25_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - // redist22_fracX_uid10_fpDivTest_b_14_inputreg(DELAY,284) - dspba_delay_ver #( .width(23), .depth(1), .reset_kind("ASYNC") ) - redist22_fracX_uid10_fpDivTest_b_14_inputreg ( .xin(redist21_fracX_uid10_fpDivTest_b_10_outputreg_q), .xout(redist22_fracX_uid10_fpDivTest_b_14_inputreg_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // redist22_fracX_uid10_fpDivTest_b_14(DELAY,208) - dspba_delay_ver #( .width(23), .depth(3), .reset_kind("ASYNC") ) - redist22_fracX_uid10_fpDivTest_b_14 ( .xin(redist22_fracX_uid10_fpDivTest_b_14_inputreg_q), .xout(redist22_fracX_uid10_fpDivTest_b_14_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // fracXIsZero_uid25_fpDivTest(LOGICAL,24)@14 - assign fracXIsZero_uid25_fpDivTest_q = paddingY_uid15_fpDivTest_q == redist22_fracX_uid10_fpDivTest_b_14_q ? 1'b1 : 1'b0; - - // redist24_expX_uid9_fpDivTest_b_12_notEnable(LOGICAL,294) - assign redist24_expX_uid9_fpDivTest_b_12_notEnable_q = ~ (en); - - // redist24_expX_uid9_fpDivTest_b_12_nor(LOGICAL,295) - assign redist24_expX_uid9_fpDivTest_b_12_nor_q = ~ (redist24_expX_uid9_fpDivTest_b_12_notEnable_q | redist24_expX_uid9_fpDivTest_b_12_sticky_ena_q); - - // redist24_expX_uid9_fpDivTest_b_12_mem_last(CONSTANT,291) - assign redist24_expX_uid9_fpDivTest_b_12_mem_last_q = 5'b01000; - - // redist24_expX_uid9_fpDivTest_b_12_cmp(LOGICAL,292) - assign redist24_expX_uid9_fpDivTest_b_12_cmp_b = {1'b0, redist24_expX_uid9_fpDivTest_b_12_rdmux_q}; - assign redist24_expX_uid9_fpDivTest_b_12_cmp_q = redist24_expX_uid9_fpDivTest_b_12_mem_last_q == redist24_expX_uid9_fpDivTest_b_12_cmp_b ? 1'b1 : 1'b0; - - // redist24_expX_uid9_fpDivTest_b_12_cmpReg(REG,293) - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - redist24_expX_uid9_fpDivTest_b_12_cmpReg_q <= 1'b0; - end - else if (en == 1'b1) - begin - redist24_expX_uid9_fpDivTest_b_12_cmpReg_q <= redist24_expX_uid9_fpDivTest_b_12_cmp_q; - end - end - - // redist24_expX_uid9_fpDivTest_b_12_sticky_ena(REG,296) - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - redist24_expX_uid9_fpDivTest_b_12_sticky_ena_q <= 1'b0; - end - else if (redist24_expX_uid9_fpDivTest_b_12_nor_q == 1'b1) - begin - redist24_expX_uid9_fpDivTest_b_12_sticky_ena_q <= redist24_expX_uid9_fpDivTest_b_12_cmpReg_q; - end - end - - // redist24_expX_uid9_fpDivTest_b_12_enaAnd(LOGICAL,297) - assign redist24_expX_uid9_fpDivTest_b_12_enaAnd_q = redist24_expX_uid9_fpDivTest_b_12_sticky_ena_q & en; - - // redist24_expX_uid9_fpDivTest_b_12_rdcnt(COUNTER,288) - // low=0, high=9, step=1, init=0 - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - redist24_expX_uid9_fpDivTest_b_12_rdcnt_i <= 4'd0; - redist24_expX_uid9_fpDivTest_b_12_rdcnt_eq <= 1'b0; - end - else if (en == 1'b1) - begin - if (redist24_expX_uid9_fpDivTest_b_12_rdcnt_i == 4'd8) - begin - redist24_expX_uid9_fpDivTest_b_12_rdcnt_eq <= 1'b1; - end - else - begin - redist24_expX_uid9_fpDivTest_b_12_rdcnt_eq <= 1'b0; - end - if (redist24_expX_uid9_fpDivTest_b_12_rdcnt_eq == 1'b1) - begin - redist24_expX_uid9_fpDivTest_b_12_rdcnt_i <= $unsigned(redist24_expX_uid9_fpDivTest_b_12_rdcnt_i) + $unsigned(4'd7); - end - else - begin - redist24_expX_uid9_fpDivTest_b_12_rdcnt_i <= $unsigned(redist24_expX_uid9_fpDivTest_b_12_rdcnt_i) + $unsigned(4'd1); - end - end - end - assign redist24_expX_uid9_fpDivTest_b_12_rdcnt_q = redist24_expX_uid9_fpDivTest_b_12_rdcnt_i[3:0]; - - // redist24_expX_uid9_fpDivTest_b_12_rdmux(MUX,289) - assign redist24_expX_uid9_fpDivTest_b_12_rdmux_s = en; - always @(redist24_expX_uid9_fpDivTest_b_12_rdmux_s or redist24_expX_uid9_fpDivTest_b_12_wraddr_q or redist24_expX_uid9_fpDivTest_b_12_rdcnt_q) - begin - unique case (redist24_expX_uid9_fpDivTest_b_12_rdmux_s) - 1'b0 : redist24_expX_uid9_fpDivTest_b_12_rdmux_q = redist24_expX_uid9_fpDivTest_b_12_wraddr_q; - 1'b1 : redist24_expX_uid9_fpDivTest_b_12_rdmux_q = redist24_expX_uid9_fpDivTest_b_12_rdcnt_q; - default : redist24_expX_uid9_fpDivTest_b_12_rdmux_q = 4'b0; - endcase - end + // redist15_fracXIsZero_uid25_fpDivTest_q_4(DELAY,167) + dspba_delay_ver #( .width(1), .depth(3), .reset_kind("ASYNC") ) + redist15_fracXIsZero_uid25_fpDivTest_q_4 ( .xin(fracXIsZero_uid25_fpDivTest_q), .xout(redist15_fracXIsZero_uid25_fpDivTest_q_4_q), .ena(en[0]), .clk(clk), .aclr(areset) ); // expX_uid9_fpDivTest(BITSELECT,8)@0 assign expX_uid9_fpDivTest_b = a[30:23]; - // redist24_expX_uid9_fpDivTest_b_12_wraddr(REG,290) - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - redist24_expX_uid9_fpDivTest_b_12_wraddr_q <= 4'b1001; - end - else - begin - redist24_expX_uid9_fpDivTest_b_12_wraddr_q <= redist24_expX_uid9_fpDivTest_b_12_rdmux_q; - end - end + // expXIsMax_uid24_fpDivTest(LOGICAL,23)@0 + 1 + assign expXIsMax_uid24_fpDivTest_qi = expX_uid9_fpDivTest_b == cstAllOWE_uid18_fpDivTest_q ? 1'b1 : 1'b0; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + expXIsMax_uid24_fpDivTest_delay ( .xin(expXIsMax_uid24_fpDivTest_qi), .xout(expXIsMax_uid24_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - // redist24_expX_uid9_fpDivTest_b_12_mem(DUALMEM,287) - assign redist24_expX_uid9_fpDivTest_b_12_mem_ia = expX_uid9_fpDivTest_b; - assign redist24_expX_uid9_fpDivTest_b_12_mem_aa = redist24_expX_uid9_fpDivTest_b_12_wraddr_q; - assign redist24_expX_uid9_fpDivTest_b_12_mem_ab = redist24_expX_uid9_fpDivTest_b_12_rdmux_q; - assign redist24_expX_uid9_fpDivTest_b_12_mem_reset0 = areset; - altera_syncram #( - .ram_block_type("MLAB"), - .operation_mode("DUAL_PORT"), - .width_a(8), - .widthad_a(4), - .numwords_a(10), - .width_b(8), - .widthad_b(4), - .numwords_b(10), - .lpm_type("altera_syncram"), - .width_byteena_a(1), - .address_reg_b("CLOCK0"), - .indata_reg_b("CLOCK0"), - .rdcontrol_reg_b("CLOCK0"), - .byteena_reg_b("CLOCK0"), - .outdata_reg_b("CLOCK1"), - .outdata_aclr_b("CLEAR1"), - .clock_enable_input_a("NORMAL"), - .clock_enable_input_b("NORMAL"), - .clock_enable_output_b("NORMAL"), - .read_during_write_mode_mixed_ports("DONT_CARE"), - .power_up_uninitialized("TRUE"), - .intended_device_family("Arria 10") - ) redist24_expX_uid9_fpDivTest_b_12_mem_dmem ( - .clocken1(redist24_expX_uid9_fpDivTest_b_12_enaAnd_q[0]), - .clocken0(VCC_q[0]), - .clock0(clk), - .aclr1(redist24_expX_uid9_fpDivTest_b_12_mem_reset0), - .clock1(clk), - .address_a(redist24_expX_uid9_fpDivTest_b_12_mem_aa), - .data_a(redist24_expX_uid9_fpDivTest_b_12_mem_ia), - .wren_a(en[0]), - .address_b(redist24_expX_uid9_fpDivTest_b_12_mem_ab), - .q_b(redist24_expX_uid9_fpDivTest_b_12_mem_iq), - .wren_b(), - .rden_a(), - .rden_b(), - .data_b(), - .clocken2(), - .clocken3(), - .aclr0(), - .addressstall_a(), - .addressstall_b(), - .byteena_a(), - .byteena_b(), - .eccencbypass(), - .eccencparity(), - .sclr(), - .address2_a(), - .address2_b(), - .q_a(), - .eccstatus() - ); - assign redist24_expX_uid9_fpDivTest_b_12_mem_q = redist24_expX_uid9_fpDivTest_b_12_mem_iq[7:0]; - - // redist24_expX_uid9_fpDivTest_b_12_outputreg(DELAY,286) - dspba_delay_ver #( .width(8), .depth(1), .reset_kind("ASYNC") ) - redist24_expX_uid9_fpDivTest_b_12_outputreg ( .xin(redist24_expX_uid9_fpDivTest_b_12_mem_q), .xout(redist24_expX_uid9_fpDivTest_b_12_outputreg_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // redist25_expX_uid9_fpDivTest_b_14(DELAY,211) - dspba_delay_ver #( .width(8), .depth(2), .reset_kind("ASYNC") ) - redist25_expX_uid9_fpDivTest_b_14 ( .xin(redist24_expX_uid9_fpDivTest_b_12_outputreg_q), .xout(redist25_expX_uid9_fpDivTest_b_14_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // expXIsMax_uid24_fpDivTest(LOGICAL,23)@14 - assign expXIsMax_uid24_fpDivTest_q = redist25_expX_uid9_fpDivTest_b_14_q == cstAllOWE_uid18_fpDivTest_q ? 1'b1 : 1'b0; + // redist16_expXIsMax_uid24_fpDivTest_q_14(DELAY,168) + dspba_delay_ver #( .width(1), .depth(13), .reset_kind("ASYNC") ) + redist16_expXIsMax_uid24_fpDivTest_q_14 ( .xin(expXIsMax_uid24_fpDivTest_q), .xout(redist16_expXIsMax_uid24_fpDivTest_q_14_q), .ena(en[0]), .clk(clk), .aclr(areset) ); // excI_x_uid27_fpDivTest(LOGICAL,26)@14 - assign excI_x_uid27_fpDivTest_q = expXIsMax_uid24_fpDivTest_q & fracXIsZero_uid25_fpDivTest_q; + assign excI_x_uid27_fpDivTest_q = redist16_expXIsMax_uid24_fpDivTest_q_14_q & redist15_fracXIsZero_uid25_fpDivTest_q_4_q; - // excXIYI_uid130_fpDivTest(LOGICAL,129)@14 - assign excXIYI_uid130_fpDivTest_q = excI_x_uid27_fpDivTest_q & excI_y_uid41_fpDivTest_q; + // excXIYI_uid96_fpDivTest(LOGICAL,95)@14 + assign excXIYI_uid96_fpDivTest_q = excI_x_uid27_fpDivTest_q & excI_y_uid41_fpDivTest_q; // fracXIsNotZero_uid40_fpDivTest(LOGICAL,39)@14 - assign fracXIsNotZero_uid40_fpDivTest_q = ~ (fracXIsZero_uid39_fpDivTest_q); + assign fracXIsNotZero_uid40_fpDivTest_q = ~ (redist12_fracXIsZero_uid39_fpDivTest_q_14_q); // excN_y_uid42_fpDivTest(LOGICAL,41)@14 - assign excN_y_uid42_fpDivTest_q = expXIsMax_uid38_fpDivTest_q & fracXIsNotZero_uid40_fpDivTest_q; + assign excN_y_uid42_fpDivTest_q = redist13_expXIsMax_uid38_fpDivTest_q_14_q & fracXIsNotZero_uid40_fpDivTest_q; // fracXIsNotZero_uid26_fpDivTest(LOGICAL,25)@14 - assign fracXIsNotZero_uid26_fpDivTest_q = ~ (fracXIsZero_uid25_fpDivTest_q); + assign fracXIsNotZero_uid26_fpDivTest_q = ~ (redist15_fracXIsZero_uid25_fpDivTest_q_4_q); // excN_x_uid28_fpDivTest(LOGICAL,27)@14 - assign excN_x_uid28_fpDivTest_q = expXIsMax_uid24_fpDivTest_q & fracXIsNotZero_uid26_fpDivTest_q; + assign excN_x_uid28_fpDivTest_q = redist16_expXIsMax_uid24_fpDivTest_q_14_q & fracXIsNotZero_uid26_fpDivTest_q; // cstAllZWE_uid20_fpDivTest(CONSTANT,19) assign cstAllZWE_uid20_fpDivTest_q = 8'b00000000; - // excZ_y_uid37_fpDivTest(LOGICAL,36)@14 - assign excZ_y_uid37_fpDivTest_q = redist20_expY_uid12_fpDivTest_b_14_q == cstAllZWE_uid20_fpDivTest_q ? 1'b1 : 1'b0; - - // excZ_x_uid23_fpDivTest(LOGICAL,22)@14 - assign excZ_x_uid23_fpDivTest_q = redist25_expX_uid9_fpDivTest_b_14_q == cstAllZWE_uid20_fpDivTest_q ? 1'b1 : 1'b0; - - // excXZYZ_uid129_fpDivTest(LOGICAL,128)@14 - assign excXZYZ_uid129_fpDivTest_q = excZ_x_uid23_fpDivTest_q & excZ_y_uid37_fpDivTest_q; - - // excRNaN_uid131_fpDivTest(LOGICAL,130)@14 + 1 - assign excRNaN_uid131_fpDivTest_qi = excXZYZ_uid129_fpDivTest_q | excN_x_uid28_fpDivTest_q | excN_y_uid42_fpDivTest_q | excXIYI_uid130_fpDivTest_q; + // excZ_y_uid37_fpDivTest(LOGICAL,36)@0 + 1 + assign excZ_y_uid37_fpDivTest_qi = expY_uid12_fpDivTest_b == cstAllZWE_uid20_fpDivTest_q ? 1'b1 : 1'b0; dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - excRNaN_uid131_fpDivTest_delay ( .xin(excRNaN_uid131_fpDivTest_qi), .xout(excRNaN_uid131_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + excZ_y_uid37_fpDivTest_delay ( .xin(excZ_y_uid37_fpDivTest_qi), .xout(excZ_y_uid37_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - // invExcRNaN_uid142_fpDivTest(LOGICAL,141)@15 - assign invExcRNaN_uid142_fpDivTest_q = ~ (excRNaN_uid131_fpDivTest_q); + // redist14_excZ_y_uid37_fpDivTest_q_14(DELAY,166) + dspba_delay_ver #( .width(1), .depth(13), .reset_kind("ASYNC") ) + redist14_excZ_y_uid37_fpDivTest_q_14 ( .xin(excZ_y_uid37_fpDivTest_q), .xout(redist14_excZ_y_uid37_fpDivTest_q_14_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // excZ_x_uid23_fpDivTest(LOGICAL,22)@0 + 1 + assign excZ_x_uid23_fpDivTest_qi = expX_uid9_fpDivTest_b == cstAllZWE_uid20_fpDivTest_q ? 1'b1 : 1'b0; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + excZ_x_uid23_fpDivTest_delay ( .xin(excZ_x_uid23_fpDivTest_qi), .xout(excZ_x_uid23_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist17_excZ_x_uid23_fpDivTest_q_14(DELAY,169) + dspba_delay_ver #( .width(1), .depth(13), .reset_kind("ASYNC") ) + redist17_excZ_x_uid23_fpDivTest_q_14 ( .xin(excZ_x_uid23_fpDivTest_q), .xout(redist17_excZ_x_uid23_fpDivTest_q_14_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // excXZYZ_uid95_fpDivTest(LOGICAL,94)@14 + assign excXZYZ_uid95_fpDivTest_q = redist17_excZ_x_uid23_fpDivTest_q_14_q & redist14_excZ_y_uid37_fpDivTest_q_14_q; + + // excRNaN_uid97_fpDivTest(LOGICAL,96)@14 + assign excRNaN_uid97_fpDivTest_q = excXZYZ_uid95_fpDivTest_q | excN_x_uid28_fpDivTest_q | excN_y_uid42_fpDivTest_q | excXIYI_uid96_fpDivTest_q; + + // invExcRNaN_uid108_fpDivTest(LOGICAL,107)@14 + assign invExcRNaN_uid108_fpDivTest_q = ~ (excRNaN_uid97_fpDivTest_q); // signY_uid14_fpDivTest(BITSELECT,13)@0 assign signY_uid14_fpDivTest_b = b[31:31]; @@ -1200,132 +582,39 @@ module acl_fdiv ( dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) signR_uid46_fpDivTest_delay ( .xin(signR_uid46_fpDivTest_qi), .xout(signR_uid46_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - // redist16_signR_uid46_fpDivTest_q_15(DELAY,202) - dspba_delay_ver #( .width(1), .depth(14), .reset_kind("ASYNC") ) - redist16_signR_uid46_fpDivTest_q_15 ( .xin(signR_uid46_fpDivTest_q), .xout(redist16_signR_uid46_fpDivTest_q_15_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + // redist11_signR_uid46_fpDivTest_q_14(DELAY,163) + dspba_delay_ver #( .width(1), .depth(13), .reset_kind("ASYNC") ) + redist11_signR_uid46_fpDivTest_q_14 ( .xin(signR_uid46_fpDivTest_q), .xout(redist11_signR_uid46_fpDivTest_q_14_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - // sRPostExc_uid143_fpDivTest(LOGICAL,142)@15 + 1 - assign sRPostExc_uid143_fpDivTest_qi = redist16_signR_uid46_fpDivTest_q_15_q & invExcRNaN_uid142_fpDivTest_q; + // sRPostExc_uid109_fpDivTest(LOGICAL,108)@14 + 1 + assign sRPostExc_uid109_fpDivTest_qi = redist11_signR_uid46_fpDivTest_q_14_q & invExcRNaN_uid108_fpDivTest_q; dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - sRPostExc_uid143_fpDivTest_delay ( .xin(sRPostExc_uid143_fpDivTest_qi), .xout(sRPostExc_uid143_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + sRPostExc_uid109_fpDivTest_delay ( .xin(sRPostExc_uid109_fpDivTest_qi), .xout(sRPostExc_uid109_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - // redist1_sRPostExc_uid143_fpDivTest_q_5(DELAY,187) - dspba_delay_ver #( .width(1), .depth(4), .reset_kind("ASYNC") ) - redist1_sRPostExc_uid143_fpDivTest_q_5 ( .xin(sRPostExc_uid143_fpDivTest_q), .xout(redist1_sRPostExc_uid143_fpDivTest_q_5_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + // lOAdded_uid58_fpDivTest(BITJOIN,57)@10 + assign lOAdded_uid58_fpDivTest_q = {VCC_q, redist19_fracX_uid10_fpDivTest_b_10_mem_q}; - // redist8_fracPostRndF_uid80_fpDivTest_q_5_notEnable(LOGICAL,233) - assign redist8_fracPostRndF_uid80_fpDivTest_q_5_notEnable_q = ~ (en); - - // redist8_fracPostRndF_uid80_fpDivTest_q_5_nor(LOGICAL,234) - assign redist8_fracPostRndF_uid80_fpDivTest_q_5_nor_q = ~ (redist8_fracPostRndF_uid80_fpDivTest_q_5_notEnable_q | redist8_fracPostRndF_uid80_fpDivTest_q_5_sticky_ena_q); - - // redist8_fracPostRndF_uid80_fpDivTest_q_5_mem_last(CONSTANT,230) - assign redist8_fracPostRndF_uid80_fpDivTest_q_5_mem_last_q = 2'b01; - - // redist8_fracPostRndF_uid80_fpDivTest_q_5_cmp(LOGICAL,231) - assign redist8_fracPostRndF_uid80_fpDivTest_q_5_cmp_q = redist8_fracPostRndF_uid80_fpDivTest_q_5_mem_last_q == redist8_fracPostRndF_uid80_fpDivTest_q_5_rdmux_q ? 1'b1 : 1'b0; - - // redist8_fracPostRndF_uid80_fpDivTest_q_5_cmpReg(REG,232) - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - redist8_fracPostRndF_uid80_fpDivTest_q_5_cmpReg_q <= 1'b0; - end - else if (en == 1'b1) - begin - redist8_fracPostRndF_uid80_fpDivTest_q_5_cmpReg_q <= redist8_fracPostRndF_uid80_fpDivTest_q_5_cmp_q; - end - end - - // redist8_fracPostRndF_uid80_fpDivTest_q_5_sticky_ena(REG,235) - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - redist8_fracPostRndF_uid80_fpDivTest_q_5_sticky_ena_q <= 1'b0; - end - else if (redist8_fracPostRndF_uid80_fpDivTest_q_5_nor_q == 1'b1) - begin - redist8_fracPostRndF_uid80_fpDivTest_q_5_sticky_ena_q <= redist8_fracPostRndF_uid80_fpDivTest_q_5_cmpReg_q; - end - end - - // redist8_fracPostRndF_uid80_fpDivTest_q_5_enaAnd(LOGICAL,236) - assign redist8_fracPostRndF_uid80_fpDivTest_q_5_enaAnd_q = redist8_fracPostRndF_uid80_fpDivTest_q_5_sticky_ena_q & en; - - // redist8_fracPostRndF_uid80_fpDivTest_q_5_rdcnt(COUNTER,227) - // low=0, high=2, step=1, init=0 - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - redist8_fracPostRndF_uid80_fpDivTest_q_5_rdcnt_i <= 2'd0; - redist8_fracPostRndF_uid80_fpDivTest_q_5_rdcnt_eq <= 1'b0; - end - else if (en == 1'b1) - begin - if (redist8_fracPostRndF_uid80_fpDivTest_q_5_rdcnt_i == 2'd1) - begin - redist8_fracPostRndF_uid80_fpDivTest_q_5_rdcnt_eq <= 1'b1; - end - else - begin - redist8_fracPostRndF_uid80_fpDivTest_q_5_rdcnt_eq <= 1'b0; - end - if (redist8_fracPostRndF_uid80_fpDivTest_q_5_rdcnt_eq == 1'b1) - begin - redist8_fracPostRndF_uid80_fpDivTest_q_5_rdcnt_i <= $unsigned(redist8_fracPostRndF_uid80_fpDivTest_q_5_rdcnt_i) + $unsigned(2'd2); - end - else - begin - redist8_fracPostRndF_uid80_fpDivTest_q_5_rdcnt_i <= $unsigned(redist8_fracPostRndF_uid80_fpDivTest_q_5_rdcnt_i) + $unsigned(2'd1); - end - end - end - assign redist8_fracPostRndF_uid80_fpDivTest_q_5_rdcnt_q = redist8_fracPostRndF_uid80_fpDivTest_q_5_rdcnt_i[1:0]; - - // redist8_fracPostRndF_uid80_fpDivTest_q_5_rdmux(MUX,228) - assign redist8_fracPostRndF_uid80_fpDivTest_q_5_rdmux_s = en; - always @(redist8_fracPostRndF_uid80_fpDivTest_q_5_rdmux_s or redist8_fracPostRndF_uid80_fpDivTest_q_5_wraddr_q or redist8_fracPostRndF_uid80_fpDivTest_q_5_rdcnt_q) - begin - unique case (redist8_fracPostRndF_uid80_fpDivTest_q_5_rdmux_s) - 1'b0 : redist8_fracPostRndF_uid80_fpDivTest_q_5_rdmux_q = redist8_fracPostRndF_uid80_fpDivTest_q_5_wraddr_q; - 1'b1 : redist8_fracPostRndF_uid80_fpDivTest_q_5_rdmux_q = redist8_fracPostRndF_uid80_fpDivTest_q_5_rdcnt_q; - default : redist8_fracPostRndF_uid80_fpDivTest_q_5_rdmux_q = 2'b0; - endcase - end - - // GND(CONSTANT,0) - assign GND_q = 1'b0; - - // fracXExt_uid77_fpDivTest(BITJOIN,76)@14 - assign fracXExt_uid77_fpDivTest_q = {redist22_fracX_uid10_fpDivTest_b_14_q, GND_q}; - - // lOAdded_uid57_fpDivTest(BITJOIN,56)@10 - assign lOAdded_uid57_fpDivTest_q = {VCC_q, redist21_fracX_uid10_fpDivTest_b_10_outputreg_q}; - - // redist9_lOAdded_uid57_fpDivTest_q_3(DELAY,195) + // redist4_lOAdded_uid58_fpDivTest_q_3(DELAY,156) dspba_delay_ver #( .width(24), .depth(3), .reset_kind("ASYNC") ) - redist9_lOAdded_uid57_fpDivTest_q_3 ( .xin(lOAdded_uid57_fpDivTest_q), .xout(redist9_lOAdded_uid57_fpDivTest_q_3_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + redist4_lOAdded_uid58_fpDivTest_q_3 ( .xin(lOAdded_uid58_fpDivTest_q), .xout(redist4_lOAdded_uid58_fpDivTest_q_3_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - // z4_uid60_fpDivTest(CONSTANT,59) - assign z4_uid60_fpDivTest_q = 4'b0000; + // oFracXSE_bottomExtension_uid61_fpDivTest(CONSTANT,60) + assign oFracXSE_bottomExtension_uid61_fpDivTest_q = 2'b00; - // oFracXZ4_uid61_fpDivTest(BITJOIN,60)@13 - assign oFracXZ4_uid61_fpDivTest_q = {redist9_lOAdded_uid57_fpDivTest_q_3_q, z4_uid60_fpDivTest_q}; + // oFracXSE_mergedSignalTM_uid63_fpDivTest(BITJOIN,62)@13 + assign oFracXSE_mergedSignalTM_uid63_fpDivTest_q = {redist4_lOAdded_uid58_fpDivTest_q_3_q, oFracXSE_bottomExtension_uid61_fpDivTest_q}; // yAddr_uid51_fpDivTest(BITSELECT,50)@0 assign yAddr_uid51_fpDivTest_b = fracY_uid13_fpDivTest_b[22:14]; - // memoryC2_uid152_invTables_lutmem(DUALMEM,181)@0 + 2 + // memoryC2_uid118_invTables_lutmem(DUALMEM,147)@0 + 2 // in j@20000000 - assign memoryC2_uid152_invTables_lutmem_aa = yAddr_uid51_fpDivTest_b; - assign memoryC2_uid152_invTables_lutmem_reset0 = areset; + assign memoryC2_uid118_invTables_lutmem_aa = yAddr_uid51_fpDivTest_b; + assign memoryC2_uid118_invTables_lutmem_reset0 = areset; altera_syncram #( .ram_block_type("M20K"), .operation_mode("ROM"), - .width_a(13), + .width_a(12), .widthad_a(9), .numwords_a(512), .lpm_type("altera_syncram"), @@ -1334,15 +623,15 @@ module acl_fdiv ( .outdata_aclr_a("CLEAR0"), .clock_enable_input_a("NORMAL"), .power_up_uninitialized("FALSE"), - .init_file("acl_fdiv_memoryC2_uid152_invTables_lutmem.hex"), + .init_file("acl_fdiv_memoryC2_uid118_invTables_lutmem.hex"), .init_file_layout("PORT_A"), .intended_device_family("Arria 10") - ) memoryC2_uid152_invTables_lutmem_dmem ( + ) memoryC2_uid118_invTables_lutmem_dmem ( .clocken0(en[0]), - .aclr0(memoryC2_uid152_invTables_lutmem_reset0), + .aclr0(memoryC2_uid118_invTables_lutmem_reset0), .clock0(clk), - .address_a(memoryC2_uid152_invTables_lutmem_aa), - .q_a(memoryC2_uid152_invTables_lutmem_ir), + .address_a(memoryC2_uid118_invTables_lutmem_aa), + .q_a(memoryC2_uid118_invTables_lutmem_ir), .wren_a(), .wren_b(), .rden_a(), @@ -1367,42 +656,42 @@ module acl_fdiv ( .q_b(), .eccstatus() ); - assign memoryC2_uid152_invTables_lutmem_r = memoryC2_uid152_invTables_lutmem_ir[12:0]; + assign memoryC2_uid118_invTables_lutmem_r = memoryC2_uid118_invTables_lutmem_ir[11:0]; // yPE_uid52_fpDivTest(BITSELECT,51)@0 assign yPE_uid52_fpDivTest_b = b[13:0]; - // redist12_yPE_uid52_fpDivTest_b_2(DELAY,198) + // redist6_yPE_uid52_fpDivTest_b_2(DELAY,158) dspba_delay_ver #( .width(14), .depth(2), .reset_kind("ASYNC") ) - redist12_yPE_uid52_fpDivTest_b_2 ( .xin(yPE_uid52_fpDivTest_b), .xout(redist12_yPE_uid52_fpDivTest_b_2_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + redist6_yPE_uid52_fpDivTest_b_2 ( .xin(yPE_uid52_fpDivTest_b), .xout(redist6_yPE_uid52_fpDivTest_b_2_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - // yT1_uid158_invPolyEval(BITSELECT,157)@2 - assign yT1_uid158_invPolyEval_b = redist12_yPE_uid52_fpDivTest_b_2_q[13:1]; + // yT1_uid124_invPolyEval(BITSELECT,123)@2 + assign yT1_uid124_invPolyEval_b = redist6_yPE_uid52_fpDivTest_b_2_q[13:2]; - // prodXY_uid174_pT1_uid159_invPolyEval_cma(CHAINMULTADD,184)@2 + 3 - assign prodXY_uid174_pT1_uid159_invPolyEval_cma_reset = areset; - assign prodXY_uid174_pT1_uid159_invPolyEval_cma_ena0 = en[0]; - assign prodXY_uid174_pT1_uid159_invPolyEval_cma_ena1 = prodXY_uid174_pT1_uid159_invPolyEval_cma_ena0; - assign prodXY_uid174_pT1_uid159_invPolyEval_cma_ena2 = prodXY_uid174_pT1_uid159_invPolyEval_cma_ena0; - assign prodXY_uid174_pT1_uid159_invPolyEval_cma_l[0] = $signed({1'b0, prodXY_uid174_pT1_uid159_invPolyEval_cma_a1[0][12:0]}); - assign prodXY_uid174_pT1_uid159_invPolyEval_cma_p[0] = prodXY_uid174_pT1_uid159_invPolyEval_cma_l[0] * prodXY_uid174_pT1_uid159_invPolyEval_cma_c1[0]; - assign prodXY_uid174_pT1_uid159_invPolyEval_cma_u[0] = prodXY_uid174_pT1_uid159_invPolyEval_cma_p[0][26:0]; - assign prodXY_uid174_pT1_uid159_invPolyEval_cma_w[0] = prodXY_uid174_pT1_uid159_invPolyEval_cma_u[0]; - assign prodXY_uid174_pT1_uid159_invPolyEval_cma_x[0] = prodXY_uid174_pT1_uid159_invPolyEval_cma_w[0]; - assign prodXY_uid174_pT1_uid159_invPolyEval_cma_y[0] = prodXY_uid174_pT1_uid159_invPolyEval_cma_x[0]; + // prodXY_uid140_pT1_uid125_invPolyEval_cma(CHAINMULTADD,149)@2 + 3 + assign prodXY_uid140_pT1_uid125_invPolyEval_cma_reset = areset; + assign prodXY_uid140_pT1_uid125_invPolyEval_cma_ena0 = en[0]; + assign prodXY_uid140_pT1_uid125_invPolyEval_cma_ena1 = prodXY_uid140_pT1_uid125_invPolyEval_cma_ena0; + assign prodXY_uid140_pT1_uid125_invPolyEval_cma_ena2 = prodXY_uid140_pT1_uid125_invPolyEval_cma_ena0; + assign prodXY_uid140_pT1_uid125_invPolyEval_cma_l[0] = $signed({1'b0, prodXY_uid140_pT1_uid125_invPolyEval_cma_a1[0][11:0]}); + assign prodXY_uid140_pT1_uid125_invPolyEval_cma_p[0] = prodXY_uid140_pT1_uid125_invPolyEval_cma_l[0] * prodXY_uid140_pT1_uid125_invPolyEval_cma_c1[0]; + assign prodXY_uid140_pT1_uid125_invPolyEval_cma_u[0] = prodXY_uid140_pT1_uid125_invPolyEval_cma_p[0][24:0]; + assign prodXY_uid140_pT1_uid125_invPolyEval_cma_w[0] = prodXY_uid140_pT1_uid125_invPolyEval_cma_u[0]; + assign prodXY_uid140_pT1_uid125_invPolyEval_cma_x[0] = prodXY_uid140_pT1_uid125_invPolyEval_cma_w[0]; + assign prodXY_uid140_pT1_uid125_invPolyEval_cma_y[0] = prodXY_uid140_pT1_uid125_invPolyEval_cma_x[0]; always @ (posedge clk or posedge areset) begin if (areset) begin - prodXY_uid174_pT1_uid159_invPolyEval_cma_a0 <= '{default: '0}; - prodXY_uid174_pT1_uid159_invPolyEval_cma_c0 <= '{default: '0}; + prodXY_uid140_pT1_uid125_invPolyEval_cma_a0 <= '{default: '0}; + prodXY_uid140_pT1_uid125_invPolyEval_cma_c0 <= '{default: '0}; end else begin - if (prodXY_uid174_pT1_uid159_invPolyEval_cma_ena0 == 1'b1) + if (prodXY_uid140_pT1_uid125_invPolyEval_cma_ena0 == 1'b1) begin - prodXY_uid174_pT1_uid159_invPolyEval_cma_a0[0] <= yT1_uid158_invPolyEval_b; - prodXY_uid174_pT1_uid159_invPolyEval_cma_c0[0] <= memoryC2_uid152_invTables_lutmem_r; + prodXY_uid140_pT1_uid125_invPolyEval_cma_a0[0] <= yT1_uid124_invPolyEval_b; + prodXY_uid140_pT1_uid125_invPolyEval_cma_c0[0] <= memoryC2_uid118_invTables_lutmem_r; end end end @@ -1410,15 +699,15 @@ module acl_fdiv ( begin if (areset) begin - prodXY_uid174_pT1_uid159_invPolyEval_cma_a1 <= '{default: '0}; - prodXY_uid174_pT1_uid159_invPolyEval_cma_c1 <= '{default: '0}; + prodXY_uid140_pT1_uid125_invPolyEval_cma_a1 <= '{default: '0}; + prodXY_uid140_pT1_uid125_invPolyEval_cma_c1 <= '{default: '0}; end else begin - if (prodXY_uid174_pT1_uid159_invPolyEval_cma_ena2 == 1'b1) + if (prodXY_uid140_pT1_uid125_invPolyEval_cma_ena2 == 1'b1) begin - prodXY_uid174_pT1_uid159_invPolyEval_cma_a1 <= prodXY_uid174_pT1_uid159_invPolyEval_cma_a0; - prodXY_uid174_pT1_uid159_invPolyEval_cma_c1 <= prodXY_uid174_pT1_uid159_invPolyEval_cma_c0; + prodXY_uid140_pT1_uid125_invPolyEval_cma_a1 <= prodXY_uid140_pT1_uid125_invPolyEval_cma_a0; + prodXY_uid140_pT1_uid125_invPolyEval_cma_c1 <= prodXY_uid140_pT1_uid125_invPolyEval_cma_c0; end end end @@ -1426,38 +715,38 @@ module acl_fdiv ( begin if (areset) begin - prodXY_uid174_pT1_uid159_invPolyEval_cma_s <= '{default: '0}; + prodXY_uid140_pT1_uid125_invPolyEval_cma_s <= '{default: '0}; end else begin - if (prodXY_uid174_pT1_uid159_invPolyEval_cma_ena1 == 1'b1) + if (prodXY_uid140_pT1_uid125_invPolyEval_cma_ena1 == 1'b1) begin - prodXY_uid174_pT1_uid159_invPolyEval_cma_s[0] <= prodXY_uid174_pT1_uid159_invPolyEval_cma_y[0]; + prodXY_uid140_pT1_uid125_invPolyEval_cma_s[0] <= prodXY_uid140_pT1_uid125_invPolyEval_cma_y[0]; end end end - dspba_delay_ver #( .width(26), .depth(0), .reset_kind("ASYNC") ) - prodXY_uid174_pT1_uid159_invPolyEval_cma_delay ( .xin(prodXY_uid174_pT1_uid159_invPolyEval_cma_s[0][25:0]), .xout(prodXY_uid174_pT1_uid159_invPolyEval_cma_qq), .ena(en[0]), .clk(clk), .aclr(areset) ); - assign prodXY_uid174_pT1_uid159_invPolyEval_cma_q = prodXY_uid174_pT1_uid159_invPolyEval_cma_qq[25:0]; + dspba_delay_ver #( .width(24), .depth(0), .reset_kind("ASYNC") ) + prodXY_uid140_pT1_uid125_invPolyEval_cma_delay ( .xin(prodXY_uid140_pT1_uid125_invPolyEval_cma_s[0][23:0]), .xout(prodXY_uid140_pT1_uid125_invPolyEval_cma_qq), .ena(en[0]), .clk(clk), .aclr(areset) ); + assign prodXY_uid140_pT1_uid125_invPolyEval_cma_q = prodXY_uid140_pT1_uid125_invPolyEval_cma_qq[23:0]; - // osig_uid175_pT1_uid159_invPolyEval(BITSELECT,174)@5 - assign osig_uid175_pT1_uid159_invPolyEval_b = prodXY_uid174_pT1_uid159_invPolyEval_cma_q[25:12]; + // osig_uid141_pT1_uid125_invPolyEval(BITSELECT,140)@5 + assign osig_uid141_pT1_uid125_invPolyEval_b = prodXY_uid140_pT1_uid125_invPolyEval_cma_q[23:11]; - // highBBits_uid161_invPolyEval(BITSELECT,160)@5 - assign highBBits_uid161_invPolyEval_b = osig_uid175_pT1_uid159_invPolyEval_b[13:1]; + // highBBits_uid127_invPolyEval(BITSELECT,126)@5 + assign highBBits_uid127_invPolyEval_b = osig_uid141_pT1_uid125_invPolyEval_b[12:1]; - // redist14_yAddr_uid51_fpDivTest_b_3(DELAY,200) + // redist8_yAddr_uid51_fpDivTest_b_3(DELAY,160) dspba_delay_ver #( .width(9), .depth(3), .reset_kind("ASYNC") ) - redist14_yAddr_uid51_fpDivTest_b_3 ( .xin(yAddr_uid51_fpDivTest_b), .xout(redist14_yAddr_uid51_fpDivTest_b_3_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + redist8_yAddr_uid51_fpDivTest_b_3 ( .xin(yAddr_uid51_fpDivTest_b), .xout(redist8_yAddr_uid51_fpDivTest_b_3_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - // memoryC1_uid149_invTables_lutmem(DUALMEM,180)@3 + 2 + // memoryC1_uid115_invTables_lutmem(DUALMEM,146)@3 + 2 // in j@20000000 - assign memoryC1_uid149_invTables_lutmem_aa = redist14_yAddr_uid51_fpDivTest_b_3_q; - assign memoryC1_uid149_invTables_lutmem_reset0 = areset; + assign memoryC1_uid115_invTables_lutmem_aa = redist8_yAddr_uid51_fpDivTest_b_3_q; + assign memoryC1_uid115_invTables_lutmem_reset0 = areset; altera_syncram #( .ram_block_type("M20K"), .operation_mode("ROM"), - .width_a(22), + .width_a(21), .widthad_a(9), .numwords_a(512), .lpm_type("altera_syncram"), @@ -1466,15 +755,15 @@ module acl_fdiv ( .outdata_aclr_a("CLEAR0"), .clock_enable_input_a("NORMAL"), .power_up_uninitialized("FALSE"), - .init_file("acl_fdiv_memoryC1_uid149_invTables_lutmem.hex"), + .init_file("acl_fdiv_memoryC1_uid115_invTables_lutmem.hex"), .init_file_layout("PORT_A"), .intended_device_family("Arria 10") - ) memoryC1_uid149_invTables_lutmem_dmem ( + ) memoryC1_uid115_invTables_lutmem_dmem ( .clocken0(en[0]), - .aclr0(memoryC1_uid149_invTables_lutmem_reset0), + .aclr0(memoryC1_uid115_invTables_lutmem_reset0), .clock0(clk), - .address_a(memoryC1_uid149_invTables_lutmem_aa), - .q_a(memoryC1_uid149_invTables_lutmem_ir), + .address_a(memoryC1_uid115_invTables_lutmem_aa), + .q_a(memoryC1_uid115_invTables_lutmem_ir), .wren_a(), .wren_b(), .rden_a(), @@ -1499,136 +788,136 @@ module acl_fdiv ( .q_b(), .eccstatus() ); - assign memoryC1_uid149_invTables_lutmem_r = memoryC1_uid149_invTables_lutmem_ir[21:0]; + assign memoryC1_uid115_invTables_lutmem_r = memoryC1_uid115_invTables_lutmem_ir[20:0]; - // s1sumAHighB_uid162_invPolyEval(ADD,161)@5 + 1 - assign s1sumAHighB_uid162_invPolyEval_a = {{1{memoryC1_uid149_invTables_lutmem_r[21]}}, memoryC1_uid149_invTables_lutmem_r}; - assign s1sumAHighB_uid162_invPolyEval_b = {{10{highBBits_uid161_invPolyEval_b[12]}}, highBBits_uid161_invPolyEval_b}; + // s1sumAHighB_uid128_invPolyEval(ADD,127)@5 + 1 + assign s1sumAHighB_uid128_invPolyEval_a = {{1{memoryC1_uid115_invTables_lutmem_r[20]}}, memoryC1_uid115_invTables_lutmem_r}; + assign s1sumAHighB_uid128_invPolyEval_b = {{10{highBBits_uid127_invPolyEval_b[11]}}, highBBits_uid127_invPolyEval_b}; always @ (posedge clk or posedge areset) begin if (areset) begin - s1sumAHighB_uid162_invPolyEval_o <= 23'b0; + s1sumAHighB_uid128_invPolyEval_o <= 22'b0; end else if (en == 1'b1) begin - s1sumAHighB_uid162_invPolyEval_o <= $signed(s1sumAHighB_uid162_invPolyEval_a) + $signed(s1sumAHighB_uid162_invPolyEval_b); + s1sumAHighB_uid128_invPolyEval_o <= $signed(s1sumAHighB_uid128_invPolyEval_a) + $signed(s1sumAHighB_uid128_invPolyEval_b); end end - assign s1sumAHighB_uid162_invPolyEval_q = s1sumAHighB_uid162_invPolyEval_o[22:0]; + assign s1sumAHighB_uid128_invPolyEval_q = s1sumAHighB_uid128_invPolyEval_o[21:0]; - // lowRangeB_uid160_invPolyEval(BITSELECT,159)@5 - assign lowRangeB_uid160_invPolyEval_in = osig_uid175_pT1_uid159_invPolyEval_b[0:0]; - assign lowRangeB_uid160_invPolyEval_b = lowRangeB_uid160_invPolyEval_in[0:0]; + // lowRangeB_uid126_invPolyEval(BITSELECT,125)@5 + assign lowRangeB_uid126_invPolyEval_in = osig_uid141_pT1_uid125_invPolyEval_b[0:0]; + assign lowRangeB_uid126_invPolyEval_b = lowRangeB_uid126_invPolyEval_in[0:0]; - // redist0_lowRangeB_uid160_invPolyEval_b_1(DELAY,186) + // redist1_lowRangeB_uid126_invPolyEval_b_1(DELAY,153) dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - redist0_lowRangeB_uid160_invPolyEval_b_1 ( .xin(lowRangeB_uid160_invPolyEval_b), .xout(redist0_lowRangeB_uid160_invPolyEval_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + redist1_lowRangeB_uid126_invPolyEval_b_1 ( .xin(lowRangeB_uid126_invPolyEval_b), .xout(redist1_lowRangeB_uid126_invPolyEval_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - // s1_uid163_invPolyEval(BITJOIN,162)@6 - assign s1_uid163_invPolyEval_q = {s1sumAHighB_uid162_invPolyEval_q, redist0_lowRangeB_uid160_invPolyEval_b_1_q}; + // s1_uid129_invPolyEval(BITJOIN,128)@6 + assign s1_uid129_invPolyEval_q = {s1sumAHighB_uid128_invPolyEval_q, redist1_lowRangeB_uid126_invPolyEval_b_1_q}; - // redist13_yPE_uid52_fpDivTest_b_6_notEnable(LOGICAL,244) - assign redist13_yPE_uid52_fpDivTest_b_6_notEnable_q = ~ (en); + // redist7_yPE_uid52_fpDivTest_b_6_notEnable(LOGICAL,179) + assign redist7_yPE_uid52_fpDivTest_b_6_notEnable_q = ~ (en); - // redist13_yPE_uid52_fpDivTest_b_6_nor(LOGICAL,245) - assign redist13_yPE_uid52_fpDivTest_b_6_nor_q = ~ (redist13_yPE_uid52_fpDivTest_b_6_notEnable_q | redist13_yPE_uid52_fpDivTest_b_6_sticky_ena_q); + // redist7_yPE_uid52_fpDivTest_b_6_nor(LOGICAL,180) + assign redist7_yPE_uid52_fpDivTest_b_6_nor_q = ~ (redist7_yPE_uid52_fpDivTest_b_6_notEnable_q | redist7_yPE_uid52_fpDivTest_b_6_sticky_ena_q); - // redist13_yPE_uid52_fpDivTest_b_6_mem_last(CONSTANT,241) - assign redist13_yPE_uid52_fpDivTest_b_6_mem_last_q = 2'b01; + // redist7_yPE_uid52_fpDivTest_b_6_mem_last(CONSTANT,176) + assign redist7_yPE_uid52_fpDivTest_b_6_mem_last_q = 2'b01; - // redist13_yPE_uid52_fpDivTest_b_6_cmp(LOGICAL,242) - assign redist13_yPE_uid52_fpDivTest_b_6_cmp_q = redist13_yPE_uid52_fpDivTest_b_6_mem_last_q == redist13_yPE_uid52_fpDivTest_b_6_rdmux_q ? 1'b1 : 1'b0; + // redist7_yPE_uid52_fpDivTest_b_6_cmp(LOGICAL,177) + assign redist7_yPE_uid52_fpDivTest_b_6_cmp_q = redist7_yPE_uid52_fpDivTest_b_6_mem_last_q == redist7_yPE_uid52_fpDivTest_b_6_rdmux_q ? 1'b1 : 1'b0; - // redist13_yPE_uid52_fpDivTest_b_6_cmpReg(REG,243) + // redist7_yPE_uid52_fpDivTest_b_6_cmpReg(REG,178) always @ (posedge clk or posedge areset) begin if (areset) begin - redist13_yPE_uid52_fpDivTest_b_6_cmpReg_q <= 1'b0; + redist7_yPE_uid52_fpDivTest_b_6_cmpReg_q <= 1'b0; end else if (en == 1'b1) begin - redist13_yPE_uid52_fpDivTest_b_6_cmpReg_q <= redist13_yPE_uid52_fpDivTest_b_6_cmp_q; + redist7_yPE_uid52_fpDivTest_b_6_cmpReg_q <= redist7_yPE_uid52_fpDivTest_b_6_cmp_q; end end - // redist13_yPE_uid52_fpDivTest_b_6_sticky_ena(REG,246) + // redist7_yPE_uid52_fpDivTest_b_6_sticky_ena(REG,181) always @ (posedge clk or posedge areset) begin if (areset) begin - redist13_yPE_uid52_fpDivTest_b_6_sticky_ena_q <= 1'b0; + redist7_yPE_uid52_fpDivTest_b_6_sticky_ena_q <= 1'b0; end - else if (redist13_yPE_uid52_fpDivTest_b_6_nor_q == 1'b1) + else if (redist7_yPE_uid52_fpDivTest_b_6_nor_q == 1'b1) begin - redist13_yPE_uid52_fpDivTest_b_6_sticky_ena_q <= redist13_yPE_uid52_fpDivTest_b_6_cmpReg_q; + redist7_yPE_uid52_fpDivTest_b_6_sticky_ena_q <= redist7_yPE_uid52_fpDivTest_b_6_cmpReg_q; end end - // redist13_yPE_uid52_fpDivTest_b_6_enaAnd(LOGICAL,247) - assign redist13_yPE_uid52_fpDivTest_b_6_enaAnd_q = redist13_yPE_uid52_fpDivTest_b_6_sticky_ena_q & en; + // redist7_yPE_uid52_fpDivTest_b_6_enaAnd(LOGICAL,182) + assign redist7_yPE_uid52_fpDivTest_b_6_enaAnd_q = redist7_yPE_uid52_fpDivTest_b_6_sticky_ena_q & en; - // redist13_yPE_uid52_fpDivTest_b_6_rdcnt(COUNTER,238) + // redist7_yPE_uid52_fpDivTest_b_6_rdcnt(COUNTER,173) // low=0, high=2, step=1, init=0 always @ (posedge clk or posedge areset) begin if (areset) begin - redist13_yPE_uid52_fpDivTest_b_6_rdcnt_i <= 2'd0; - redist13_yPE_uid52_fpDivTest_b_6_rdcnt_eq <= 1'b0; + redist7_yPE_uid52_fpDivTest_b_6_rdcnt_i <= 2'd0; + redist7_yPE_uid52_fpDivTest_b_6_rdcnt_eq <= 1'b0; end else if (en == 1'b1) begin - if (redist13_yPE_uid52_fpDivTest_b_6_rdcnt_i == 2'd1) + if (redist7_yPE_uid52_fpDivTest_b_6_rdcnt_i == 2'd1) begin - redist13_yPE_uid52_fpDivTest_b_6_rdcnt_eq <= 1'b1; + redist7_yPE_uid52_fpDivTest_b_6_rdcnt_eq <= 1'b1; end else begin - redist13_yPE_uid52_fpDivTest_b_6_rdcnt_eq <= 1'b0; + redist7_yPE_uid52_fpDivTest_b_6_rdcnt_eq <= 1'b0; end - if (redist13_yPE_uid52_fpDivTest_b_6_rdcnt_eq == 1'b1) + if (redist7_yPE_uid52_fpDivTest_b_6_rdcnt_eq == 1'b1) begin - redist13_yPE_uid52_fpDivTest_b_6_rdcnt_i <= $unsigned(redist13_yPE_uid52_fpDivTest_b_6_rdcnt_i) + $unsigned(2'd2); + redist7_yPE_uid52_fpDivTest_b_6_rdcnt_i <= $unsigned(redist7_yPE_uid52_fpDivTest_b_6_rdcnt_i) + $unsigned(2'd2); end else begin - redist13_yPE_uid52_fpDivTest_b_6_rdcnt_i <= $unsigned(redist13_yPE_uid52_fpDivTest_b_6_rdcnt_i) + $unsigned(2'd1); + redist7_yPE_uid52_fpDivTest_b_6_rdcnt_i <= $unsigned(redist7_yPE_uid52_fpDivTest_b_6_rdcnt_i) + $unsigned(2'd1); end end end - assign redist13_yPE_uid52_fpDivTest_b_6_rdcnt_q = redist13_yPE_uid52_fpDivTest_b_6_rdcnt_i[1:0]; + assign redist7_yPE_uid52_fpDivTest_b_6_rdcnt_q = redist7_yPE_uid52_fpDivTest_b_6_rdcnt_i[1:0]; - // redist13_yPE_uid52_fpDivTest_b_6_rdmux(MUX,239) - assign redist13_yPE_uid52_fpDivTest_b_6_rdmux_s = en; - always @(redist13_yPE_uid52_fpDivTest_b_6_rdmux_s or redist13_yPE_uid52_fpDivTest_b_6_wraddr_q or redist13_yPE_uid52_fpDivTest_b_6_rdcnt_q) + // redist7_yPE_uid52_fpDivTest_b_6_rdmux(MUX,174) + assign redist7_yPE_uid52_fpDivTest_b_6_rdmux_s = en; + always @(redist7_yPE_uid52_fpDivTest_b_6_rdmux_s or redist7_yPE_uid52_fpDivTest_b_6_wraddr_q or redist7_yPE_uid52_fpDivTest_b_6_rdcnt_q) begin - unique case (redist13_yPE_uid52_fpDivTest_b_6_rdmux_s) - 1'b0 : redist13_yPE_uid52_fpDivTest_b_6_rdmux_q = redist13_yPE_uid52_fpDivTest_b_6_wraddr_q; - 1'b1 : redist13_yPE_uid52_fpDivTest_b_6_rdmux_q = redist13_yPE_uid52_fpDivTest_b_6_rdcnt_q; - default : redist13_yPE_uid52_fpDivTest_b_6_rdmux_q = 2'b0; + unique case (redist7_yPE_uid52_fpDivTest_b_6_rdmux_s) + 1'b0 : redist7_yPE_uid52_fpDivTest_b_6_rdmux_q = redist7_yPE_uid52_fpDivTest_b_6_wraddr_q; + 1'b1 : redist7_yPE_uid52_fpDivTest_b_6_rdmux_q = redist7_yPE_uid52_fpDivTest_b_6_rdcnt_q; + default : redist7_yPE_uid52_fpDivTest_b_6_rdmux_q = 2'b0; endcase end - // redist13_yPE_uid52_fpDivTest_b_6_wraddr(REG,240) + // redist7_yPE_uid52_fpDivTest_b_6_wraddr(REG,175) always @ (posedge clk or posedge areset) begin if (areset) begin - redist13_yPE_uid52_fpDivTest_b_6_wraddr_q <= 2'b10; + redist7_yPE_uid52_fpDivTest_b_6_wraddr_q <= 2'b10; end else begin - redist13_yPE_uid52_fpDivTest_b_6_wraddr_q <= redist13_yPE_uid52_fpDivTest_b_6_rdmux_q; + redist7_yPE_uid52_fpDivTest_b_6_wraddr_q <= redist7_yPE_uid52_fpDivTest_b_6_rdmux_q; end end - // redist13_yPE_uid52_fpDivTest_b_6_mem(DUALMEM,237) - assign redist13_yPE_uid52_fpDivTest_b_6_mem_ia = redist12_yPE_uid52_fpDivTest_b_2_q; - assign redist13_yPE_uid52_fpDivTest_b_6_mem_aa = redist13_yPE_uid52_fpDivTest_b_6_wraddr_q; - assign redist13_yPE_uid52_fpDivTest_b_6_mem_ab = redist13_yPE_uid52_fpDivTest_b_6_rdmux_q; - assign redist13_yPE_uid52_fpDivTest_b_6_mem_reset0 = areset; + // redist7_yPE_uid52_fpDivTest_b_6_mem(DUALMEM,172) + assign redist7_yPE_uid52_fpDivTest_b_6_mem_ia = redist6_yPE_uid52_fpDivTest_b_2_q; + assign redist7_yPE_uid52_fpDivTest_b_6_mem_aa = redist7_yPE_uid52_fpDivTest_b_6_wraddr_q; + assign redist7_yPE_uid52_fpDivTest_b_6_mem_ab = redist7_yPE_uid52_fpDivTest_b_6_rdmux_q; + assign redist7_yPE_uid52_fpDivTest_b_6_mem_reset0 = areset; altera_syncram #( .ram_block_type("MLAB"), .operation_mode("DUAL_PORT"), @@ -1652,17 +941,17 @@ module acl_fdiv ( .read_during_write_mode_mixed_ports("DONT_CARE"), .power_up_uninitialized("TRUE"), .intended_device_family("Arria 10") - ) redist13_yPE_uid52_fpDivTest_b_6_mem_dmem ( - .clocken1(redist13_yPE_uid52_fpDivTest_b_6_enaAnd_q[0]), + ) redist7_yPE_uid52_fpDivTest_b_6_mem_dmem ( + .clocken1(redist7_yPE_uid52_fpDivTest_b_6_enaAnd_q[0]), .clocken0(VCC_q[0]), .clock0(clk), - .aclr1(redist13_yPE_uid52_fpDivTest_b_6_mem_reset0), + .aclr1(redist7_yPE_uid52_fpDivTest_b_6_mem_reset0), .clock1(clk), - .address_a(redist13_yPE_uid52_fpDivTest_b_6_mem_aa), - .data_a(redist13_yPE_uid52_fpDivTest_b_6_mem_ia), + .address_a(redist7_yPE_uid52_fpDivTest_b_6_mem_aa), + .data_a(redist7_yPE_uid52_fpDivTest_b_6_mem_ia), .wren_a(en[0]), - .address_b(redist13_yPE_uid52_fpDivTest_b_6_mem_ab), - .q_b(redist13_yPE_uid52_fpDivTest_b_6_mem_iq), + .address_b(redist7_yPE_uid52_fpDivTest_b_6_mem_ab), + .q_b(redist7_yPE_uid52_fpDivTest_b_6_mem_iq), .wren_b(), .rden_a(), .rden_b(), @@ -1682,32 +971,32 @@ module acl_fdiv ( .q_a(), .eccstatus() ); - assign redist13_yPE_uid52_fpDivTest_b_6_mem_q = redist13_yPE_uid52_fpDivTest_b_6_mem_iq[13:0]; + assign redist7_yPE_uid52_fpDivTest_b_6_mem_q = redist7_yPE_uid52_fpDivTest_b_6_mem_iq[13:0]; - // prodXY_uid177_pT2_uid165_invPolyEval_cma(CHAINMULTADD,185)@6 + 3 - assign prodXY_uid177_pT2_uid165_invPolyEval_cma_reset = areset; - assign prodXY_uid177_pT2_uid165_invPolyEval_cma_ena0 = en[0]; - assign prodXY_uid177_pT2_uid165_invPolyEval_cma_ena1 = prodXY_uid177_pT2_uid165_invPolyEval_cma_ena0; - assign prodXY_uid177_pT2_uid165_invPolyEval_cma_ena2 = prodXY_uid177_pT2_uid165_invPolyEval_cma_ena0; - assign prodXY_uid177_pT2_uid165_invPolyEval_cma_l[0] = $signed({1'b0, prodXY_uid177_pT2_uid165_invPolyEval_cma_a1[0][13:0]}); - assign prodXY_uid177_pT2_uid165_invPolyEval_cma_p[0] = prodXY_uid177_pT2_uid165_invPolyEval_cma_l[0] * prodXY_uid177_pT2_uid165_invPolyEval_cma_c1[0]; - assign prodXY_uid177_pT2_uid165_invPolyEval_cma_u[0] = prodXY_uid177_pT2_uid165_invPolyEval_cma_p[0][38:0]; - assign prodXY_uid177_pT2_uid165_invPolyEval_cma_w[0] = prodXY_uid177_pT2_uid165_invPolyEval_cma_u[0]; - assign prodXY_uid177_pT2_uid165_invPolyEval_cma_x[0] = prodXY_uid177_pT2_uid165_invPolyEval_cma_w[0]; - assign prodXY_uid177_pT2_uid165_invPolyEval_cma_y[0] = prodXY_uid177_pT2_uid165_invPolyEval_cma_x[0]; + // prodXY_uid143_pT2_uid131_invPolyEval_cma(CHAINMULTADD,150)@6 + 3 + assign prodXY_uid143_pT2_uid131_invPolyEval_cma_reset = areset; + assign prodXY_uid143_pT2_uid131_invPolyEval_cma_ena0 = en[0]; + assign prodXY_uid143_pT2_uid131_invPolyEval_cma_ena1 = prodXY_uid143_pT2_uid131_invPolyEval_cma_ena0; + assign prodXY_uid143_pT2_uid131_invPolyEval_cma_ena2 = prodXY_uid143_pT2_uid131_invPolyEval_cma_ena0; + assign prodXY_uid143_pT2_uid131_invPolyEval_cma_l[0] = $signed({1'b0, prodXY_uid143_pT2_uid131_invPolyEval_cma_a1[0][13:0]}); + assign prodXY_uid143_pT2_uid131_invPolyEval_cma_p[0] = prodXY_uid143_pT2_uid131_invPolyEval_cma_l[0] * prodXY_uid143_pT2_uid131_invPolyEval_cma_c1[0]; + assign prodXY_uid143_pT2_uid131_invPolyEval_cma_u[0] = prodXY_uid143_pT2_uid131_invPolyEval_cma_p[0][37:0]; + assign prodXY_uid143_pT2_uid131_invPolyEval_cma_w[0] = prodXY_uid143_pT2_uid131_invPolyEval_cma_u[0]; + assign prodXY_uid143_pT2_uid131_invPolyEval_cma_x[0] = prodXY_uid143_pT2_uid131_invPolyEval_cma_w[0]; + assign prodXY_uid143_pT2_uid131_invPolyEval_cma_y[0] = prodXY_uid143_pT2_uid131_invPolyEval_cma_x[0]; always @ (posedge clk or posedge areset) begin if (areset) begin - prodXY_uid177_pT2_uid165_invPolyEval_cma_a0 <= '{default: '0}; - prodXY_uid177_pT2_uid165_invPolyEval_cma_c0 <= '{default: '0}; + prodXY_uid143_pT2_uid131_invPolyEval_cma_a0 <= '{default: '0}; + prodXY_uid143_pT2_uid131_invPolyEval_cma_c0 <= '{default: '0}; end else begin - if (prodXY_uid177_pT2_uid165_invPolyEval_cma_ena0 == 1'b1) + if (prodXY_uid143_pT2_uid131_invPolyEval_cma_ena0 == 1'b1) begin - prodXY_uid177_pT2_uid165_invPolyEval_cma_a0[0] <= redist13_yPE_uid52_fpDivTest_b_6_mem_q; - prodXY_uid177_pT2_uid165_invPolyEval_cma_c0[0] <= s1_uid163_invPolyEval_q; + prodXY_uid143_pT2_uid131_invPolyEval_cma_a0[0] <= redist7_yPE_uid52_fpDivTest_b_6_mem_q; + prodXY_uid143_pT2_uid131_invPolyEval_cma_c0[0] <= s1_uid129_invPolyEval_q; end end end @@ -1715,15 +1004,15 @@ module acl_fdiv ( begin if (areset) begin - prodXY_uid177_pT2_uid165_invPolyEval_cma_a1 <= '{default: '0}; - prodXY_uid177_pT2_uid165_invPolyEval_cma_c1 <= '{default: '0}; + prodXY_uid143_pT2_uid131_invPolyEval_cma_a1 <= '{default: '0}; + prodXY_uid143_pT2_uid131_invPolyEval_cma_c1 <= '{default: '0}; end else begin - if (prodXY_uid177_pT2_uid165_invPolyEval_cma_ena2 == 1'b1) + if (prodXY_uid143_pT2_uid131_invPolyEval_cma_ena2 == 1'b1) begin - prodXY_uid177_pT2_uid165_invPolyEval_cma_a1 <= prodXY_uid177_pT2_uid165_invPolyEval_cma_a0; - prodXY_uid177_pT2_uid165_invPolyEval_cma_c1 <= prodXY_uid177_pT2_uid165_invPolyEval_cma_c0; + prodXY_uid143_pT2_uid131_invPolyEval_cma_a1 <= prodXY_uid143_pT2_uid131_invPolyEval_cma_a0; + prodXY_uid143_pT2_uid131_invPolyEval_cma_c1 <= prodXY_uid143_pT2_uid131_invPolyEval_cma_c0; end end end @@ -1731,38 +1020,38 @@ module acl_fdiv ( begin if (areset) begin - prodXY_uid177_pT2_uid165_invPolyEval_cma_s <= '{default: '0}; + prodXY_uid143_pT2_uid131_invPolyEval_cma_s <= '{default: '0}; end else begin - if (prodXY_uid177_pT2_uid165_invPolyEval_cma_ena1 == 1'b1) + if (prodXY_uid143_pT2_uid131_invPolyEval_cma_ena1 == 1'b1) begin - prodXY_uid177_pT2_uid165_invPolyEval_cma_s[0] <= prodXY_uid177_pT2_uid165_invPolyEval_cma_y[0]; + prodXY_uid143_pT2_uid131_invPolyEval_cma_s[0] <= prodXY_uid143_pT2_uid131_invPolyEval_cma_y[0]; end end end - dspba_delay_ver #( .width(38), .depth(0), .reset_kind("ASYNC") ) - prodXY_uid177_pT2_uid165_invPolyEval_cma_delay ( .xin(prodXY_uid177_pT2_uid165_invPolyEval_cma_s[0][37:0]), .xout(prodXY_uid177_pT2_uid165_invPolyEval_cma_qq), .ena(en[0]), .clk(clk), .aclr(areset) ); - assign prodXY_uid177_pT2_uid165_invPolyEval_cma_q = prodXY_uid177_pT2_uid165_invPolyEval_cma_qq[37:0]; + dspba_delay_ver #( .width(37), .depth(0), .reset_kind("ASYNC") ) + prodXY_uid143_pT2_uid131_invPolyEval_cma_delay ( .xin(prodXY_uid143_pT2_uid131_invPolyEval_cma_s[0][36:0]), .xout(prodXY_uid143_pT2_uid131_invPolyEval_cma_qq), .ena(en[0]), .clk(clk), .aclr(areset) ); + assign prodXY_uid143_pT2_uid131_invPolyEval_cma_q = prodXY_uid143_pT2_uid131_invPolyEval_cma_qq[36:0]; - // osig_uid178_pT2_uid165_invPolyEval(BITSELECT,177)@9 - assign osig_uid178_pT2_uid165_invPolyEval_b = prodXY_uid177_pT2_uid165_invPolyEval_cma_q[37:13]; + // osig_uid144_pT2_uid131_invPolyEval(BITSELECT,143)@9 + assign osig_uid144_pT2_uid131_invPolyEval_b = prodXY_uid143_pT2_uid131_invPolyEval_cma_q[36:13]; - // highBBits_uid167_invPolyEval(BITSELECT,166)@9 - assign highBBits_uid167_invPolyEval_b = osig_uid178_pT2_uid165_invPolyEval_b[24:2]; + // highBBits_uid133_invPolyEval(BITSELECT,132)@9 + assign highBBits_uid133_invPolyEval_b = osig_uid144_pT2_uid131_invPolyEval_b[23:2]; - // redist15_yAddr_uid51_fpDivTest_b_7(DELAY,201) + // redist9_yAddr_uid51_fpDivTest_b_7(DELAY,161) dspba_delay_ver #( .width(9), .depth(4), .reset_kind("ASYNC") ) - redist15_yAddr_uid51_fpDivTest_b_7 ( .xin(redist14_yAddr_uid51_fpDivTest_b_3_q), .xout(redist15_yAddr_uid51_fpDivTest_b_7_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + redist9_yAddr_uid51_fpDivTest_b_7 ( .xin(redist8_yAddr_uid51_fpDivTest_b_3_q), .xout(redist9_yAddr_uid51_fpDivTest_b_7_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - // memoryC0_uid146_invTables_lutmem(DUALMEM,179)@7 + 2 + // memoryC0_uid112_invTables_lutmem(DUALMEM,145)@7 + 2 // in j@20000000 - assign memoryC0_uid146_invTables_lutmem_aa = redist15_yAddr_uid51_fpDivTest_b_7_q; - assign memoryC0_uid146_invTables_lutmem_reset0 = areset; + assign memoryC0_uid112_invTables_lutmem_aa = redist9_yAddr_uid51_fpDivTest_b_7_q; + assign memoryC0_uid112_invTables_lutmem_reset0 = areset; altera_syncram #( .ram_block_type("M20K"), .operation_mode("ROM"), - .width_a(32), + .width_a(31), .widthad_a(9), .numwords_a(512), .lpm_type("altera_syncram"), @@ -1771,15 +1060,15 @@ module acl_fdiv ( .outdata_aclr_a("CLEAR0"), .clock_enable_input_a("NORMAL"), .power_up_uninitialized("FALSE"), - .init_file("acl_fdiv_memoryC0_uid146_invTables_lutmem.hex"), + .init_file("acl_fdiv_memoryC0_uid112_invTables_lutmem.hex"), .init_file_layout("PORT_A"), .intended_device_family("Arria 10") - ) memoryC0_uid146_invTables_lutmem_dmem ( + ) memoryC0_uid112_invTables_lutmem_dmem ( .clocken0(en[0]), - .aclr0(memoryC0_uid146_invTables_lutmem_reset0), + .aclr0(memoryC0_uid112_invTables_lutmem_reset0), .clock0(clk), - .address_a(memoryC0_uid146_invTables_lutmem_aa), - .q_a(memoryC0_uid146_invTables_lutmem_ir), + .address_a(memoryC0_uid112_invTables_lutmem_aa), + .q_a(memoryC0_uid112_invTables_lutmem_ir), .wren_a(), .wren_b(), .rden_a(), @@ -1804,52 +1093,56 @@ module acl_fdiv ( .q_b(), .eccstatus() ); - assign memoryC0_uid146_invTables_lutmem_r = memoryC0_uid146_invTables_lutmem_ir[31:0]; + assign memoryC0_uid112_invTables_lutmem_r = memoryC0_uid112_invTables_lutmem_ir[30:0]; - // s2sumAHighB_uid168_invPolyEval(ADD,167)@9 - assign s2sumAHighB_uid168_invPolyEval_a = {{1{memoryC0_uid146_invTables_lutmem_r[31]}}, memoryC0_uid146_invTables_lutmem_r}; - assign s2sumAHighB_uid168_invPolyEval_b = {{10{highBBits_uid167_invPolyEval_b[22]}}, highBBits_uid167_invPolyEval_b}; - assign s2sumAHighB_uid168_invPolyEval_o = $signed(s2sumAHighB_uid168_invPolyEval_a) + $signed(s2sumAHighB_uid168_invPolyEval_b); - assign s2sumAHighB_uid168_invPolyEval_q = s2sumAHighB_uid168_invPolyEval_o[32:0]; + // s2sumAHighB_uid134_invPolyEval(ADD,133)@9 + assign s2sumAHighB_uid134_invPolyEval_a = {{1{memoryC0_uid112_invTables_lutmem_r[30]}}, memoryC0_uid112_invTables_lutmem_r}; + assign s2sumAHighB_uid134_invPolyEval_b = {{10{highBBits_uid133_invPolyEval_b[21]}}, highBBits_uid133_invPolyEval_b}; + assign s2sumAHighB_uid134_invPolyEval_o = $signed(s2sumAHighB_uid134_invPolyEval_a) + $signed(s2sumAHighB_uid134_invPolyEval_b); + assign s2sumAHighB_uid134_invPolyEval_q = s2sumAHighB_uid134_invPolyEval_o[31:0]; - // lowRangeB_uid166_invPolyEval(BITSELECT,165)@9 - assign lowRangeB_uid166_invPolyEval_in = osig_uid178_pT2_uid165_invPolyEval_b[1:0]; - assign lowRangeB_uid166_invPolyEval_b = lowRangeB_uid166_invPolyEval_in[1:0]; + // lowRangeB_uid132_invPolyEval(BITSELECT,131)@9 + assign lowRangeB_uid132_invPolyEval_in = osig_uid144_pT2_uid131_invPolyEval_b[1:0]; + assign lowRangeB_uid132_invPolyEval_b = lowRangeB_uid132_invPolyEval_in[1:0]; - // s2_uid169_invPolyEval(BITJOIN,168)@9 - assign s2_uid169_invPolyEval_q = {s2sumAHighB_uid168_invPolyEval_q, lowRangeB_uid166_invPolyEval_b}; + // s2_uid135_invPolyEval(BITJOIN,134)@9 + assign s2_uid135_invPolyEval_q = {s2sumAHighB_uid134_invPolyEval_q, lowRangeB_uid132_invPolyEval_b}; - // invY_uid54_fpDivTest(BITSELECT,53)@9 - assign invY_uid54_fpDivTest_in = s2_uid169_invPolyEval_q[31:0]; - assign invY_uid54_fpDivTest_b = invY_uid54_fpDivTest_in[31:5]; + // invY_uid54_fpDivTest_merged_bit_select(BITSELECT,151)@9 + assign invY_uid54_fpDivTest_merged_bit_select_in = s2_uid135_invPolyEval_q[31:0]; + assign invY_uid54_fpDivTest_merged_bit_select_b = invY_uid54_fpDivTest_merged_bit_select_in[30:5]; + assign invY_uid54_fpDivTest_merged_bit_select_c = invY_uid54_fpDivTest_merged_bit_select_in[31:31]; - // redist11_invY_uid54_fpDivTest_b_1(DELAY,197) - dspba_delay_ver #( .width(27), .depth(1), .reset_kind("ASYNC") ) - redist11_invY_uid54_fpDivTest_b_1 ( .xin(invY_uid54_fpDivTest_b), .xout(redist11_invY_uid54_fpDivTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + // redist0_invY_uid54_fpDivTest_merged_bit_select_b_1(DELAY,152) + dspba_delay_ver #( .width(26), .depth(1), .reset_kind("ASYNC") ) + redist0_invY_uid54_fpDivTest_merged_bit_select_b_1 ( .xin(invY_uid54_fpDivTest_merged_bit_select_b), .xout(redist0_invY_uid54_fpDivTest_merged_bit_select_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - // prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma(CHAINMULTADD,183)@10 + 3 - assign prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_reset = areset; - assign prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_ena0 = en[0]; - assign prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_ena1 = prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_ena0; - assign prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_ena2 = prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_ena0; - assign prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_p[0] = prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_a1[0] * prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_c1[0]; - assign prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_u[0] = prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_p[0][50:0]; - assign prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_w[0] = prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_u[0]; - assign prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_x[0] = prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_w[0]; - assign prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_y[0] = prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_x[0]; + // GND(CONSTANT,0) + assign GND_q = 1'b0; + + // prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma(CHAINMULTADD,148)@10 + 3 + assign prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_reset = areset; + assign prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_ena0 = en[0]; + assign prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_ena1 = prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_ena0; + assign prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_ena2 = prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_ena0; + assign prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_p[0] = prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_a1[0] * prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_c1[0]; + assign prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_u[0] = prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_p[0][49:0]; + assign prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_w[0] = prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_u[0]; + assign prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_x[0] = prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_w[0]; + assign prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_y[0] = prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_x[0]; always @ (posedge clk or posedge areset) begin if (areset) begin - prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_a0 <= '{default: '0}; - prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_c0 <= '{default: '0}; + prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_a0 <= '{default: '0}; + prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_c0 <= '{default: '0}; end else begin - if (prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_ena0 == 1'b1) + if (prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_ena0 == 1'b1) begin - prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_a0[0] <= redist11_invY_uid54_fpDivTest_b_1_q; - prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_c0[0] <= lOAdded_uid57_fpDivTest_q; + prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_a0[0] <= redist0_invY_uid54_fpDivTest_merged_bit_select_b_1_q; + prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_c0[0] <= lOAdded_uid58_fpDivTest_q; end end end @@ -1857,15 +1150,15 @@ module acl_fdiv ( begin if (areset) begin - prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_a1 <= '{default: '0}; - prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_c1 <= '{default: '0}; + prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_a1 <= '{default: '0}; + prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_c1 <= '{default: '0}; end else begin - if (prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_ena2 == 1'b1) + if (prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_ena2 == 1'b1) begin - prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_a1 <= prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_a0; - prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_c1 <= prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_c0; + prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_a1 <= prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_a0; + prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_c1 <= prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_c0; end end end @@ -1873,58 +1166,152 @@ module acl_fdiv ( begin if (areset) begin - prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_s <= '{default: '0}; + prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_s <= '{default: '0}; end else begin - if (prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_ena1 == 1'b1) + if (prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_ena1 == 1'b1) begin - prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_s[0] <= prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_y[0]; + prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_s[0] <= prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_y[0]; end end end - dspba_delay_ver #( .width(51), .depth(0), .reset_kind("ASYNC") ) - prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_delay ( .xin(prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_s[0][50:0]), .xout(prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_qq), .ena(en[0]), .clk(clk), .aclr(areset) ); - assign prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_q = prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_qq[50:0]; + dspba_delay_ver #( .width(50), .depth(0), .reset_kind("ASYNC") ) + prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_delay ( .xin(prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_s[0][49:0]), .xout(prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_qq), .ena(en[0]), .clk(clk), .aclr(areset) ); + assign prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_q = prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_qq[49:0]; - // osig_uid172_divValPreNorm_uid59_fpDivTest(BITSELECT,171)@13 - assign osig_uid172_divValPreNorm_uid59_fpDivTest_b = prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_q[50:23]; + // osig_uid138_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,137)@13 + assign osig_uid138_prodDivPreNormProd_uid60_fpDivTest_b = prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_q[49:24]; - // updatedY_uid16_fpDivTest(BITJOIN,15)@12 + // updatedY_uid16_fpDivTest(BITJOIN,15)@0 assign updatedY_uid16_fpDivTest_q = {GND_q, paddingY_uid15_fpDivTest_q}; - // fracYZero_uid15_fpDivTest(LOGICAL,16)@12 + 1 - assign fracYZero_uid15_fpDivTest_a = {1'b0, redist17_fracY_uid13_fpDivTest_b_12_outputreg_q}; + // fracYZero_uid15_fpDivTest(LOGICAL,16)@0 + 1 + assign fracYZero_uid15_fpDivTest_a = {1'b0, fracY_uid13_fpDivTest_b}; assign fracYZero_uid15_fpDivTest_qi = fracYZero_uid15_fpDivTest_a == updatedY_uid16_fpDivTest_q ? 1'b1 : 1'b0; dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) fracYZero_uid15_fpDivTest_delay ( .xin(fracYZero_uid15_fpDivTest_qi), .xout(fracYZero_uid15_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - // divValPreNormYPow2Exc_uid63_fpDivTest(MUX,62)@13 - assign divValPreNormYPow2Exc_uid63_fpDivTest_s = fracYZero_uid15_fpDivTest_q; - always @(divValPreNormYPow2Exc_uid63_fpDivTest_s or en or osig_uid172_divValPreNorm_uid59_fpDivTest_b or oFracXZ4_uid61_fpDivTest_q) + // redist18_fracYZero_uid15_fpDivTest_q_9(DELAY,170) + dspba_delay_ver #( .width(1), .depth(8), .reset_kind("ASYNC") ) + redist18_fracYZero_uid15_fpDivTest_q_9 ( .xin(fracYZero_uid15_fpDivTest_q), .xout(redist18_fracYZero_uid15_fpDivTest_q_9_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // fracYPostZ_uid56_fpDivTest(LOGICAL,55)@9 + 1 + assign fracYPostZ_uid56_fpDivTest_qi = redist18_fracYZero_uid15_fpDivTest_q_9_q | invY_uid54_fpDivTest_merged_bit_select_c; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + fracYPostZ_uid56_fpDivTest_delay ( .xin(fracYPostZ_uid56_fpDivTest_qi), .xout(fracYPostZ_uid56_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist5_fracYPostZ_uid56_fpDivTest_q_4(DELAY,157) + dspba_delay_ver #( .width(1), .depth(3), .reset_kind("ASYNC") ) + redist5_fracYPostZ_uid56_fpDivTest_q_4 ( .xin(fracYPostZ_uid56_fpDivTest_q), .xout(redist5_fracYPostZ_uid56_fpDivTest_q_4_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // divValPreNormTrunc_uid66_fpDivTest(MUX,65)@13 + assign divValPreNormTrunc_uid66_fpDivTest_s = redist5_fracYPostZ_uid56_fpDivTest_q_4_q; + always @(divValPreNormTrunc_uid66_fpDivTest_s or en or osig_uid138_prodDivPreNormProd_uid60_fpDivTest_b or oFracXSE_mergedSignalTM_uid63_fpDivTest_q) begin - unique case (divValPreNormYPow2Exc_uid63_fpDivTest_s) - 1'b0 : divValPreNormYPow2Exc_uid63_fpDivTest_q = osig_uid172_divValPreNorm_uid59_fpDivTest_b; - 1'b1 : divValPreNormYPow2Exc_uid63_fpDivTest_q = oFracXZ4_uid61_fpDivTest_q; - default : divValPreNormYPow2Exc_uid63_fpDivTest_q = 28'b0; + unique case (divValPreNormTrunc_uid66_fpDivTest_s) + 1'b0 : divValPreNormTrunc_uid66_fpDivTest_q = osig_uid138_prodDivPreNormProd_uid60_fpDivTest_b; + 1'b1 : divValPreNormTrunc_uid66_fpDivTest_q = oFracXSE_mergedSignalTM_uid63_fpDivTest_q; + default : divValPreNormTrunc_uid66_fpDivTest_q = 26'b0; endcase end - // norm_uid64_fpDivTest(BITSELECT,63)@13 - assign norm_uid64_fpDivTest_b = divValPreNormYPow2Exc_uid63_fpDivTest_q[27:27]; + // norm_uid67_fpDivTest(BITSELECT,66)@13 + assign norm_uid67_fpDivTest_b = divValPreNormTrunc_uid66_fpDivTest_q[25:25]; - // zeroPaddingInAddition_uid74_fpDivTest(CONSTANT,73) - assign zeroPaddingInAddition_uid74_fpDivTest_q = 24'b000000000000000000000000; - - // expFracPostRnd_uid75_fpDivTest(BITJOIN,74)@13 - assign expFracPostRnd_uid75_fpDivTest_q = {norm_uid64_fpDivTest_b, zeroPaddingInAddition_uid74_fpDivTest_q, VCC_q}; + // rndOp_uid75_fpDivTest(BITJOIN,74)@13 + assign rndOp_uid75_fpDivTest_q = {norm_uid67_fpDivTest_b, paddingY_uid15_fpDivTest_q, VCC_q}; // cstBiasM1_uid6_fpDivTest(CONSTANT,5) assign cstBiasM1_uid6_fpDivTest_q = 8'b01111110; - // expXmY_uid47_fpDivTest(SUB,46)@12 + 1 - assign expXmY_uid47_fpDivTest_a = {1'b0, redist24_expX_uid9_fpDivTest_b_12_outputreg_q}; - assign expXmY_uid47_fpDivTest_b = {1'b0, redist19_expY_uid12_fpDivTest_b_12_outputreg_q}; + // redist10_expXmY_uid47_fpDivTest_q_13_notEnable(LOGICAL,191) + assign redist10_expXmY_uid47_fpDivTest_q_13_notEnable_q = ~ (en); + + // redist10_expXmY_uid47_fpDivTest_q_13_nor(LOGICAL,192) + assign redist10_expXmY_uid47_fpDivTest_q_13_nor_q = ~ (redist10_expXmY_uid47_fpDivTest_q_13_notEnable_q | redist10_expXmY_uid47_fpDivTest_q_13_sticky_ena_q); + + // redist10_expXmY_uid47_fpDivTest_q_13_mem_last(CONSTANT,188) + assign redist10_expXmY_uid47_fpDivTest_q_13_mem_last_q = 5'b01000; + + // redist10_expXmY_uid47_fpDivTest_q_13_cmp(LOGICAL,189) + assign redist10_expXmY_uid47_fpDivTest_q_13_cmp_b = {1'b0, redist10_expXmY_uid47_fpDivTest_q_13_rdmux_q}; + assign redist10_expXmY_uid47_fpDivTest_q_13_cmp_q = redist10_expXmY_uid47_fpDivTest_q_13_mem_last_q == redist10_expXmY_uid47_fpDivTest_q_13_cmp_b ? 1'b1 : 1'b0; + + // redist10_expXmY_uid47_fpDivTest_q_13_cmpReg(REG,190) + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist10_expXmY_uid47_fpDivTest_q_13_cmpReg_q <= 1'b0; + end + else if (en == 1'b1) + begin + redist10_expXmY_uid47_fpDivTest_q_13_cmpReg_q <= redist10_expXmY_uid47_fpDivTest_q_13_cmp_q; + end + end + + // redist10_expXmY_uid47_fpDivTest_q_13_sticky_ena(REG,193) + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist10_expXmY_uid47_fpDivTest_q_13_sticky_ena_q <= 1'b0; + end + else if (redist10_expXmY_uid47_fpDivTest_q_13_nor_q == 1'b1) + begin + redist10_expXmY_uid47_fpDivTest_q_13_sticky_ena_q <= redist10_expXmY_uid47_fpDivTest_q_13_cmpReg_q; + end + end + + // redist10_expXmY_uid47_fpDivTest_q_13_enaAnd(LOGICAL,194) + assign redist10_expXmY_uid47_fpDivTest_q_13_enaAnd_q = redist10_expXmY_uid47_fpDivTest_q_13_sticky_ena_q & en; + + // redist10_expXmY_uid47_fpDivTest_q_13_rdcnt(COUNTER,185) + // low=0, high=9, step=1, init=0 + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist10_expXmY_uid47_fpDivTest_q_13_rdcnt_i <= 4'd0; + redist10_expXmY_uid47_fpDivTest_q_13_rdcnt_eq <= 1'b0; + end + else if (en == 1'b1) + begin + if (redist10_expXmY_uid47_fpDivTest_q_13_rdcnt_i == 4'd8) + begin + redist10_expXmY_uid47_fpDivTest_q_13_rdcnt_eq <= 1'b1; + end + else + begin + redist10_expXmY_uid47_fpDivTest_q_13_rdcnt_eq <= 1'b0; + end + if (redist10_expXmY_uid47_fpDivTest_q_13_rdcnt_eq == 1'b1) + begin + redist10_expXmY_uid47_fpDivTest_q_13_rdcnt_i <= $unsigned(redist10_expXmY_uid47_fpDivTest_q_13_rdcnt_i) + $unsigned(4'd7); + end + else + begin + redist10_expXmY_uid47_fpDivTest_q_13_rdcnt_i <= $unsigned(redist10_expXmY_uid47_fpDivTest_q_13_rdcnt_i) + $unsigned(4'd1); + end + end + end + assign redist10_expXmY_uid47_fpDivTest_q_13_rdcnt_q = redist10_expXmY_uid47_fpDivTest_q_13_rdcnt_i[3:0]; + + // redist10_expXmY_uid47_fpDivTest_q_13_rdmux(MUX,186) + assign redist10_expXmY_uid47_fpDivTest_q_13_rdmux_s = en; + always @(redist10_expXmY_uid47_fpDivTest_q_13_rdmux_s or redist10_expXmY_uid47_fpDivTest_q_13_wraddr_q or redist10_expXmY_uid47_fpDivTest_q_13_rdcnt_q) + begin + unique case (redist10_expXmY_uid47_fpDivTest_q_13_rdmux_s) + 1'b0 : redist10_expXmY_uid47_fpDivTest_q_13_rdmux_q = redist10_expXmY_uid47_fpDivTest_q_13_wraddr_q; + 1'b1 : redist10_expXmY_uid47_fpDivTest_q_13_rdmux_q = redist10_expXmY_uid47_fpDivTest_q_13_rdcnt_q; + default : redist10_expXmY_uid47_fpDivTest_q_13_rdmux_q = 4'b0; + endcase + end + + // expXmY_uid47_fpDivTest(SUB,46)@0 + 1 + assign expXmY_uid47_fpDivTest_a = {1'b0, expX_uid9_fpDivTest_b}; + assign expXmY_uid47_fpDivTest_b = {1'b0, expY_uid12_fpDivTest_b}; always @ (posedge clk or posedge areset) begin if (areset) @@ -1938,695 +1325,268 @@ module acl_fdiv ( end assign expXmY_uid47_fpDivTest_q = expXmY_uid47_fpDivTest_o[8:0]; - // expR_uid48_fpDivTest(ADD,47)@13 - assign expR_uid48_fpDivTest_a = {{2{expXmY_uid47_fpDivTest_q[8]}}, expXmY_uid47_fpDivTest_q}; - assign expR_uid48_fpDivTest_b = {3'b000, cstBiasM1_uid6_fpDivTest_q}; - assign expR_uid48_fpDivTest_o = $signed(expR_uid48_fpDivTest_a) + $signed(expR_uid48_fpDivTest_b); - assign expR_uid48_fpDivTest_q = expR_uid48_fpDivTest_o[9:0]; - - // divValPreNormHigh_uid65_fpDivTest(BITSELECT,64)@13 - assign divValPreNormHigh_uid65_fpDivTest_in = divValPreNormYPow2Exc_uid63_fpDivTest_q[26:0]; - assign divValPreNormHigh_uid65_fpDivTest_b = divValPreNormHigh_uid65_fpDivTest_in[26:2]; - - // divValPreNormLow_uid66_fpDivTest(BITSELECT,65)@13 - assign divValPreNormLow_uid66_fpDivTest_in = divValPreNormYPow2Exc_uid63_fpDivTest_q[25:0]; - assign divValPreNormLow_uid66_fpDivTest_b = divValPreNormLow_uid66_fpDivTest_in[25:1]; - - // normFracRnd_uid67_fpDivTest(MUX,66)@13 - assign normFracRnd_uid67_fpDivTest_s = norm_uid64_fpDivTest_b; - always @(normFracRnd_uid67_fpDivTest_s or en or divValPreNormLow_uid66_fpDivTest_b or divValPreNormHigh_uid65_fpDivTest_b) - begin - unique case (normFracRnd_uid67_fpDivTest_s) - 1'b0 : normFracRnd_uid67_fpDivTest_q = divValPreNormLow_uid66_fpDivTest_b; - 1'b1 : normFracRnd_uid67_fpDivTest_q = divValPreNormHigh_uid65_fpDivTest_b; - default : normFracRnd_uid67_fpDivTest_q = 25'b0; - endcase - end - - // expFracRnd_uid68_fpDivTest(BITJOIN,67)@13 - assign expFracRnd_uid68_fpDivTest_q = {expR_uid48_fpDivTest_q, normFracRnd_uid67_fpDivTest_q}; - - // expFracPostRnd_uid76_fpDivTest(ADD,75)@13 + 1 - assign expFracPostRnd_uid76_fpDivTest_a = {{2{expFracRnd_uid68_fpDivTest_q[34]}}, expFracRnd_uid68_fpDivTest_q}; - assign expFracPostRnd_uid76_fpDivTest_b = {11'b00000000000, expFracPostRnd_uid75_fpDivTest_q}; + // redist10_expXmY_uid47_fpDivTest_q_13_wraddr(REG,187) always @ (posedge clk or posedge areset) begin if (areset) begin - expFracPostRnd_uid76_fpDivTest_o <= 37'b0; + redist10_expXmY_uid47_fpDivTest_q_13_wraddr_q <= 4'b1001; + end + else + begin + redist10_expXmY_uid47_fpDivTest_q_13_wraddr_q <= redist10_expXmY_uid47_fpDivTest_q_13_rdmux_q; + end + end + + // redist10_expXmY_uid47_fpDivTest_q_13_mem(DUALMEM,184) + assign redist10_expXmY_uid47_fpDivTest_q_13_mem_ia = expXmY_uid47_fpDivTest_q; + assign redist10_expXmY_uid47_fpDivTest_q_13_mem_aa = redist10_expXmY_uid47_fpDivTest_q_13_wraddr_q; + assign redist10_expXmY_uid47_fpDivTest_q_13_mem_ab = redist10_expXmY_uid47_fpDivTest_q_13_rdmux_q; + assign redist10_expXmY_uid47_fpDivTest_q_13_mem_reset0 = areset; + altera_syncram #( + .ram_block_type("MLAB"), + .operation_mode("DUAL_PORT"), + .width_a(9), + .widthad_a(4), + .numwords_a(10), + .width_b(9), + .widthad_b(4), + .numwords_b(10), + .lpm_type("altera_syncram"), + .width_byteena_a(1), + .address_reg_b("CLOCK0"), + .indata_reg_b("CLOCK0"), + .rdcontrol_reg_b("CLOCK0"), + .byteena_reg_b("CLOCK0"), + .outdata_reg_b("CLOCK1"), + .outdata_aclr_b("CLEAR1"), + .clock_enable_input_a("NORMAL"), + .clock_enable_input_b("NORMAL"), + .clock_enable_output_b("NORMAL"), + .read_during_write_mode_mixed_ports("DONT_CARE"), + .power_up_uninitialized("TRUE"), + .intended_device_family("Arria 10") + ) redist10_expXmY_uid47_fpDivTest_q_13_mem_dmem ( + .clocken1(redist10_expXmY_uid47_fpDivTest_q_13_enaAnd_q[0]), + .clocken0(VCC_q[0]), + .clock0(clk), + .aclr1(redist10_expXmY_uid47_fpDivTest_q_13_mem_reset0), + .clock1(clk), + .address_a(redist10_expXmY_uid47_fpDivTest_q_13_mem_aa), + .data_a(redist10_expXmY_uid47_fpDivTest_q_13_mem_ia), + .wren_a(en[0]), + .address_b(redist10_expXmY_uid47_fpDivTest_q_13_mem_ab), + .q_b(redist10_expXmY_uid47_fpDivTest_q_13_mem_iq), + .wren_b(), + .rden_a(), + .rden_b(), + .data_b(), + .clocken2(), + .clocken3(), + .aclr0(), + .addressstall_a(), + .addressstall_b(), + .byteena_a(), + .byteena_b(), + .eccencbypass(), + .eccencparity(), + .sclr(), + .address2_a(), + .address2_b(), + .q_a(), + .eccstatus() + ); + assign redist10_expXmY_uid47_fpDivTest_q_13_mem_q = redist10_expXmY_uid47_fpDivTest_q_13_mem_iq[8:0]; + + // redist10_expXmY_uid47_fpDivTest_q_13_outputreg(DELAY,183) + dspba_delay_ver #( .width(9), .depth(1), .reset_kind("ASYNC") ) + redist10_expXmY_uid47_fpDivTest_q_13_outputreg ( .xin(redist10_expXmY_uid47_fpDivTest_q_13_mem_q), .xout(redist10_expXmY_uid47_fpDivTest_q_13_outputreg_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // expR_uid48_fpDivTest(ADD,47)@13 + assign expR_uid48_fpDivTest_a = {{2{redist10_expXmY_uid47_fpDivTest_q_13_outputreg_q[8]}}, redist10_expXmY_uid47_fpDivTest_q_13_outputreg_q}; + assign expR_uid48_fpDivTest_b = {3'b000, cstBiasM1_uid6_fpDivTest_q}; + assign expR_uid48_fpDivTest_o = $signed(expR_uid48_fpDivTest_a) + $signed(expR_uid48_fpDivTest_b); + assign expR_uid48_fpDivTest_q = expR_uid48_fpDivTest_o[9:0]; + + // divValPreNormHigh_uid68_fpDivTest(BITSELECT,67)@13 + assign divValPreNormHigh_uid68_fpDivTest_in = divValPreNormTrunc_uid66_fpDivTest_q[24:0]; + assign divValPreNormHigh_uid68_fpDivTest_b = divValPreNormHigh_uid68_fpDivTest_in[24:1]; + + // divValPreNormLow_uid69_fpDivTest(BITSELECT,68)@13 + assign divValPreNormLow_uid69_fpDivTest_in = divValPreNormTrunc_uid66_fpDivTest_q[23:0]; + assign divValPreNormLow_uid69_fpDivTest_b = divValPreNormLow_uid69_fpDivTest_in[23:0]; + + // normFracRnd_uid70_fpDivTest(MUX,69)@13 + assign normFracRnd_uid70_fpDivTest_s = norm_uid67_fpDivTest_b; + always @(normFracRnd_uid70_fpDivTest_s or en or divValPreNormLow_uid69_fpDivTest_b or divValPreNormHigh_uid68_fpDivTest_b) + begin + unique case (normFracRnd_uid70_fpDivTest_s) + 1'b0 : normFracRnd_uid70_fpDivTest_q = divValPreNormLow_uid69_fpDivTest_b; + 1'b1 : normFracRnd_uid70_fpDivTest_q = divValPreNormHigh_uid68_fpDivTest_b; + default : normFracRnd_uid70_fpDivTest_q = 24'b0; + endcase + end + + // expFracRnd_uid71_fpDivTest(BITJOIN,70)@13 + assign expFracRnd_uid71_fpDivTest_q = {expR_uid48_fpDivTest_q, normFracRnd_uid70_fpDivTest_q}; + + // expFracPostRnd_uid76_fpDivTest(ADD,75)@13 + 1 + assign expFracPostRnd_uid76_fpDivTest_a = {{2{expFracRnd_uid71_fpDivTest_q[33]}}, expFracRnd_uid71_fpDivTest_q}; + assign expFracPostRnd_uid76_fpDivTest_b = {11'b00000000000, rndOp_uid75_fpDivTest_q}; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + expFracPostRnd_uid76_fpDivTest_o <= 36'b0; end else if (en == 1'b1) begin expFracPostRnd_uid76_fpDivTest_o <= $signed(expFracPostRnd_uid76_fpDivTest_a) + $signed(expFracPostRnd_uid76_fpDivTest_b); end end - assign expFracPostRnd_uid76_fpDivTest_q = expFracPostRnd_uid76_fpDivTest_o[35:0]; + assign expFracPostRnd_uid76_fpDivTest_q = expFracPostRnd_uid76_fpDivTest_o[34:0]; - // fracPostRndF_uid79_fpDivTest(BITSELECT,78)@14 - assign fracPostRndF_uid79_fpDivTest_in = expFracPostRnd_uid76_fpDivTest_q[24:0]; - assign fracPostRndF_uid79_fpDivTest_b = fracPostRndF_uid79_fpDivTest_in[24:1]; + // excRPreExc_uid79_fpDivTest(BITSELECT,78)@14 + assign excRPreExc_uid79_fpDivTest_in = expFracPostRnd_uid76_fpDivTest_q[31:0]; + assign excRPreExc_uid79_fpDivTest_b = excRPreExc_uid79_fpDivTest_in[31:24]; - // invYO_uid55_fpDivTest(BITSELECT,54)@9 - assign invYO_uid55_fpDivTest_in = s2_uid169_invPolyEval_q[32:0]; - assign invYO_uid55_fpDivTest_b = invYO_uid55_fpDivTest_in[32:32]; - - // redist10_invYO_uid55_fpDivTest_b_5(DELAY,196) - dspba_delay_ver #( .width(1), .depth(5), .reset_kind("ASYNC") ) - redist10_invYO_uid55_fpDivTest_b_5 ( .xin(invYO_uid55_fpDivTest_b), .xout(redist10_invYO_uid55_fpDivTest_b_5_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // fracPostRndF_uid80_fpDivTest(MUX,79)@14 - assign fracPostRndF_uid80_fpDivTest_s = redist10_invYO_uid55_fpDivTest_b_5_q; - always @(fracPostRndF_uid80_fpDivTest_s or en or fracPostRndF_uid79_fpDivTest_b or fracXExt_uid77_fpDivTest_q) - begin - unique case (fracPostRndF_uid80_fpDivTest_s) - 1'b0 : fracPostRndF_uid80_fpDivTest_q = fracPostRndF_uid79_fpDivTest_b; - 1'b1 : fracPostRndF_uid80_fpDivTest_q = fracXExt_uid77_fpDivTest_q; - default : fracPostRndF_uid80_fpDivTest_q = 24'b0; - endcase - end - - // redist8_fracPostRndF_uid80_fpDivTest_q_5_wraddr(REG,229) - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - redist8_fracPostRndF_uid80_fpDivTest_q_5_wraddr_q <= 2'b10; - end - else - begin - redist8_fracPostRndF_uid80_fpDivTest_q_5_wraddr_q <= redist8_fracPostRndF_uid80_fpDivTest_q_5_rdmux_q; - end - end - - // redist8_fracPostRndF_uid80_fpDivTest_q_5_mem(DUALMEM,226) - assign redist8_fracPostRndF_uid80_fpDivTest_q_5_mem_ia = fracPostRndF_uid80_fpDivTest_q; - assign redist8_fracPostRndF_uid80_fpDivTest_q_5_mem_aa = redist8_fracPostRndF_uid80_fpDivTest_q_5_wraddr_q; - assign redist8_fracPostRndF_uid80_fpDivTest_q_5_mem_ab = redist8_fracPostRndF_uid80_fpDivTest_q_5_rdmux_q; - assign redist8_fracPostRndF_uid80_fpDivTest_q_5_mem_reset0 = areset; - altera_syncram #( - .ram_block_type("MLAB"), - .operation_mode("DUAL_PORT"), - .width_a(24), - .widthad_a(2), - .numwords_a(3), - .width_b(24), - .widthad_b(2), - .numwords_b(3), - .lpm_type("altera_syncram"), - .width_byteena_a(1), - .address_reg_b("CLOCK0"), - .indata_reg_b("CLOCK0"), - .rdcontrol_reg_b("CLOCK0"), - .byteena_reg_b("CLOCK0"), - .outdata_reg_b("CLOCK1"), - .outdata_aclr_b("CLEAR1"), - .clock_enable_input_a("NORMAL"), - .clock_enable_input_b("NORMAL"), - .clock_enable_output_b("NORMAL"), - .read_during_write_mode_mixed_ports("DONT_CARE"), - .power_up_uninitialized("TRUE"), - .intended_device_family("Arria 10") - ) redist8_fracPostRndF_uid80_fpDivTest_q_5_mem_dmem ( - .clocken1(redist8_fracPostRndF_uid80_fpDivTest_q_5_enaAnd_q[0]), - .clocken0(VCC_q[0]), - .clock0(clk), - .aclr1(redist8_fracPostRndF_uid80_fpDivTest_q_5_mem_reset0), - .clock1(clk), - .address_a(redist8_fracPostRndF_uid80_fpDivTest_q_5_mem_aa), - .data_a(redist8_fracPostRndF_uid80_fpDivTest_q_5_mem_ia), - .wren_a(en[0]), - .address_b(redist8_fracPostRndF_uid80_fpDivTest_q_5_mem_ab), - .q_b(redist8_fracPostRndF_uid80_fpDivTest_q_5_mem_iq), - .wren_b(), - .rden_a(), - .rden_b(), - .data_b(), - .clocken2(), - .clocken3(), - .aclr0(), - .addressstall_a(), - .addressstall_b(), - .byteena_a(), - .byteena_b(), - .eccencbypass(), - .eccencparity(), - .sclr(), - .address2_a(), - .address2_b(), - .q_a(), - .eccstatus() - ); - assign redist8_fracPostRndF_uid80_fpDivTest_q_5_mem_q = redist8_fracPostRndF_uid80_fpDivTest_q_5_mem_iq[23:0]; - - // redist8_fracPostRndF_uid80_fpDivTest_q_5_outputreg(DELAY,225) - dspba_delay_ver #( .width(24), .depth(1), .reset_kind("ASYNC") ) - redist8_fracPostRndF_uid80_fpDivTest_q_5_outputreg ( .xin(redist8_fracPostRndF_uid80_fpDivTest_q_5_mem_q), .xout(redist8_fracPostRndF_uid80_fpDivTest_q_5_outputreg_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // betweenFPwF_uid102_fpDivTest(BITSELECT,101)@19 - assign betweenFPwF_uid102_fpDivTest_in = redist8_fracPostRndF_uid80_fpDivTest_q_5_outputreg_q[0:0]; - assign betweenFPwF_uid102_fpDivTest_b = betweenFPwF_uid102_fpDivTest_in[0:0]; - - // redist26_expX_uid9_fpDivTest_b_18(DELAY,212) - dspba_delay_ver #( .width(8), .depth(4), .reset_kind("ASYNC") ) - redist26_expX_uid9_fpDivTest_b_18 ( .xin(redist25_expX_uid9_fpDivTest_b_14_q), .xout(redist26_expX_uid9_fpDivTest_b_18_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // redist23_fracX_uid10_fpDivTest_b_18_inputreg(DELAY,285) - dspba_delay_ver #( .width(23), .depth(1), .reset_kind("ASYNC") ) - redist23_fracX_uid10_fpDivTest_b_18_inputreg ( .xin(redist22_fracX_uid10_fpDivTest_b_14_q), .xout(redist23_fracX_uid10_fpDivTest_b_18_inputreg_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // redist23_fracX_uid10_fpDivTest_b_18(DELAY,209) - dspba_delay_ver #( .width(23), .depth(3), .reset_kind("ASYNC") ) - redist23_fracX_uid10_fpDivTest_b_18 ( .xin(redist23_fracX_uid10_fpDivTest_b_18_inputreg_q), .xout(redist23_fracX_uid10_fpDivTest_b_18_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // qDivProdLTX_opB_uid100_fpDivTest(BITJOIN,99)@18 - assign qDivProdLTX_opB_uid100_fpDivTest_q = {redist26_expX_uid9_fpDivTest_b_18_q, redist23_fracX_uid10_fpDivTest_b_18_q}; - - // lOAdded_uid87_fpDivTest(BITJOIN,86)@14 - assign lOAdded_uid87_fpDivTest_q = {VCC_q, redist18_fracY_uid13_fpDivTest_b_14_q}; - - // lOAdded_uid84_fpDivTest(BITJOIN,83)@14 - assign lOAdded_uid84_fpDivTest_q = {VCC_q, fracPostRndF_uid80_fpDivTest_q}; - - // qDivProd_uid89_fpDivTest_cma(CHAINMULTADD,182)@14 + 3 - assign qDivProd_uid89_fpDivTest_cma_reset = areset; - assign qDivProd_uid89_fpDivTest_cma_ena0 = en[0]; - assign qDivProd_uid89_fpDivTest_cma_ena1 = qDivProd_uid89_fpDivTest_cma_ena0; - assign qDivProd_uid89_fpDivTest_cma_ena2 = qDivProd_uid89_fpDivTest_cma_ena0; - assign qDivProd_uid89_fpDivTest_cma_p[0] = qDivProd_uid89_fpDivTest_cma_a1[0] * qDivProd_uid89_fpDivTest_cma_c1[0]; - assign qDivProd_uid89_fpDivTest_cma_u[0] = qDivProd_uid89_fpDivTest_cma_p[0][48:0]; - assign qDivProd_uid89_fpDivTest_cma_w[0] = qDivProd_uid89_fpDivTest_cma_u[0]; - assign qDivProd_uid89_fpDivTest_cma_x[0] = qDivProd_uid89_fpDivTest_cma_w[0]; - assign qDivProd_uid89_fpDivTest_cma_y[0] = qDivProd_uid89_fpDivTest_cma_x[0]; - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - qDivProd_uid89_fpDivTest_cma_a0 <= '{default: '0}; - qDivProd_uid89_fpDivTest_cma_c0 <= '{default: '0}; - end - else - begin - if (qDivProd_uid89_fpDivTest_cma_ena0 == 1'b1) - begin - qDivProd_uid89_fpDivTest_cma_a0[0] <= lOAdded_uid84_fpDivTest_q; - qDivProd_uid89_fpDivTest_cma_c0[0] <= lOAdded_uid87_fpDivTest_q; - end - end - end - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - qDivProd_uid89_fpDivTest_cma_a1 <= '{default: '0}; - qDivProd_uid89_fpDivTest_cma_c1 <= '{default: '0}; - end - else - begin - if (qDivProd_uid89_fpDivTest_cma_ena2 == 1'b1) - begin - qDivProd_uid89_fpDivTest_cma_a1 <= qDivProd_uid89_fpDivTest_cma_a0; - qDivProd_uid89_fpDivTest_cma_c1 <= qDivProd_uid89_fpDivTest_cma_c0; - end - end - end - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - qDivProd_uid89_fpDivTest_cma_s <= '{default: '0}; - end - else - begin - if (qDivProd_uid89_fpDivTest_cma_ena1 == 1'b1) - begin - qDivProd_uid89_fpDivTest_cma_s[0] <= qDivProd_uid89_fpDivTest_cma_y[0]; - end - end - end - dspba_delay_ver #( .width(49), .depth(0), .reset_kind("ASYNC") ) - qDivProd_uid89_fpDivTest_cma_delay ( .xin(qDivProd_uid89_fpDivTest_cma_s[0][48:0]), .xout(qDivProd_uid89_fpDivTest_cma_qq), .ena(en[0]), .clk(clk), .aclr(areset) ); - assign qDivProd_uid89_fpDivTest_cma_q = qDivProd_uid89_fpDivTest_cma_qq[48:0]; - - // qDivProdNorm_uid90_fpDivTest(BITSELECT,89)@17 - assign qDivProdNorm_uid90_fpDivTest_b = qDivProd_uid89_fpDivTest_cma_q[48:48]; - - // cstBias_uid7_fpDivTest(CONSTANT,6) - assign cstBias_uid7_fpDivTest_q = 8'b01111111; - - // qDivProdExp_opBs_uid95_fpDivTest(SUB,94)@17 + 1 - assign qDivProdExp_opBs_uid95_fpDivTest_a = {1'b0, cstBias_uid7_fpDivTest_q}; - assign qDivProdExp_opBs_uid95_fpDivTest_b = {8'b00000000, qDivProdNorm_uid90_fpDivTest_b}; - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - qDivProdExp_opBs_uid95_fpDivTest_o <= 9'b0; - end - else if (en == 1'b1) - begin - qDivProdExp_opBs_uid95_fpDivTest_o <= $unsigned(qDivProdExp_opBs_uid95_fpDivTest_a) - $unsigned(qDivProdExp_opBs_uid95_fpDivTest_b); - end - end - assign qDivProdExp_opBs_uid95_fpDivTest_q = qDivProdExp_opBs_uid95_fpDivTest_o[8:0]; - - // expPostRndFR_uid81_fpDivTest(BITSELECT,80)@14 - assign expPostRndFR_uid81_fpDivTest_in = expFracPostRnd_uid76_fpDivTest_q[32:0]; - assign expPostRndFR_uid81_fpDivTest_b = expPostRndFR_uid81_fpDivTest_in[32:25]; - - // expPostRndF_uid82_fpDivTest(MUX,81)@14 - assign expPostRndF_uid82_fpDivTest_s = redist10_invYO_uid55_fpDivTest_b_5_q; - always @(expPostRndF_uid82_fpDivTest_s or en or expPostRndFR_uid81_fpDivTest_b or redist25_expX_uid9_fpDivTest_b_14_q) - begin - unique case (expPostRndF_uid82_fpDivTest_s) - 1'b0 : expPostRndF_uid82_fpDivTest_q = expPostRndFR_uid81_fpDivTest_b; - 1'b1 : expPostRndF_uid82_fpDivTest_q = redist25_expX_uid9_fpDivTest_b_14_q; - default : expPostRndF_uid82_fpDivTest_q = 8'b0; - endcase - end - - // qDivProdExp_opA_uid94_fpDivTest(ADD,93)@14 + 1 - assign qDivProdExp_opA_uid94_fpDivTest_a = {1'b0, redist20_expY_uid12_fpDivTest_b_14_q}; - assign qDivProdExp_opA_uid94_fpDivTest_b = {1'b0, expPostRndF_uid82_fpDivTest_q}; - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - qDivProdExp_opA_uid94_fpDivTest_o <= 9'b0; - end - else if (en == 1'b1) - begin - qDivProdExp_opA_uid94_fpDivTest_o <= $unsigned(qDivProdExp_opA_uid94_fpDivTest_a) + $unsigned(qDivProdExp_opA_uid94_fpDivTest_b); - end - end - assign qDivProdExp_opA_uid94_fpDivTest_q = qDivProdExp_opA_uid94_fpDivTest_o[8:0]; - - // redist6_qDivProdExp_opA_uid94_fpDivTest_q_4(DELAY,192) - dspba_delay_ver #( .width(9), .depth(3), .reset_kind("ASYNC") ) - redist6_qDivProdExp_opA_uid94_fpDivTest_q_4 ( .xin(qDivProdExp_opA_uid94_fpDivTest_q), .xout(redist6_qDivProdExp_opA_uid94_fpDivTest_q_4_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // qDivProdExp_uid96_fpDivTest(SUB,95)@18 - assign qDivProdExp_uid96_fpDivTest_a = {3'b000, redist6_qDivProdExp_opA_uid94_fpDivTest_q_4_q}; - assign qDivProdExp_uid96_fpDivTest_b = {{3{qDivProdExp_opBs_uid95_fpDivTest_q[8]}}, qDivProdExp_opBs_uid95_fpDivTest_q}; - assign qDivProdExp_uid96_fpDivTest_o = $signed(qDivProdExp_uid96_fpDivTest_a) - $signed(qDivProdExp_uid96_fpDivTest_b); - assign qDivProdExp_uid96_fpDivTest_q = qDivProdExp_uid96_fpDivTest_o[10:0]; - - // qDivProdLTX_opA_uid98_fpDivTest(BITSELECT,97)@18 - assign qDivProdLTX_opA_uid98_fpDivTest_in = qDivProdExp_uid96_fpDivTest_q[7:0]; - assign qDivProdLTX_opA_uid98_fpDivTest_b = qDivProdLTX_opA_uid98_fpDivTest_in[7:0]; - - // qDivProdFracHigh_uid91_fpDivTest(BITSELECT,90)@17 - assign qDivProdFracHigh_uid91_fpDivTest_in = qDivProd_uid89_fpDivTest_cma_q[47:0]; - assign qDivProdFracHigh_uid91_fpDivTest_b = qDivProdFracHigh_uid91_fpDivTest_in[47:24]; - - // qDivProdFracLow_uid92_fpDivTest(BITSELECT,91)@17 - assign qDivProdFracLow_uid92_fpDivTest_in = qDivProd_uid89_fpDivTest_cma_q[46:0]; - assign qDivProdFracLow_uid92_fpDivTest_b = qDivProdFracLow_uid92_fpDivTest_in[46:23]; - - // qDivProdFrac_uid93_fpDivTest(MUX,92)@17 - assign qDivProdFrac_uid93_fpDivTest_s = qDivProdNorm_uid90_fpDivTest_b; - always @(qDivProdFrac_uid93_fpDivTest_s or en or qDivProdFracLow_uid92_fpDivTest_b or qDivProdFracHigh_uid91_fpDivTest_b) - begin - unique case (qDivProdFrac_uid93_fpDivTest_s) - 1'b0 : qDivProdFrac_uid93_fpDivTest_q = qDivProdFracLow_uid92_fpDivTest_b; - 1'b1 : qDivProdFrac_uid93_fpDivTest_q = qDivProdFracHigh_uid91_fpDivTest_b; - default : qDivProdFrac_uid93_fpDivTest_q = 24'b0; - endcase - end - - // qDivProdFracWF_uid97_fpDivTest(BITSELECT,96)@17 - assign qDivProdFracWF_uid97_fpDivTest_b = qDivProdFrac_uid93_fpDivTest_q[23:1]; - - // redist5_qDivProdFracWF_uid97_fpDivTest_b_1(DELAY,191) - dspba_delay_ver #( .width(23), .depth(1), .reset_kind("ASYNC") ) - redist5_qDivProdFracWF_uid97_fpDivTest_b_1 ( .xin(qDivProdFracWF_uid97_fpDivTest_b), .xout(redist5_qDivProdFracWF_uid97_fpDivTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // qDivProdLTX_opA_uid99_fpDivTest(BITJOIN,98)@18 - assign qDivProdLTX_opA_uid99_fpDivTest_q = {qDivProdLTX_opA_uid98_fpDivTest_b, redist5_qDivProdFracWF_uid97_fpDivTest_b_1_q}; - - // qDividerProdLTX_uid101_fpDivTest(COMPARE,100)@18 + 1 - assign qDividerProdLTX_uid101_fpDivTest_a = {2'b00, qDivProdLTX_opA_uid99_fpDivTest_q}; - assign qDividerProdLTX_uid101_fpDivTest_b = {2'b00, qDivProdLTX_opB_uid100_fpDivTest_q}; - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - qDividerProdLTX_uid101_fpDivTest_o <= 33'b0; - end - else if (en == 1'b1) - begin - qDividerProdLTX_uid101_fpDivTest_o <= $unsigned(qDividerProdLTX_uid101_fpDivTest_a) - $unsigned(qDividerProdLTX_uid101_fpDivTest_b); - end - end - assign qDividerProdLTX_uid101_fpDivTest_c[0] = qDividerProdLTX_uid101_fpDivTest_o[32]; - - // extraUlp_uid103_fpDivTest(LOGICAL,102)@19 - assign extraUlp_uid103_fpDivTest_q = qDividerProdLTX_uid101_fpDivTest_c & betweenFPwF_uid102_fpDivTest_b; - - // fracPostRndFT_uid104_fpDivTest(BITSELECT,103)@19 - assign fracPostRndFT_uid104_fpDivTest_b = redist8_fracPostRndF_uid80_fpDivTest_q_5_outputreg_q[23:1]; - - // fracRPreExcExt_uid105_fpDivTest(ADD,104)@19 - assign fracRPreExcExt_uid105_fpDivTest_a = {1'b0, fracPostRndFT_uid104_fpDivTest_b}; - assign fracRPreExcExt_uid105_fpDivTest_b = {23'b00000000000000000000000, extraUlp_uid103_fpDivTest_q}; - assign fracRPreExcExt_uid105_fpDivTest_o = $unsigned(fracRPreExcExt_uid105_fpDivTest_a) + $unsigned(fracRPreExcExt_uid105_fpDivTest_b); - assign fracRPreExcExt_uid105_fpDivTest_q = fracRPreExcExt_uid105_fpDivTest_o[23:0]; - - // ovfIncRnd_uid109_fpDivTest(BITSELECT,108)@19 - assign ovfIncRnd_uid109_fpDivTest_b = fracRPreExcExt_uid105_fpDivTest_q[23:23]; - - // redist3_ovfIncRnd_uid109_fpDivTest_b_1(DELAY,189) - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - redist3_ovfIncRnd_uid109_fpDivTest_b_1 ( .xin(ovfIncRnd_uid109_fpDivTest_b), .xout(redist3_ovfIncRnd_uid109_fpDivTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // expFracPostRndInc_uid110_fpDivTest(ADD,109)@20 - assign expFracPostRndInc_uid110_fpDivTest_a = {1'b0, redist7_expPostRndFR_uid81_fpDivTest_b_6_outputreg_q}; - assign expFracPostRndInc_uid110_fpDivTest_b = {8'b00000000, redist3_ovfIncRnd_uid109_fpDivTest_b_1_q}; - assign expFracPostRndInc_uid110_fpDivTest_o = $unsigned(expFracPostRndInc_uid110_fpDivTest_a) + $unsigned(expFracPostRndInc_uid110_fpDivTest_b); - assign expFracPostRndInc_uid110_fpDivTest_q = expFracPostRndInc_uid110_fpDivTest_o[8:0]; - - // expFracPostRndR_uid111_fpDivTest(BITSELECT,110)@20 - assign expFracPostRndR_uid111_fpDivTest_in = expFracPostRndInc_uid110_fpDivTest_q[7:0]; - assign expFracPostRndR_uid111_fpDivTest_b = expFracPostRndR_uid111_fpDivTest_in[7:0]; - - // redist7_expPostRndFR_uid81_fpDivTest_b_6_notEnable(LOGICAL,221) - assign redist7_expPostRndFR_uid81_fpDivTest_b_6_notEnable_q = ~ (en); - - // redist7_expPostRndFR_uid81_fpDivTest_b_6_nor(LOGICAL,222) - assign redist7_expPostRndFR_uid81_fpDivTest_b_6_nor_q = ~ (redist7_expPostRndFR_uid81_fpDivTest_b_6_notEnable_q | redist7_expPostRndFR_uid81_fpDivTest_b_6_sticky_ena_q); - - // redist7_expPostRndFR_uid81_fpDivTest_b_6_mem_last(CONSTANT,218) - assign redist7_expPostRndFR_uid81_fpDivTest_b_6_mem_last_q = 3'b010; - - // redist7_expPostRndFR_uid81_fpDivTest_b_6_cmp(LOGICAL,219) - assign redist7_expPostRndFR_uid81_fpDivTest_b_6_cmp_b = {1'b0, redist7_expPostRndFR_uid81_fpDivTest_b_6_rdmux_q}; - assign redist7_expPostRndFR_uid81_fpDivTest_b_6_cmp_q = redist7_expPostRndFR_uid81_fpDivTest_b_6_mem_last_q == redist7_expPostRndFR_uid81_fpDivTest_b_6_cmp_b ? 1'b1 : 1'b0; - - // redist7_expPostRndFR_uid81_fpDivTest_b_6_cmpReg(REG,220) - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - redist7_expPostRndFR_uid81_fpDivTest_b_6_cmpReg_q <= 1'b0; - end - else if (en == 1'b1) - begin - redist7_expPostRndFR_uid81_fpDivTest_b_6_cmpReg_q <= redist7_expPostRndFR_uid81_fpDivTest_b_6_cmp_q; - end - end - - // redist7_expPostRndFR_uid81_fpDivTest_b_6_sticky_ena(REG,223) - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - redist7_expPostRndFR_uid81_fpDivTest_b_6_sticky_ena_q <= 1'b0; - end - else if (redist7_expPostRndFR_uid81_fpDivTest_b_6_nor_q == 1'b1) - begin - redist7_expPostRndFR_uid81_fpDivTest_b_6_sticky_ena_q <= redist7_expPostRndFR_uid81_fpDivTest_b_6_cmpReg_q; - end - end - - // redist7_expPostRndFR_uid81_fpDivTest_b_6_enaAnd(LOGICAL,224) - assign redist7_expPostRndFR_uid81_fpDivTest_b_6_enaAnd_q = redist7_expPostRndFR_uid81_fpDivTest_b_6_sticky_ena_q & en; - - // redist7_expPostRndFR_uid81_fpDivTest_b_6_rdcnt(COUNTER,215) - // low=0, high=3, step=1, init=0 - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - redist7_expPostRndFR_uid81_fpDivTest_b_6_rdcnt_i <= 2'd0; - end - else if (en == 1'b1) - begin - redist7_expPostRndFR_uid81_fpDivTest_b_6_rdcnt_i <= $unsigned(redist7_expPostRndFR_uid81_fpDivTest_b_6_rdcnt_i) + $unsigned(2'd1); - end - end - assign redist7_expPostRndFR_uid81_fpDivTest_b_6_rdcnt_q = redist7_expPostRndFR_uid81_fpDivTest_b_6_rdcnt_i[1:0]; - - // redist7_expPostRndFR_uid81_fpDivTest_b_6_rdmux(MUX,216) - assign redist7_expPostRndFR_uid81_fpDivTest_b_6_rdmux_s = en; - always @(redist7_expPostRndFR_uid81_fpDivTest_b_6_rdmux_s or redist7_expPostRndFR_uid81_fpDivTest_b_6_wraddr_q or redist7_expPostRndFR_uid81_fpDivTest_b_6_rdcnt_q) - begin - unique case (redist7_expPostRndFR_uid81_fpDivTest_b_6_rdmux_s) - 1'b0 : redist7_expPostRndFR_uid81_fpDivTest_b_6_rdmux_q = redist7_expPostRndFR_uid81_fpDivTest_b_6_wraddr_q; - 1'b1 : redist7_expPostRndFR_uid81_fpDivTest_b_6_rdmux_q = redist7_expPostRndFR_uid81_fpDivTest_b_6_rdcnt_q; - default : redist7_expPostRndFR_uid81_fpDivTest_b_6_rdmux_q = 2'b0; - endcase - end - - // redist7_expPostRndFR_uid81_fpDivTest_b_6_wraddr(REG,217) - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - redist7_expPostRndFR_uid81_fpDivTest_b_6_wraddr_q <= 2'b11; - end - else - begin - redist7_expPostRndFR_uid81_fpDivTest_b_6_wraddr_q <= redist7_expPostRndFR_uid81_fpDivTest_b_6_rdmux_q; - end - end - - // redist7_expPostRndFR_uid81_fpDivTest_b_6_mem(DUALMEM,214) - assign redist7_expPostRndFR_uid81_fpDivTest_b_6_mem_ia = expPostRndFR_uid81_fpDivTest_b; - assign redist7_expPostRndFR_uid81_fpDivTest_b_6_mem_aa = redist7_expPostRndFR_uid81_fpDivTest_b_6_wraddr_q; - assign redist7_expPostRndFR_uid81_fpDivTest_b_6_mem_ab = redist7_expPostRndFR_uid81_fpDivTest_b_6_rdmux_q; - assign redist7_expPostRndFR_uid81_fpDivTest_b_6_mem_reset0 = areset; - altera_syncram #( - .ram_block_type("MLAB"), - .operation_mode("DUAL_PORT"), - .width_a(8), - .widthad_a(2), - .numwords_a(4), - .width_b(8), - .widthad_b(2), - .numwords_b(4), - .lpm_type("altera_syncram"), - .width_byteena_a(1), - .address_reg_b("CLOCK0"), - .indata_reg_b("CLOCK0"), - .rdcontrol_reg_b("CLOCK0"), - .byteena_reg_b("CLOCK0"), - .outdata_reg_b("CLOCK1"), - .outdata_aclr_b("CLEAR1"), - .clock_enable_input_a("NORMAL"), - .clock_enable_input_b("NORMAL"), - .clock_enable_output_b("NORMAL"), - .read_during_write_mode_mixed_ports("DONT_CARE"), - .power_up_uninitialized("TRUE"), - .intended_device_family("Arria 10") - ) redist7_expPostRndFR_uid81_fpDivTest_b_6_mem_dmem ( - .clocken1(redist7_expPostRndFR_uid81_fpDivTest_b_6_enaAnd_q[0]), - .clocken0(VCC_q[0]), - .clock0(clk), - .aclr1(redist7_expPostRndFR_uid81_fpDivTest_b_6_mem_reset0), - .clock1(clk), - .address_a(redist7_expPostRndFR_uid81_fpDivTest_b_6_mem_aa), - .data_a(redist7_expPostRndFR_uid81_fpDivTest_b_6_mem_ia), - .wren_a(en[0]), - .address_b(redist7_expPostRndFR_uid81_fpDivTest_b_6_mem_ab), - .q_b(redist7_expPostRndFR_uid81_fpDivTest_b_6_mem_iq), - .wren_b(), - .rden_a(), - .rden_b(), - .data_b(), - .clocken2(), - .clocken3(), - .aclr0(), - .addressstall_a(), - .addressstall_b(), - .byteena_a(), - .byteena_b(), - .eccencbypass(), - .eccencparity(), - .sclr(), - .address2_a(), - .address2_b(), - .q_a(), - .eccstatus() - ); - assign redist7_expPostRndFR_uid81_fpDivTest_b_6_mem_q = redist7_expPostRndFR_uid81_fpDivTest_b_6_mem_iq[7:0]; - - // redist7_expPostRndFR_uid81_fpDivTest_b_6_outputreg(DELAY,213) + // redist2_excRPreExc_uid79_fpDivTest_b_1(DELAY,154) dspba_delay_ver #( .width(8), .depth(1), .reset_kind("ASYNC") ) - redist7_expPostRndFR_uid81_fpDivTest_b_6_outputreg ( .xin(redist7_expPostRndFR_uid81_fpDivTest_b_6_mem_q), .xout(redist7_expPostRndFR_uid81_fpDivTest_b_6_outputreg_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // redist4_extraUlp_uid103_fpDivTest_q_1(DELAY,190) - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - redist4_extraUlp_uid103_fpDivTest_q_1 ( .xin(extraUlp_uid103_fpDivTest_q), .xout(redist4_extraUlp_uid103_fpDivTest_q_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // expRPreExc_uid112_fpDivTest(MUX,111)@20 - assign expRPreExc_uid112_fpDivTest_s = redist4_extraUlp_uid103_fpDivTest_q_1_q; - always @(expRPreExc_uid112_fpDivTest_s or en or redist7_expPostRndFR_uid81_fpDivTest_b_6_outputreg_q or expFracPostRndR_uid111_fpDivTest_b) - begin - unique case (expRPreExc_uid112_fpDivTest_s) - 1'b0 : expRPreExc_uid112_fpDivTest_q = redist7_expPostRndFR_uid81_fpDivTest_b_6_outputreg_q; - 1'b1 : expRPreExc_uid112_fpDivTest_q = expFracPostRndR_uid111_fpDivTest_b; - default : expRPreExc_uid112_fpDivTest_q = 8'b0; - endcase - end + redist2_excRPreExc_uid79_fpDivTest_b_1 ( .xin(excRPreExc_uid79_fpDivTest_b), .xout(redist2_excRPreExc_uid79_fpDivTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); // invExpXIsMax_uid43_fpDivTest(LOGICAL,42)@14 - assign invExpXIsMax_uid43_fpDivTest_q = ~ (expXIsMax_uid38_fpDivTest_q); + assign invExpXIsMax_uid43_fpDivTest_q = ~ (redist13_expXIsMax_uid38_fpDivTest_q_14_q); // InvExpXIsZero_uid44_fpDivTest(LOGICAL,43)@14 - assign InvExpXIsZero_uid44_fpDivTest_q = ~ (excZ_y_uid37_fpDivTest_q); + assign InvExpXIsZero_uid44_fpDivTest_q = ~ (redist14_excZ_y_uid37_fpDivTest_q_14_q); // excR_y_uid45_fpDivTest(LOGICAL,44)@14 assign excR_y_uid45_fpDivTest_q = InvExpXIsZero_uid44_fpDivTest_q & invExpXIsMax_uid43_fpDivTest_q; - // excXIYR_uid127_fpDivTest(LOGICAL,126)@14 - assign excXIYR_uid127_fpDivTest_q = excI_x_uid27_fpDivTest_q & excR_y_uid45_fpDivTest_q; + // excXIYR_uid93_fpDivTest(LOGICAL,92)@14 + assign excXIYR_uid93_fpDivTest_q = excI_x_uid27_fpDivTest_q & excR_y_uid45_fpDivTest_q; - // excXIYZ_uid126_fpDivTest(LOGICAL,125)@14 - assign excXIYZ_uid126_fpDivTest_q = excI_x_uid27_fpDivTest_q & excZ_y_uid37_fpDivTest_q; + // excXIYZ_uid92_fpDivTest(LOGICAL,91)@14 + assign excXIYZ_uid92_fpDivTest_q = excI_x_uid27_fpDivTest_q & redist14_excZ_y_uid37_fpDivTest_q_14_q; - // expRExt_uid114_fpDivTest(BITSELECT,113)@14 - assign expRExt_uid114_fpDivTest_b = expFracPostRnd_uid76_fpDivTest_q[35:25]; + // expRExt_uid80_fpDivTest(BITSELECT,79)@14 + assign expRExt_uid80_fpDivTest_b = expFracPostRnd_uid76_fpDivTest_q[34:24]; - // expOvf_uid118_fpDivTest(COMPARE,117)@14 - assign expOvf_uid118_fpDivTest_a = {{2{expRExt_uid114_fpDivTest_b[10]}}, expRExt_uid114_fpDivTest_b}; - assign expOvf_uid118_fpDivTest_b = {5'b00000, cstAllOWE_uid18_fpDivTest_q}; - assign expOvf_uid118_fpDivTest_o = $signed(expOvf_uid118_fpDivTest_a) - $signed(expOvf_uid118_fpDivTest_b); - assign expOvf_uid118_fpDivTest_n[0] = ~ (expOvf_uid118_fpDivTest_o[12]); + // expOvf_uid84_fpDivTest(COMPARE,83)@14 + assign expOvf_uid84_fpDivTest_a = {{2{expRExt_uid80_fpDivTest_b[10]}}, expRExt_uid80_fpDivTest_b}; + assign expOvf_uid84_fpDivTest_b = {5'b00000, cstAllOWE_uid18_fpDivTest_q}; + assign expOvf_uid84_fpDivTest_o = $signed(expOvf_uid84_fpDivTest_a) - $signed(expOvf_uid84_fpDivTest_b); + assign expOvf_uid84_fpDivTest_n[0] = ~ (expOvf_uid84_fpDivTest_o[12]); // invExpXIsMax_uid29_fpDivTest(LOGICAL,28)@14 - assign invExpXIsMax_uid29_fpDivTest_q = ~ (expXIsMax_uid24_fpDivTest_q); + assign invExpXIsMax_uid29_fpDivTest_q = ~ (redist16_expXIsMax_uid24_fpDivTest_q_14_q); // InvExpXIsZero_uid30_fpDivTest(LOGICAL,29)@14 - assign InvExpXIsZero_uid30_fpDivTest_q = ~ (excZ_x_uid23_fpDivTest_q); + assign InvExpXIsZero_uid30_fpDivTest_q = ~ (redist17_excZ_x_uid23_fpDivTest_q_14_q); // excR_x_uid31_fpDivTest(LOGICAL,30)@14 assign excR_x_uid31_fpDivTest_q = InvExpXIsZero_uid30_fpDivTest_q & invExpXIsMax_uid29_fpDivTest_q; - // excXRYROvf_uid125_fpDivTest(LOGICAL,124)@14 - assign excXRYROvf_uid125_fpDivTest_q = excR_x_uid31_fpDivTest_q & excR_y_uid45_fpDivTest_q & expOvf_uid118_fpDivTest_n; + // excXRYROvf_uid91_fpDivTest(LOGICAL,90)@14 + assign excXRYROvf_uid91_fpDivTest_q = excR_x_uid31_fpDivTest_q & excR_y_uid45_fpDivTest_q & expOvf_uid84_fpDivTest_n; - // excXRYZ_uid124_fpDivTest(LOGICAL,123)@14 - assign excXRYZ_uid124_fpDivTest_q = excR_x_uid31_fpDivTest_q & excZ_y_uid37_fpDivTest_q; + // excXRYZ_uid90_fpDivTest(LOGICAL,89)@14 + assign excXRYZ_uid90_fpDivTest_q = excR_x_uid31_fpDivTest_q & redist14_excZ_y_uid37_fpDivTest_q_14_q; - // excRInf_uid128_fpDivTest(LOGICAL,127)@14 + 1 - assign excRInf_uid128_fpDivTest_qi = excXRYZ_uid124_fpDivTest_q | excXRYROvf_uid125_fpDivTest_q | excXIYZ_uid126_fpDivTest_q | excXIYR_uid127_fpDivTest_q; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - excRInf_uid128_fpDivTest_delay ( .xin(excRInf_uid128_fpDivTest_qi), .xout(excRInf_uid128_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + // excRInf_uid94_fpDivTest(LOGICAL,93)@14 + assign excRInf_uid94_fpDivTest_q = excXRYZ_uid90_fpDivTest_q | excXRYROvf_uid91_fpDivTest_q | excXIYZ_uid92_fpDivTest_q | excXIYR_uid93_fpDivTest_q; - // xRegOrZero_uid121_fpDivTest(LOGICAL,120)@14 - assign xRegOrZero_uid121_fpDivTest_q = excR_x_uid31_fpDivTest_q | excZ_x_uid23_fpDivTest_q; + // xRegOrZero_uid87_fpDivTest(LOGICAL,86)@14 + assign xRegOrZero_uid87_fpDivTest_q = excR_x_uid31_fpDivTest_q | redist17_excZ_x_uid23_fpDivTest_q_14_q; - // regOrZeroOverInf_uid122_fpDivTest(LOGICAL,121)@14 + 1 - assign regOrZeroOverInf_uid122_fpDivTest_qi = xRegOrZero_uid121_fpDivTest_q & excI_y_uid41_fpDivTest_q; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - regOrZeroOverInf_uid122_fpDivTest_delay ( .xin(regOrZeroOverInf_uid122_fpDivTest_qi), .xout(regOrZeroOverInf_uid122_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + // regOrZeroOverInf_uid88_fpDivTest(LOGICAL,87)@14 + assign regOrZeroOverInf_uid88_fpDivTest_q = xRegOrZero_uid87_fpDivTest_q & excI_y_uid41_fpDivTest_q; - // expUdf_uid115_fpDivTest(COMPARE,114)@14 - assign expUdf_uid115_fpDivTest_a = {12'b000000000000, GND_q}; - assign expUdf_uid115_fpDivTest_b = {{2{expRExt_uid114_fpDivTest_b[10]}}, expRExt_uid114_fpDivTest_b}; - assign expUdf_uid115_fpDivTest_o = $signed(expUdf_uid115_fpDivTest_a) - $signed(expUdf_uid115_fpDivTest_b); - assign expUdf_uid115_fpDivTest_n[0] = ~ (expUdf_uid115_fpDivTest_o[12]); + // expUdf_uid81_fpDivTest(COMPARE,80)@14 + assign expUdf_uid81_fpDivTest_a = {12'b000000000000, GND_q}; + assign expUdf_uid81_fpDivTest_b = {{2{expRExt_uid80_fpDivTest_b[10]}}, expRExt_uid80_fpDivTest_b}; + assign expUdf_uid81_fpDivTest_o = $signed(expUdf_uid81_fpDivTest_a) - $signed(expUdf_uid81_fpDivTest_b); + assign expUdf_uid81_fpDivTest_n[0] = ~ (expUdf_uid81_fpDivTest_o[12]); - // regOverRegWithUf_uid120_fpDivTest(LOGICAL,119)@14 + 1 - assign regOverRegWithUf_uid120_fpDivTest_qi = expUdf_uid115_fpDivTest_n & excR_x_uid31_fpDivTest_q & excR_y_uid45_fpDivTest_q; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - regOverRegWithUf_uid120_fpDivTest_delay ( .xin(regOverRegWithUf_uid120_fpDivTest_qi), .xout(regOverRegWithUf_uid120_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + // regOverRegWithUf_uid86_fpDivTest(LOGICAL,85)@14 + assign regOverRegWithUf_uid86_fpDivTest_q = expUdf_uid81_fpDivTest_n & excR_x_uid31_fpDivTest_q & excR_y_uid45_fpDivTest_q; - // zeroOverReg_uid119_fpDivTest(LOGICAL,118)@14 + 1 - assign zeroOverReg_uid119_fpDivTest_qi = excZ_x_uid23_fpDivTest_q & excR_y_uid45_fpDivTest_q; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - zeroOverReg_uid119_fpDivTest_delay ( .xin(zeroOverReg_uid119_fpDivTest_qi), .xout(zeroOverReg_uid119_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + // zeroOverReg_uid85_fpDivTest(LOGICAL,84)@14 + assign zeroOverReg_uid85_fpDivTest_q = redist17_excZ_x_uid23_fpDivTest_q_14_q & excR_y_uid45_fpDivTest_q; - // excRZero_uid123_fpDivTest(LOGICAL,122)@15 - assign excRZero_uid123_fpDivTest_q = zeroOverReg_uid119_fpDivTest_q | regOverRegWithUf_uid120_fpDivTest_q | regOrZeroOverInf_uid122_fpDivTest_q; + // excRZero_uid89_fpDivTest(LOGICAL,88)@14 + assign excRZero_uid89_fpDivTest_q = zeroOverReg_uid85_fpDivTest_q | regOverRegWithUf_uid86_fpDivTest_q | regOrZeroOverInf_uid88_fpDivTest_q; - // concExc_uid132_fpDivTest(BITJOIN,131)@15 - assign concExc_uid132_fpDivTest_q = {excRNaN_uid131_fpDivTest_q, excRInf_uid128_fpDivTest_q, excRZero_uid123_fpDivTest_q}; + // concExc_uid98_fpDivTest(BITJOIN,97)@14 + assign concExc_uid98_fpDivTest_q = {excRNaN_uid97_fpDivTest_q, excRInf_uid94_fpDivTest_q, excRZero_uid89_fpDivTest_q}; - // excREnc_uid133_fpDivTest(LOOKUP,132)@15 + 1 + // excREnc_uid99_fpDivTest(LOOKUP,98)@14 + 1 always @ (posedge clk or posedge areset) begin if (areset) begin - excREnc_uid133_fpDivTest_q <= 2'b01; + excREnc_uid99_fpDivTest_q <= 2'b01; end else if (en == 1'b1) begin - unique case (concExc_uid132_fpDivTest_q) - 3'b000 : excREnc_uid133_fpDivTest_q <= 2'b01; - 3'b001 : excREnc_uid133_fpDivTest_q <= 2'b00; - 3'b010 : excREnc_uid133_fpDivTest_q <= 2'b10; - 3'b011 : excREnc_uid133_fpDivTest_q <= 2'b00; - 3'b100 : excREnc_uid133_fpDivTest_q <= 2'b11; - 3'b101 : excREnc_uid133_fpDivTest_q <= 2'b00; - 3'b110 : excREnc_uid133_fpDivTest_q <= 2'b00; - 3'b111 : excREnc_uid133_fpDivTest_q <= 2'b00; + unique case (concExc_uid98_fpDivTest_q) + 3'b000 : excREnc_uid99_fpDivTest_q <= 2'b01; + 3'b001 : excREnc_uid99_fpDivTest_q <= 2'b00; + 3'b010 : excREnc_uid99_fpDivTest_q <= 2'b10; + 3'b011 : excREnc_uid99_fpDivTest_q <= 2'b00; + 3'b100 : excREnc_uid99_fpDivTest_q <= 2'b11; + 3'b101 : excREnc_uid99_fpDivTest_q <= 2'b00; + 3'b110 : excREnc_uid99_fpDivTest_q <= 2'b00; + 3'b111 : excREnc_uid99_fpDivTest_q <= 2'b00; default : begin // unreachable - excREnc_uid133_fpDivTest_q <= 2'bxx; + excREnc_uid99_fpDivTest_q <= 2'bxx; end endcase end end - // redist2_excREnc_uid133_fpDivTest_q_5(DELAY,188) - dspba_delay_ver #( .width(2), .depth(4), .reset_kind("ASYNC") ) - redist2_excREnc_uid133_fpDivTest_q_5 ( .xin(excREnc_uid133_fpDivTest_q), .xout(redist2_excREnc_uid133_fpDivTest_q_5_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // expRPostExc_uid141_fpDivTest(MUX,140)@20 - assign expRPostExc_uid141_fpDivTest_s = redist2_excREnc_uid133_fpDivTest_q_5_q; - always @(expRPostExc_uid141_fpDivTest_s or en or cstAllZWE_uid20_fpDivTest_q or expRPreExc_uid112_fpDivTest_q or cstAllOWE_uid18_fpDivTest_q) + // expRPostExc_uid107_fpDivTest(MUX,106)@15 + assign expRPostExc_uid107_fpDivTest_s = excREnc_uid99_fpDivTest_q; + always @(expRPostExc_uid107_fpDivTest_s or en or cstAllZWE_uid20_fpDivTest_q or redist2_excRPreExc_uid79_fpDivTest_b_1_q or cstAllOWE_uid18_fpDivTest_q) begin - unique case (expRPostExc_uid141_fpDivTest_s) - 2'b00 : expRPostExc_uid141_fpDivTest_q = cstAllZWE_uid20_fpDivTest_q; - 2'b01 : expRPostExc_uid141_fpDivTest_q = expRPreExc_uid112_fpDivTest_q; - 2'b10 : expRPostExc_uid141_fpDivTest_q = cstAllOWE_uid18_fpDivTest_q; - 2'b11 : expRPostExc_uid141_fpDivTest_q = cstAllOWE_uid18_fpDivTest_q; - default : expRPostExc_uid141_fpDivTest_q = 8'b0; + unique case (expRPostExc_uid107_fpDivTest_s) + 2'b00 : expRPostExc_uid107_fpDivTest_q = cstAllZWE_uid20_fpDivTest_q; + 2'b01 : expRPostExc_uid107_fpDivTest_q = redist2_excRPreExc_uid79_fpDivTest_b_1_q; + 2'b10 : expRPostExc_uid107_fpDivTest_q = cstAllOWE_uid18_fpDivTest_q; + 2'b11 : expRPostExc_uid107_fpDivTest_q = cstAllOWE_uid18_fpDivTest_q; + default : expRPostExc_uid107_fpDivTest_q = 8'b0; endcase end - // oneFracRPostExc2_uid134_fpDivTest(CONSTANT,133) - assign oneFracRPostExc2_uid134_fpDivTest_q = 23'b00000000000000000000001; + // oneFracRPostExc2_uid100_fpDivTest(CONSTANT,99) + assign oneFracRPostExc2_uid100_fpDivTest_q = 23'b00000000000000000000001; - // fracPostRndFPostUlp_uid106_fpDivTest(BITSELECT,105)@19 - assign fracPostRndFPostUlp_uid106_fpDivTest_in = fracRPreExcExt_uid105_fpDivTest_q[22:0]; - assign fracPostRndFPostUlp_uid106_fpDivTest_b = fracPostRndFPostUlp_uid106_fpDivTest_in[22:0]; + // fracRPreExc_uid78_fpDivTest(BITSELECT,77)@14 + assign fracRPreExc_uid78_fpDivTest_in = expFracPostRnd_uid76_fpDivTest_q[23:0]; + assign fracRPreExc_uid78_fpDivTest_b = fracRPreExc_uid78_fpDivTest_in[23:1]; - // fracRPreExc_uid107_fpDivTest(MUX,106)@19 + 1 - assign fracRPreExc_uid107_fpDivTest_s = extraUlp_uid103_fpDivTest_q; - always @ (posedge clk or posedge areset) + // redist3_fracRPreExc_uid78_fpDivTest_b_1(DELAY,155) + dspba_delay_ver #( .width(23), .depth(1), .reset_kind("ASYNC") ) + redist3_fracRPreExc_uid78_fpDivTest_b_1 ( .xin(fracRPreExc_uid78_fpDivTest_b), .xout(redist3_fracRPreExc_uid78_fpDivTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // fracRPostExc_uid103_fpDivTest(MUX,102)@15 + assign fracRPostExc_uid103_fpDivTest_s = excREnc_uid99_fpDivTest_q; + always @(fracRPostExc_uid103_fpDivTest_s or en or paddingY_uid15_fpDivTest_q or redist3_fracRPreExc_uid78_fpDivTest_b_1_q or oneFracRPostExc2_uid100_fpDivTest_q) begin - if (areset) - begin - fracRPreExc_uid107_fpDivTest_q <= 23'b0; - end - else if (en == 1'b1) - begin - unique case (fracRPreExc_uid107_fpDivTest_s) - 1'b0 : fracRPreExc_uid107_fpDivTest_q <= fracPostRndFT_uid104_fpDivTest_b; - 1'b1 : fracRPreExc_uid107_fpDivTest_q <= fracPostRndFPostUlp_uid106_fpDivTest_b; - default : fracRPreExc_uid107_fpDivTest_q <= 23'b0; - endcase - end - end - - // fracRPostExc_uid137_fpDivTest(MUX,136)@20 - assign fracRPostExc_uid137_fpDivTest_s = redist2_excREnc_uid133_fpDivTest_q_5_q; - always @(fracRPostExc_uid137_fpDivTest_s or en or paddingY_uid15_fpDivTest_q or fracRPreExc_uid107_fpDivTest_q or oneFracRPostExc2_uid134_fpDivTest_q) - begin - unique case (fracRPostExc_uid137_fpDivTest_s) - 2'b00 : fracRPostExc_uid137_fpDivTest_q = paddingY_uid15_fpDivTest_q; - 2'b01 : fracRPostExc_uid137_fpDivTest_q = fracRPreExc_uid107_fpDivTest_q; - 2'b10 : fracRPostExc_uid137_fpDivTest_q = paddingY_uid15_fpDivTest_q; - 2'b11 : fracRPostExc_uid137_fpDivTest_q = oneFracRPostExc2_uid134_fpDivTest_q; - default : fracRPostExc_uid137_fpDivTest_q = 23'b0; + unique case (fracRPostExc_uid103_fpDivTest_s) + 2'b00 : fracRPostExc_uid103_fpDivTest_q = paddingY_uid15_fpDivTest_q; + 2'b01 : fracRPostExc_uid103_fpDivTest_q = redist3_fracRPreExc_uid78_fpDivTest_b_1_q; + 2'b10 : fracRPostExc_uid103_fpDivTest_q = paddingY_uid15_fpDivTest_q; + 2'b11 : fracRPostExc_uid103_fpDivTest_q = oneFracRPostExc2_uid100_fpDivTest_q; + default : fracRPostExc_uid103_fpDivTest_q = 23'b0; endcase end - // divR_uid144_fpDivTest(BITJOIN,143)@20 - assign divR_uid144_fpDivTest_q = {redist1_sRPostExc_uid143_fpDivTest_q_5_q, expRPostExc_uid141_fpDivTest_q, fracRPostExc_uid137_fpDivTest_q}; + // divR_uid110_fpDivTest(BITJOIN,109)@15 + assign divR_uid110_fpDivTest_q = {sRPostExc_uid109_fpDivTest_q, expRPostExc_uid107_fpDivTest_q, fracRPostExc_uid103_fpDivTest_q}; - // xOut(GPOUT,4)@20 - assign q = divR_uid144_fpDivTest_q; + // xOut(GPOUT,4)@15 + assign q = divR_uid110_fpDivTest_q; endmodule diff --git a/hw/rtl/fp_cores/altera/arria10/acl_fmadd.sv b/hw/rtl/fp_cores/altera/arria10/acl_fmadd.sv index 9ebb18ab..a30384ef 100644 --- a/hw/rtl/fp_cores/altera/arria10/acl_fmadd.sv +++ b/hw/rtl/fp_cores/altera/arria10/acl_fmadd.sv @@ -16,7 +16,7 @@ // --------------------------------------------------------------------------- // SystemVerilog created from acl_fmadd -// SystemVerilog created on Sun Dec 27 09:47:20 2020 +// SystemVerilog created on Mon Jan 18 04:15:46 2021 (* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *) diff --git a/hw/rtl/fp_cores/altera/arria10/acl_fsqrt.sv b/hw/rtl/fp_cores/altera/arria10/acl_fsqrt.sv index e0c54e61..80083328 100644 --- a/hw/rtl/fp_cores/altera/arria10/acl_fsqrt.sv +++ b/hw/rtl/fp_cores/altera/arria10/acl_fsqrt.sv @@ -16,7 +16,7 @@ // --------------------------------------------------------------------------- // SystemVerilog created from acl_fsqrt -// SystemVerilog created on Sun Dec 27 09:47:21 2020 +// SystemVerilog created on Mon Jan 18 04:15:46 2021 (* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *) @@ -69,585 +69,184 @@ module acl_fsqrt ( wire [7:0] yAddr_uid35_fpSqrtTest_b; wire [15:0] yForPe_uid36_fpSqrtTest_in; wire [15:0] yForPe_uid36_fpSqrtTest_b; - wire [30:0] expIncPEOnly_uid38_fpSqrtTest_in; - wire [0:0] expIncPEOnly_uid38_fpSqrtTest_b; - wire [28:0] fracRPreCR_uid39_fpSqrtTest_in; - wire [23:0] fracRPreCR_uid39_fpSqrtTest_b; - wire [24:0] fracPaddingOne_uid41_fpSqrtTest_q; - wire [23:0] oFracX_uid44_fpSqrtTest_q; - wire [24:0] oFracXZ_mergedSignalTM_uid47_fpSqrtTest_q; - wire [24:0] oFracXSignExt_mergedSignalTM_uid52_fpSqrtTest_q; - wire [0:0] normalizedXForComp_uid54_fpSqrtTest_s; - reg [24:0] normalizedXForComp_uid54_fpSqrtTest_q; - wire [24:0] paddingY_uid55_fpSqrtTest_q; - wire [49:0] updatedY_uid56_fpSqrtTest_q; - wire [51:0] squaredResultGTEIn_uid55_fpSqrtTest_a; - wire [51:0] squaredResultGTEIn_uid55_fpSqrtTest_b; - logic [51:0] squaredResultGTEIn_uid55_fpSqrtTest_o; - wire [0:0] squaredResultGTEIn_uid55_fpSqrtTest_n; - wire [0:0] pLTOne_uid58_fpSqrtTest_q; - wire [24:0] fxpSqrtResPostUpdateE_uid60_fpSqrtTest_a; - wire [24:0] fxpSqrtResPostUpdateE_uid60_fpSqrtTest_b; - logic [24:0] fxpSqrtResPostUpdateE_uid60_fpSqrtTest_o; - wire [24:0] fxpSqrtResPostUpdateE_uid60_fpSqrtTest_q; - wire [0:0] fracPENotOne_uid62_fpSqrtTest_q; - wire [0:0] fracPENotOneAndCRRoundsExp_uid63_fpSqrtTest_q; - wire [0:0] expInc_uid64_fpSqrtTest_qi; - reg [0:0] expInc_uid64_fpSqrtTest_q; - wire [8:0] expR_uid66_fpSqrtTest_a; - wire [8:0] expR_uid66_fpSqrtTest_b; - logic [8:0] expR_uid66_fpSqrtTest_o; - wire [8:0] expR_uid66_fpSqrtTest_q; - wire [0:0] invSignX_uid67_fpSqrtTest_q; - wire [0:0] inInfAndNotNeg_uid68_fpSqrtTest_q; - wire [0:0] minReg_uid69_fpSqrtTest_q; - wire [0:0] minInf_uid70_fpSqrtTest_q; - wire [0:0] excRNaN_uid71_fpSqrtTest_q; - wire [2:0] excConc_uid72_fpSqrtTest_q; - wire [3:0] fracSelIn_uid73_fpSqrtTest_q; - reg [1:0] fracSel_uid74_fpSqrtTest_q; - wire [7:0] expRR_uid77_fpSqrtTest_in; - wire [7:0] expRR_uid77_fpSqrtTest_b; - wire [1:0] expRPostExc_uid79_fpSqrtTest_s; - reg [7:0] expRPostExc_uid79_fpSqrtTest_q; - wire [22:0] fracNaN_uid80_fpSqrtTest_q; - wire [1:0] fracRPostExc_uid84_fpSqrtTest_s; - reg [22:0] fracRPostExc_uid84_fpSqrtTest_q; - wire [0:0] negZero_uid85_fpSqrtTest_qi; - reg [0:0] negZero_uid85_fpSqrtTest_q; - wire [31:0] RSqrt_uid86_fpSqrtTest_q; - wire [11:0] yT1_uid100_invPolyEval_b; - wire [0:0] lowRangeB_uid102_invPolyEval_in; - wire [0:0] lowRangeB_uid102_invPolyEval_b; - wire [11:0] highBBits_uid103_invPolyEval_b; - wire [21:0] s1sumAHighB_uid104_invPolyEval_a; - wire [21:0] s1sumAHighB_uid104_invPolyEval_b; - logic [21:0] s1sumAHighB_uid104_invPolyEval_o; - wire [21:0] s1sumAHighB_uid104_invPolyEval_q; - wire [22:0] s1_uid105_invPolyEval_q; - wire [1:0] lowRangeB_uid108_invPolyEval_in; - wire [1:0] lowRangeB_uid108_invPolyEval_b; - wire [21:0] highBBits_uid109_invPolyEval_b; - wire [29:0] s2sumAHighB_uid110_invPolyEval_a; - wire [29:0] s2sumAHighB_uid110_invPolyEval_b; - logic [29:0] s2sumAHighB_uid110_invPolyEval_o; - wire [29:0] s2sumAHighB_uid110_invPolyEval_q; - wire [31:0] s2_uid111_invPolyEval_q; - wire [12:0] osig_uid114_pT1_uid101_invPolyEval_b; - wire [23:0] osig_uid117_pT2_uid107_invPolyEval_b; - wire memoryC0_uid88_sqrtTables_lutmem_reset0; - wire [28:0] memoryC0_uid88_sqrtTables_lutmem_ia; - wire [7:0] memoryC0_uid88_sqrtTables_lutmem_aa; - wire [7:0] memoryC0_uid88_sqrtTables_lutmem_ab; - wire [28:0] memoryC0_uid88_sqrtTables_lutmem_ir; - wire [28:0] memoryC0_uid88_sqrtTables_lutmem_r; - wire memoryC1_uid91_sqrtTables_lutmem_reset0; - wire [20:0] memoryC1_uid91_sqrtTables_lutmem_ia; - wire [7:0] memoryC1_uid91_sqrtTables_lutmem_aa; - wire [7:0] memoryC1_uid91_sqrtTables_lutmem_ab; - wire [20:0] memoryC1_uid91_sqrtTables_lutmem_ir; - wire [20:0] memoryC1_uid91_sqrtTables_lutmem_r; - wire memoryC2_uid94_sqrtTables_lutmem_reset0; - wire [11:0] memoryC2_uid94_sqrtTables_lutmem_ia; - wire [7:0] memoryC2_uid94_sqrtTables_lutmem_aa; - wire [7:0] memoryC2_uid94_sqrtTables_lutmem_ab; - wire [11:0] memoryC2_uid94_sqrtTables_lutmem_ir; - wire [11:0] memoryC2_uid94_sqrtTables_lutmem_r; - wire squaredResult_uid42_fpSqrtTest_cma_reset; - (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [24:0] squaredResult_uid42_fpSqrtTest_cma_a0 [0:0]; - (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [24:0] squaredResult_uid42_fpSqrtTest_cma_a1 [0:0]; - (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [24:0] squaredResult_uid42_fpSqrtTest_cma_c0 [0:0]; - (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [24:0] squaredResult_uid42_fpSqrtTest_cma_c1 [0:0]; - wire [49:0] squaredResult_uid42_fpSqrtTest_cma_p [0:0]; - wire [49:0] squaredResult_uid42_fpSqrtTest_cma_u [0:0]; - wire [49:0] squaredResult_uid42_fpSqrtTest_cma_w [0:0]; - wire [49:0] squaredResult_uid42_fpSqrtTest_cma_x [0:0]; - wire [49:0] squaredResult_uid42_fpSqrtTest_cma_y [0:0]; - reg [49:0] squaredResult_uid42_fpSqrtTest_cma_s [0:0]; - wire [49:0] squaredResult_uid42_fpSqrtTest_cma_qq; - wire [49:0] squaredResult_uid42_fpSqrtTest_cma_q; - wire squaredResult_uid42_fpSqrtTest_cma_ena0; - wire squaredResult_uid42_fpSqrtTest_cma_ena1; - wire squaredResult_uid42_fpSqrtTest_cma_ena2; - wire prodXY_uid113_pT1_uid101_invPolyEval_cma_reset; - (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [11:0] prodXY_uid113_pT1_uid101_invPolyEval_cma_a0 [0:0]; - (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [11:0] prodXY_uid113_pT1_uid101_invPolyEval_cma_a1 [0:0]; - (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg signed [11:0] prodXY_uid113_pT1_uid101_invPolyEval_cma_c0 [0:0]; - (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg signed [11:0] prodXY_uid113_pT1_uid101_invPolyEval_cma_c1 [0:0]; - wire signed [12:0] prodXY_uid113_pT1_uid101_invPolyEval_cma_l [0:0]; - wire signed [24:0] prodXY_uid113_pT1_uid101_invPolyEval_cma_p [0:0]; - wire signed [24:0] prodXY_uid113_pT1_uid101_invPolyEval_cma_u [0:0]; - wire signed [24:0] prodXY_uid113_pT1_uid101_invPolyEval_cma_w [0:0]; - wire signed [24:0] prodXY_uid113_pT1_uid101_invPolyEval_cma_x [0:0]; - wire signed [24:0] prodXY_uid113_pT1_uid101_invPolyEval_cma_y [0:0]; - reg signed [24:0] prodXY_uid113_pT1_uid101_invPolyEval_cma_s [0:0]; - wire [23:0] prodXY_uid113_pT1_uid101_invPolyEval_cma_qq; - wire [23:0] prodXY_uid113_pT1_uid101_invPolyEval_cma_q; - wire prodXY_uid113_pT1_uid101_invPolyEval_cma_ena0; - wire prodXY_uid113_pT1_uid101_invPolyEval_cma_ena1; - wire prodXY_uid113_pT1_uid101_invPolyEval_cma_ena2; - wire prodXY_uid116_pT2_uid107_invPolyEval_cma_reset; - (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [15:0] prodXY_uid116_pT2_uid107_invPolyEval_cma_a0 [0:0]; - (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [15:0] prodXY_uid116_pT2_uid107_invPolyEval_cma_a1 [0:0]; - (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg signed [22:0] prodXY_uid116_pT2_uid107_invPolyEval_cma_c0 [0:0]; - (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg signed [22:0] prodXY_uid116_pT2_uid107_invPolyEval_cma_c1 [0:0]; - wire signed [16:0] prodXY_uid116_pT2_uid107_invPolyEval_cma_l [0:0]; - wire signed [39:0] prodXY_uid116_pT2_uid107_invPolyEval_cma_p [0:0]; - wire signed [39:0] prodXY_uid116_pT2_uid107_invPolyEval_cma_u [0:0]; - wire signed [39:0] prodXY_uid116_pT2_uid107_invPolyEval_cma_w [0:0]; - wire signed [39:0] prodXY_uid116_pT2_uid107_invPolyEval_cma_x [0:0]; - wire signed [39:0] prodXY_uid116_pT2_uid107_invPolyEval_cma_y [0:0]; - reg signed [39:0] prodXY_uid116_pT2_uid107_invPolyEval_cma_s [0:0]; - wire [38:0] prodXY_uid116_pT2_uid107_invPolyEval_cma_qq; - wire [38:0] prodXY_uid116_pT2_uid107_invPolyEval_cma_q; - wire prodXY_uid116_pT2_uid107_invPolyEval_cma_ena0; - wire prodXY_uid116_pT2_uid107_invPolyEval_cma_ena1; - wire prodXY_uid116_pT2_uid107_invPolyEval_cma_ena2; - wire [0:0] expUpdateCRU_uid61_fpSqrtTest_merged_bit_select_b; - wire [22:0] expUpdateCRU_uid61_fpSqrtTest_merged_bit_select_c; - reg [22:0] redist0_expUpdateCRU_uid61_fpSqrtTest_merged_bit_select_c_1_q; - reg [0:0] redist1_lowRangeB_uid102_invPolyEval_b_1_q; - reg [23:0] redist2_fracRPreCR_uid39_fpSqrtTest_b_1_q; - reg [23:0] redist3_fracRPreCR_uid39_fpSqrtTest_b_5_q; - reg [0:0] redist4_expIncPEOnly_uid38_fpSqrtTest_b_5_q; - reg [7:0] redist6_yAddr_uid35_fpSqrtTest_b_3_q; - reg [7:0] redist7_yAddr_uid35_fpSqrtTest_b_7_q; - reg [7:0] redist8_expRMux_uid31_fpSqrtTest_q_2_q; - reg [0:0] redist9_expOddSelect_uid30_fpSqrtTest_q_13_q; - reg [22:0] redist10_frac_x_uid12_fpSqrtTest_b_2_q; - reg [0:0] redist12_signX_uid7_fpSqrtTest_b_14_q; - reg [23:0] redist3_fracRPreCR_uid39_fpSqrtTest_b_5_inputreg_q; - wire redist5_yForPe_uid36_fpSqrtTest_b_4_mem_reset0; - wire [15:0] redist5_yForPe_uid36_fpSqrtTest_b_4_mem_ia; - wire [1:0] redist5_yForPe_uid36_fpSqrtTest_b_4_mem_aa; - wire [1:0] redist5_yForPe_uid36_fpSqrtTest_b_4_mem_ab; - wire [15:0] redist5_yForPe_uid36_fpSqrtTest_b_4_mem_iq; - wire [15:0] redist5_yForPe_uid36_fpSqrtTest_b_4_mem_q; - wire [1:0] redist5_yForPe_uid36_fpSqrtTest_b_4_rdcnt_q; - (* preserve *) reg [1:0] redist5_yForPe_uid36_fpSqrtTest_b_4_rdcnt_i; - (* preserve *) reg redist5_yForPe_uid36_fpSqrtTest_b_4_rdcnt_eq; - wire [0:0] redist5_yForPe_uid36_fpSqrtTest_b_4_rdmux_s; - reg [1:0] redist5_yForPe_uid36_fpSqrtTest_b_4_rdmux_q; - reg [1:0] redist5_yForPe_uid36_fpSqrtTest_b_4_wraddr_q; - wire [1:0] redist5_yForPe_uid36_fpSqrtTest_b_4_mem_last_q; - wire [0:0] redist5_yForPe_uid36_fpSqrtTest_b_4_cmp_q; - reg [0:0] redist5_yForPe_uid36_fpSqrtTest_b_4_cmpReg_q; - wire [0:0] redist5_yForPe_uid36_fpSqrtTest_b_4_notEnable_q; - wire [0:0] redist5_yForPe_uid36_fpSqrtTest_b_4_nor_q; - (* preserve_syn_only *) reg [0:0] redist5_yForPe_uid36_fpSqrtTest_b_4_sticky_ena_q; - wire [0:0] redist5_yForPe_uid36_fpSqrtTest_b_4_enaAnd_q; - reg [22:0] redist11_frac_x_uid12_fpSqrtTest_b_13_outputreg_q; - wire redist11_frac_x_uid12_fpSqrtTest_b_13_mem_reset0; - wire [22:0] redist11_frac_x_uid12_fpSqrtTest_b_13_mem_ia; - wire [3:0] redist11_frac_x_uid12_fpSqrtTest_b_13_mem_aa; - wire [3:0] redist11_frac_x_uid12_fpSqrtTest_b_13_mem_ab; - wire [22:0] redist11_frac_x_uid12_fpSqrtTest_b_13_mem_iq; - wire [22:0] redist11_frac_x_uid12_fpSqrtTest_b_13_mem_q; - wire [3:0] redist11_frac_x_uid12_fpSqrtTest_b_13_rdcnt_q; - (* preserve *) reg [3:0] redist11_frac_x_uid12_fpSqrtTest_b_13_rdcnt_i; - (* preserve *) reg redist11_frac_x_uid12_fpSqrtTest_b_13_rdcnt_eq; - wire [0:0] redist11_frac_x_uid12_fpSqrtTest_b_13_rdmux_s; - reg [3:0] redist11_frac_x_uid12_fpSqrtTest_b_13_rdmux_q; - reg [3:0] redist11_frac_x_uid12_fpSqrtTest_b_13_wraddr_q; - wire [3:0] redist11_frac_x_uid12_fpSqrtTest_b_13_mem_last_q; - wire [0:0] redist11_frac_x_uid12_fpSqrtTest_b_13_cmp_q; - reg [0:0] redist11_frac_x_uid12_fpSqrtTest_b_13_cmpReg_q; - wire [0:0] redist11_frac_x_uid12_fpSqrtTest_b_13_notEnable_q; - wire [0:0] redist11_frac_x_uid12_fpSqrtTest_b_13_nor_q; - (* preserve_syn_only *) reg [0:0] redist11_frac_x_uid12_fpSqrtTest_b_13_sticky_ena_q; - wire [0:0] redist11_frac_x_uid12_fpSqrtTest_b_13_enaAnd_q; - reg [7:0] redist13_expX_uid6_fpSqrtTest_b_13_outputreg_q; - wire redist13_expX_uid6_fpSqrtTest_b_13_mem_reset0; - wire [7:0] redist13_expX_uid6_fpSqrtTest_b_13_mem_ia; - wire [3:0] redist13_expX_uid6_fpSqrtTest_b_13_mem_aa; - wire [3:0] redist13_expX_uid6_fpSqrtTest_b_13_mem_ab; - wire [7:0] redist13_expX_uid6_fpSqrtTest_b_13_mem_iq; - wire [7:0] redist13_expX_uid6_fpSqrtTest_b_13_mem_q; - wire [3:0] redist13_expX_uid6_fpSqrtTest_b_13_rdcnt_q; - (* preserve *) reg [3:0] redist13_expX_uid6_fpSqrtTest_b_13_rdcnt_i; - (* preserve *) reg redist13_expX_uid6_fpSqrtTest_b_13_rdcnt_eq; - wire [0:0] redist13_expX_uid6_fpSqrtTest_b_13_rdmux_s; - reg [3:0] redist13_expX_uid6_fpSqrtTest_b_13_rdmux_q; - reg [3:0] redist13_expX_uid6_fpSqrtTest_b_13_wraddr_q; - wire [4:0] redist13_expX_uid6_fpSqrtTest_b_13_mem_last_q; - wire [4:0] redist13_expX_uid6_fpSqrtTest_b_13_cmp_b; - wire [0:0] redist13_expX_uid6_fpSqrtTest_b_13_cmp_q; - reg [0:0] redist13_expX_uid6_fpSqrtTest_b_13_cmpReg_q; - wire [0:0] redist13_expX_uid6_fpSqrtTest_b_13_notEnable_q; - wire [0:0] redist13_expX_uid6_fpSqrtTest_b_13_nor_q; - (* preserve_syn_only *) reg [0:0] redist13_expX_uid6_fpSqrtTest_b_13_sticky_ena_q; - wire [0:0] redist13_expX_uid6_fpSqrtTest_b_13_enaAnd_q; + wire [30:0] expInc_uid38_fpSqrtTest_in; + wire [0:0] expInc_uid38_fpSqrtTest_b; + wire [28:0] fracRPostProcessings_uid39_fpSqrtTest_in; + wire [22:0] fracRPostProcessings_uid39_fpSqrtTest_b; + wire [8:0] expR_uid40_fpSqrtTest_a; + wire [8:0] expR_uid40_fpSqrtTest_b; + logic [8:0] expR_uid40_fpSqrtTest_o; + wire [8:0] expR_uid40_fpSqrtTest_q; + wire [0:0] invSignX_uid41_fpSqrtTest_q; + wire [0:0] inInfAndNotNeg_uid42_fpSqrtTest_q; + wire [0:0] minReg_uid43_fpSqrtTest_q; + wire [0:0] minInf_uid44_fpSqrtTest_q; + wire [0:0] excRNaN_uid45_fpSqrtTest_q; + wire [2:0] excConc_uid46_fpSqrtTest_q; + wire [3:0] fracSelIn_uid47_fpSqrtTest_q; + reg [1:0] fracSel_uid48_fpSqrtTest_q; + wire [7:0] expRR_uid51_fpSqrtTest_in; + wire [7:0] expRR_uid51_fpSqrtTest_b; + wire [1:0] expRPostExc_uid53_fpSqrtTest_s; + reg [7:0] expRPostExc_uid53_fpSqrtTest_q; + wire [22:0] fracNaN_uid54_fpSqrtTest_q; + wire [1:0] fracRPostExc_uid58_fpSqrtTest_s; + reg [22:0] fracRPostExc_uid58_fpSqrtTest_q; + wire [0:0] negZero_uid59_fpSqrtTest_qi; + reg [0:0] negZero_uid59_fpSqrtTest_q; + wire [31:0] RSqrt_uid60_fpSqrtTest_q; + wire [11:0] yT1_uid74_invPolyEval_b; + wire [0:0] lowRangeB_uid76_invPolyEval_in; + wire [0:0] lowRangeB_uid76_invPolyEval_b; + wire [11:0] highBBits_uid77_invPolyEval_b; + wire [21:0] s1sumAHighB_uid78_invPolyEval_a; + wire [21:0] s1sumAHighB_uid78_invPolyEval_b; + logic [21:0] s1sumAHighB_uid78_invPolyEval_o; + wire [21:0] s1sumAHighB_uid78_invPolyEval_q; + wire [22:0] s1_uid79_invPolyEval_q; + wire [1:0] lowRangeB_uid82_invPolyEval_in; + wire [1:0] lowRangeB_uid82_invPolyEval_b; + wire [21:0] highBBits_uid83_invPolyEval_b; + wire [29:0] s2sumAHighB_uid84_invPolyEval_a; + wire [29:0] s2sumAHighB_uid84_invPolyEval_b; + logic [29:0] s2sumAHighB_uid84_invPolyEval_o; + wire [29:0] s2sumAHighB_uid84_invPolyEval_q; + wire [31:0] s2_uid85_invPolyEval_q; + wire [12:0] osig_uid88_pT1_uid75_invPolyEval_b; + wire [23:0] osig_uid91_pT2_uid81_invPolyEval_b; + wire memoryC0_uid62_sqrtTables_lutmem_reset0; + wire [28:0] memoryC0_uid62_sqrtTables_lutmem_ia; + wire [7:0] memoryC0_uid62_sqrtTables_lutmem_aa; + wire [7:0] memoryC0_uid62_sqrtTables_lutmem_ab; + wire [28:0] memoryC0_uid62_sqrtTables_lutmem_ir; + wire [28:0] memoryC0_uid62_sqrtTables_lutmem_r; + wire memoryC1_uid65_sqrtTables_lutmem_reset0; + wire [20:0] memoryC1_uid65_sqrtTables_lutmem_ia; + wire [7:0] memoryC1_uid65_sqrtTables_lutmem_aa; + wire [7:0] memoryC1_uid65_sqrtTables_lutmem_ab; + wire [20:0] memoryC1_uid65_sqrtTables_lutmem_ir; + wire [20:0] memoryC1_uid65_sqrtTables_lutmem_r; + wire memoryC2_uid68_sqrtTables_lutmem_reset0; + wire [11:0] memoryC2_uid68_sqrtTables_lutmem_ia; + wire [7:0] memoryC2_uid68_sqrtTables_lutmem_aa; + wire [7:0] memoryC2_uid68_sqrtTables_lutmem_ab; + wire [11:0] memoryC2_uid68_sqrtTables_lutmem_ir; + wire [11:0] memoryC2_uid68_sqrtTables_lutmem_r; + wire prodXY_uid87_pT1_uid75_invPolyEval_cma_reset; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [11:0] prodXY_uid87_pT1_uid75_invPolyEval_cma_a0 [0:0]; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [11:0] prodXY_uid87_pT1_uid75_invPolyEval_cma_a1 [0:0]; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg signed [11:0] prodXY_uid87_pT1_uid75_invPolyEval_cma_c0 [0:0]; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg signed [11:0] prodXY_uid87_pT1_uid75_invPolyEval_cma_c1 [0:0]; + wire signed [12:0] prodXY_uid87_pT1_uid75_invPolyEval_cma_l [0:0]; + wire signed [24:0] prodXY_uid87_pT1_uid75_invPolyEval_cma_p [0:0]; + wire signed [24:0] prodXY_uid87_pT1_uid75_invPolyEval_cma_u [0:0]; + wire signed [24:0] prodXY_uid87_pT1_uid75_invPolyEval_cma_w [0:0]; + wire signed [24:0] prodXY_uid87_pT1_uid75_invPolyEval_cma_x [0:0]; + wire signed [24:0] prodXY_uid87_pT1_uid75_invPolyEval_cma_y [0:0]; + reg signed [24:0] prodXY_uid87_pT1_uid75_invPolyEval_cma_s [0:0]; + wire [23:0] prodXY_uid87_pT1_uid75_invPolyEval_cma_qq; + wire [23:0] prodXY_uid87_pT1_uid75_invPolyEval_cma_q; + wire prodXY_uid87_pT1_uid75_invPolyEval_cma_ena0; + wire prodXY_uid87_pT1_uid75_invPolyEval_cma_ena1; + wire prodXY_uid87_pT1_uid75_invPolyEval_cma_ena2; + wire prodXY_uid90_pT2_uid81_invPolyEval_cma_reset; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [15:0] prodXY_uid90_pT2_uid81_invPolyEval_cma_a0 [0:0]; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [15:0] prodXY_uid90_pT2_uid81_invPolyEval_cma_a1 [0:0]; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg signed [22:0] prodXY_uid90_pT2_uid81_invPolyEval_cma_c0 [0:0]; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg signed [22:0] prodXY_uid90_pT2_uid81_invPolyEval_cma_c1 [0:0]; + wire signed [16:0] prodXY_uid90_pT2_uid81_invPolyEval_cma_l [0:0]; + wire signed [39:0] prodXY_uid90_pT2_uid81_invPolyEval_cma_p [0:0]; + wire signed [39:0] prodXY_uid90_pT2_uid81_invPolyEval_cma_u [0:0]; + wire signed [39:0] prodXY_uid90_pT2_uid81_invPolyEval_cma_w [0:0]; + wire signed [39:0] prodXY_uid90_pT2_uid81_invPolyEval_cma_x [0:0]; + wire signed [39:0] prodXY_uid90_pT2_uid81_invPolyEval_cma_y [0:0]; + reg signed [39:0] prodXY_uid90_pT2_uid81_invPolyEval_cma_s [0:0]; + wire [38:0] prodXY_uid90_pT2_uid81_invPolyEval_cma_qq; + wire [38:0] prodXY_uid90_pT2_uid81_invPolyEval_cma_q; + wire prodXY_uid90_pT2_uid81_invPolyEval_cma_ena0; + wire prodXY_uid90_pT2_uid81_invPolyEval_cma_ena1; + wire prodXY_uid90_pT2_uid81_invPolyEval_cma_ena2; + reg [0:0] redist0_lowRangeB_uid76_invPolyEval_b_1_q; + reg [0:0] redist1_negZero_uid59_fpSqrtTest_q_9_q; + reg [1:0] redist2_fracSel_uid48_fpSqrtTest_q_9_q; + reg [22:0] redist3_fracRPostProcessings_uid39_fpSqrtTest_b_1_q; + reg [0:0] redist4_expInc_uid38_fpSqrtTest_b_1_q; + reg [15:0] redist5_yForPe_uid36_fpSqrtTest_b_2_q; + reg [7:0] redist7_yAddr_uid35_fpSqrtTest_b_3_q; + reg [7:0] redist8_yAddr_uid35_fpSqrtTest_b_7_q; + reg [0:0] redist10_signX_uid7_fpSqrtTest_b_1_q; + wire redist6_yForPe_uid36_fpSqrtTest_b_6_mem_reset0; + wire [15:0] redist6_yForPe_uid36_fpSqrtTest_b_6_mem_ia; + wire [1:0] redist6_yForPe_uid36_fpSqrtTest_b_6_mem_aa; + wire [1:0] redist6_yForPe_uid36_fpSqrtTest_b_6_mem_ab; + wire [15:0] redist6_yForPe_uid36_fpSqrtTest_b_6_mem_iq; + wire [15:0] redist6_yForPe_uid36_fpSqrtTest_b_6_mem_q; + wire [1:0] redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_q; + (* preserve *) reg [1:0] redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_i; + (* preserve *) reg redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_eq; + wire [0:0] redist6_yForPe_uid36_fpSqrtTest_b_6_rdmux_s; + reg [1:0] redist6_yForPe_uid36_fpSqrtTest_b_6_rdmux_q; + reg [1:0] redist6_yForPe_uid36_fpSqrtTest_b_6_wraddr_q; + wire [1:0] redist6_yForPe_uid36_fpSqrtTest_b_6_mem_last_q; + wire [0:0] redist6_yForPe_uid36_fpSqrtTest_b_6_cmp_q; + reg [0:0] redist6_yForPe_uid36_fpSqrtTest_b_6_cmpReg_q; + wire [0:0] redist6_yForPe_uid36_fpSqrtTest_b_6_notEnable_q; + wire [0:0] redist6_yForPe_uid36_fpSqrtTest_b_6_nor_q; + (* preserve_syn_only *) reg [0:0] redist6_yForPe_uid36_fpSqrtTest_b_6_sticky_ena_q; + wire [0:0] redist6_yForPe_uid36_fpSqrtTest_b_6_enaAnd_q; + reg [7:0] redist9_expRMux_uid31_fpSqrtTest_q_10_outputreg_q; + wire redist9_expRMux_uid31_fpSqrtTest_q_10_mem_reset0; + wire [7:0] redist9_expRMux_uid31_fpSqrtTest_q_10_mem_ia; + wire [2:0] redist9_expRMux_uid31_fpSqrtTest_q_10_mem_aa; + wire [2:0] redist9_expRMux_uid31_fpSqrtTest_q_10_mem_ab; + wire [7:0] redist9_expRMux_uid31_fpSqrtTest_q_10_mem_iq; + wire [7:0] redist9_expRMux_uid31_fpSqrtTest_q_10_mem_q; + wire [2:0] redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_q; + (* preserve *) reg [2:0] redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_i; + (* preserve *) reg redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_eq; + wire [0:0] redist9_expRMux_uid31_fpSqrtTest_q_10_rdmux_s; + reg [2:0] redist9_expRMux_uid31_fpSqrtTest_q_10_rdmux_q; + reg [2:0] redist9_expRMux_uid31_fpSqrtTest_q_10_wraddr_q; + wire [3:0] redist9_expRMux_uid31_fpSqrtTest_q_10_mem_last_q; + wire [3:0] redist9_expRMux_uid31_fpSqrtTest_q_10_cmp_b; + wire [0:0] redist9_expRMux_uid31_fpSqrtTest_q_10_cmp_q; + reg [0:0] redist9_expRMux_uid31_fpSqrtTest_q_10_cmpReg_q; + wire [0:0] redist9_expRMux_uid31_fpSqrtTest_q_10_notEnable_q; + wire [0:0] redist9_expRMux_uid31_fpSqrtTest_q_10_nor_q; + (* preserve_syn_only *) reg [0:0] redist9_expRMux_uid31_fpSqrtTest_q_10_sticky_ena_q; + wire [0:0] redist9_expRMux_uid31_fpSqrtTest_q_10_enaAnd_q; // signX_uid7_fpSqrtTest(BITSELECT,6)@0 assign signX_uid7_fpSqrtTest_b = a[31:31]; - // redist12_signX_uid7_fpSqrtTest_b_14(DELAY,137) - dspba_delay_ver #( .width(1), .depth(14), .reset_kind("ASYNC") ) - redist12_signX_uid7_fpSqrtTest_b_14 ( .xin(signX_uid7_fpSqrtTest_b), .xout(redist12_signX_uid7_fpSqrtTest_b_14_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + // redist10_signX_uid7_fpSqrtTest_b_1(DELAY,107) + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + redist10_signX_uid7_fpSqrtTest_b_1 ( .xin(signX_uid7_fpSqrtTest_b), .xout(redist10_signX_uid7_fpSqrtTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); // cstAllZWE_uid10_fpSqrtTest(CONSTANT,9) assign cstAllZWE_uid10_fpSqrtTest_q = 8'b00000000; - // redist13_expX_uid6_fpSqrtTest_b_13_notEnable(LOGICAL,171) - assign redist13_expX_uid6_fpSqrtTest_b_13_notEnable_q = ~ (en); - - // redist13_expX_uid6_fpSqrtTest_b_13_nor(LOGICAL,172) - assign redist13_expX_uid6_fpSqrtTest_b_13_nor_q = ~ (redist13_expX_uid6_fpSqrtTest_b_13_notEnable_q | redist13_expX_uid6_fpSqrtTest_b_13_sticky_ena_q); - - // redist13_expX_uid6_fpSqrtTest_b_13_mem_last(CONSTANT,168) - assign redist13_expX_uid6_fpSqrtTest_b_13_mem_last_q = 5'b01001; - - // redist13_expX_uid6_fpSqrtTest_b_13_cmp(LOGICAL,169) - assign redist13_expX_uid6_fpSqrtTest_b_13_cmp_b = {1'b0, redist13_expX_uid6_fpSqrtTest_b_13_rdmux_q}; - assign redist13_expX_uid6_fpSqrtTest_b_13_cmp_q = redist13_expX_uid6_fpSqrtTest_b_13_mem_last_q == redist13_expX_uid6_fpSqrtTest_b_13_cmp_b ? 1'b1 : 1'b0; - - // redist13_expX_uid6_fpSqrtTest_b_13_cmpReg(REG,170) - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - redist13_expX_uid6_fpSqrtTest_b_13_cmpReg_q <= 1'b0; - end - else if (en == 1'b1) - begin - redist13_expX_uid6_fpSqrtTest_b_13_cmpReg_q <= redist13_expX_uid6_fpSqrtTest_b_13_cmp_q; - end - end - - // redist13_expX_uid6_fpSqrtTest_b_13_sticky_ena(REG,173) - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - redist13_expX_uid6_fpSqrtTest_b_13_sticky_ena_q <= 1'b0; - end - else if (redist13_expX_uid6_fpSqrtTest_b_13_nor_q == 1'b1) - begin - redist13_expX_uid6_fpSqrtTest_b_13_sticky_ena_q <= redist13_expX_uid6_fpSqrtTest_b_13_cmpReg_q; - end - end - - // redist13_expX_uid6_fpSqrtTest_b_13_enaAnd(LOGICAL,174) - assign redist13_expX_uid6_fpSqrtTest_b_13_enaAnd_q = redist13_expX_uid6_fpSqrtTest_b_13_sticky_ena_q & en; - - // redist13_expX_uid6_fpSqrtTest_b_13_rdcnt(COUNTER,165) - // low=0, high=10, step=1, init=0 - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - redist13_expX_uid6_fpSqrtTest_b_13_rdcnt_i <= 4'd0; - redist13_expX_uid6_fpSqrtTest_b_13_rdcnt_eq <= 1'b0; - end - else if (en == 1'b1) - begin - if (redist13_expX_uid6_fpSqrtTest_b_13_rdcnt_i == 4'd9) - begin - redist13_expX_uid6_fpSqrtTest_b_13_rdcnt_eq <= 1'b1; - end - else - begin - redist13_expX_uid6_fpSqrtTest_b_13_rdcnt_eq <= 1'b0; - end - if (redist13_expX_uid6_fpSqrtTest_b_13_rdcnt_eq == 1'b1) - begin - redist13_expX_uid6_fpSqrtTest_b_13_rdcnt_i <= $unsigned(redist13_expX_uid6_fpSqrtTest_b_13_rdcnt_i) + $unsigned(4'd6); - end - else - begin - redist13_expX_uid6_fpSqrtTest_b_13_rdcnt_i <= $unsigned(redist13_expX_uid6_fpSqrtTest_b_13_rdcnt_i) + $unsigned(4'd1); - end - end - end - assign redist13_expX_uid6_fpSqrtTest_b_13_rdcnt_q = redist13_expX_uid6_fpSqrtTest_b_13_rdcnt_i[3:0]; - - // redist13_expX_uid6_fpSqrtTest_b_13_rdmux(MUX,166) - assign redist13_expX_uid6_fpSqrtTest_b_13_rdmux_s = en; - always @(redist13_expX_uid6_fpSqrtTest_b_13_rdmux_s or redist13_expX_uid6_fpSqrtTest_b_13_wraddr_q or redist13_expX_uid6_fpSqrtTest_b_13_rdcnt_q) - begin - unique case (redist13_expX_uid6_fpSqrtTest_b_13_rdmux_s) - 1'b0 : redist13_expX_uid6_fpSqrtTest_b_13_rdmux_q = redist13_expX_uid6_fpSqrtTest_b_13_wraddr_q; - 1'b1 : redist13_expX_uid6_fpSqrtTest_b_13_rdmux_q = redist13_expX_uid6_fpSqrtTest_b_13_rdcnt_q; - default : redist13_expX_uid6_fpSqrtTest_b_13_rdmux_q = 4'b0; - endcase - end - - // VCC(CONSTANT,1) - assign VCC_q = 1'b1; - // expX_uid6_fpSqrtTest(BITSELECT,5)@0 assign expX_uid6_fpSqrtTest_b = a[30:23]; - // redist13_expX_uid6_fpSqrtTest_b_13_wraddr(REG,167) - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - redist13_expX_uid6_fpSqrtTest_b_13_wraddr_q <= 4'b1010; - end - else - begin - redist13_expX_uid6_fpSqrtTest_b_13_wraddr_q <= redist13_expX_uid6_fpSqrtTest_b_13_rdmux_q; - end - end - - // redist13_expX_uid6_fpSqrtTest_b_13_mem(DUALMEM,164) - assign redist13_expX_uid6_fpSqrtTest_b_13_mem_ia = expX_uid6_fpSqrtTest_b; - assign redist13_expX_uid6_fpSqrtTest_b_13_mem_aa = redist13_expX_uid6_fpSqrtTest_b_13_wraddr_q; - assign redist13_expX_uid6_fpSqrtTest_b_13_mem_ab = redist13_expX_uid6_fpSqrtTest_b_13_rdmux_q; - assign redist13_expX_uid6_fpSqrtTest_b_13_mem_reset0 = areset; - altera_syncram #( - .ram_block_type("MLAB"), - .operation_mode("DUAL_PORT"), - .width_a(8), - .widthad_a(4), - .numwords_a(11), - .width_b(8), - .widthad_b(4), - .numwords_b(11), - .lpm_type("altera_syncram"), - .width_byteena_a(1), - .address_reg_b("CLOCK0"), - .indata_reg_b("CLOCK0"), - .rdcontrol_reg_b("CLOCK0"), - .byteena_reg_b("CLOCK0"), - .outdata_reg_b("CLOCK1"), - .outdata_aclr_b("CLEAR1"), - .clock_enable_input_a("NORMAL"), - .clock_enable_input_b("NORMAL"), - .clock_enable_output_b("NORMAL"), - .read_during_write_mode_mixed_ports("DONT_CARE"), - .power_up_uninitialized("TRUE"), - .intended_device_family("Arria 10") - ) redist13_expX_uid6_fpSqrtTest_b_13_mem_dmem ( - .clocken1(redist13_expX_uid6_fpSqrtTest_b_13_enaAnd_q[0]), - .clocken0(VCC_q[0]), - .clock0(clk), - .aclr1(redist13_expX_uid6_fpSqrtTest_b_13_mem_reset0), - .clock1(clk), - .address_a(redist13_expX_uid6_fpSqrtTest_b_13_mem_aa), - .data_a(redist13_expX_uid6_fpSqrtTest_b_13_mem_ia), - .wren_a(en[0]), - .address_b(redist13_expX_uid6_fpSqrtTest_b_13_mem_ab), - .q_b(redist13_expX_uid6_fpSqrtTest_b_13_mem_iq), - .wren_b(), - .rden_a(), - .rden_b(), - .data_b(), - .clocken2(), - .clocken3(), - .aclr0(), - .addressstall_a(), - .addressstall_b(), - .byteena_a(), - .byteena_b(), - .eccencbypass(), - .eccencparity(), - .sclr(), - .address2_a(), - .address2_b(), - .q_a(), - .eccstatus() - ); - assign redist13_expX_uid6_fpSqrtTest_b_13_mem_q = redist13_expX_uid6_fpSqrtTest_b_13_mem_iq[7:0]; - - // redist13_expX_uid6_fpSqrtTest_b_13_outputreg(DELAY,163) - dspba_delay_ver #( .width(8), .depth(1), .reset_kind("ASYNC") ) - redist13_expX_uid6_fpSqrtTest_b_13_outputreg ( .xin(redist13_expX_uid6_fpSqrtTest_b_13_mem_q), .xout(redist13_expX_uid6_fpSqrtTest_b_13_outputreg_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // excZ_x_uid13_fpSqrtTest(LOGICAL,12)@13 + 1 - assign excZ_x_uid13_fpSqrtTest_qi = redist13_expX_uid6_fpSqrtTest_b_13_outputreg_q == cstAllZWE_uid10_fpSqrtTest_q ? 1'b1 : 1'b0; + // excZ_x_uid13_fpSqrtTest(LOGICAL,12)@0 + 1 + assign excZ_x_uid13_fpSqrtTest_qi = expX_uid6_fpSqrtTest_b == cstAllZWE_uid10_fpSqrtTest_q ? 1'b1 : 1'b0; dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) excZ_x_uid13_fpSqrtTest_delay ( .xin(excZ_x_uid13_fpSqrtTest_qi), .xout(excZ_x_uid13_fpSqrtTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - // negZero_uid85_fpSqrtTest(LOGICAL,84)@14 + 1 - assign negZero_uid85_fpSqrtTest_qi = excZ_x_uid13_fpSqrtTest_q & redist12_signX_uid7_fpSqrtTest_b_14_q; + // negZero_uid59_fpSqrtTest(LOGICAL,58)@1 + 1 + assign negZero_uid59_fpSqrtTest_qi = excZ_x_uid13_fpSqrtTest_q & redist10_signX_uid7_fpSqrtTest_b_1_q; dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - negZero_uid85_fpSqrtTest_delay ( .xin(negZero_uid85_fpSqrtTest_qi), .xout(negZero_uid85_fpSqrtTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + negZero_uid59_fpSqrtTest_delay ( .xin(negZero_uid59_fpSqrtTest_qi), .xout(negZero_uid59_fpSqrtTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist1_negZero_uid59_fpSqrtTest_q_9(DELAY,98) + dspba_delay_ver #( .width(1), .depth(8), .reset_kind("ASYNC") ) + redist1_negZero_uid59_fpSqrtTest_q_9 ( .xin(negZero_uid59_fpSqrtTest_q), .xout(redist1_negZero_uid59_fpSqrtTest_q_9_q), .ena(en[0]), .clk(clk), .aclr(areset) ); // cstAllOWE_uid8_fpSqrtTest(CONSTANT,7) assign cstAllOWE_uid8_fpSqrtTest_q = 8'b11111111; - // GND(CONSTANT,0) - assign GND_q = 1'b0; - - // redist11_frac_x_uid12_fpSqrtTest_b_13_notEnable(LOGICAL,159) - assign redist11_frac_x_uid12_fpSqrtTest_b_13_notEnable_q = ~ (en); - - // redist11_frac_x_uid12_fpSqrtTest_b_13_nor(LOGICAL,160) - assign redist11_frac_x_uid12_fpSqrtTest_b_13_nor_q = ~ (redist11_frac_x_uid12_fpSqrtTest_b_13_notEnable_q | redist11_frac_x_uid12_fpSqrtTest_b_13_sticky_ena_q); - - // redist11_frac_x_uid12_fpSqrtTest_b_13_mem_last(CONSTANT,156) - assign redist11_frac_x_uid12_fpSqrtTest_b_13_mem_last_q = 4'b0111; - - // redist11_frac_x_uid12_fpSqrtTest_b_13_cmp(LOGICAL,157) - assign redist11_frac_x_uid12_fpSqrtTest_b_13_cmp_q = redist11_frac_x_uid12_fpSqrtTest_b_13_mem_last_q == redist11_frac_x_uid12_fpSqrtTest_b_13_rdmux_q ? 1'b1 : 1'b0; - - // redist11_frac_x_uid12_fpSqrtTest_b_13_cmpReg(REG,158) - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - redist11_frac_x_uid12_fpSqrtTest_b_13_cmpReg_q <= 1'b0; - end - else if (en == 1'b1) - begin - redist11_frac_x_uid12_fpSqrtTest_b_13_cmpReg_q <= redist11_frac_x_uid12_fpSqrtTest_b_13_cmp_q; - end - end - - // redist11_frac_x_uid12_fpSqrtTest_b_13_sticky_ena(REG,161) - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - redist11_frac_x_uid12_fpSqrtTest_b_13_sticky_ena_q <= 1'b0; - end - else if (redist11_frac_x_uid12_fpSqrtTest_b_13_nor_q == 1'b1) - begin - redist11_frac_x_uid12_fpSqrtTest_b_13_sticky_ena_q <= redist11_frac_x_uid12_fpSqrtTest_b_13_cmpReg_q; - end - end - - // redist11_frac_x_uid12_fpSqrtTest_b_13_enaAnd(LOGICAL,162) - assign redist11_frac_x_uid12_fpSqrtTest_b_13_enaAnd_q = redist11_frac_x_uid12_fpSqrtTest_b_13_sticky_ena_q & en; - - // redist11_frac_x_uid12_fpSqrtTest_b_13_rdcnt(COUNTER,153) - // low=0, high=8, step=1, init=0 - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - redist11_frac_x_uid12_fpSqrtTest_b_13_rdcnt_i <= 4'd0; - redist11_frac_x_uid12_fpSqrtTest_b_13_rdcnt_eq <= 1'b0; - end - else if (en == 1'b1) - begin - if (redist11_frac_x_uid12_fpSqrtTest_b_13_rdcnt_i == 4'd7) - begin - redist11_frac_x_uid12_fpSqrtTest_b_13_rdcnt_eq <= 1'b1; - end - else - begin - redist11_frac_x_uid12_fpSqrtTest_b_13_rdcnt_eq <= 1'b0; - end - if (redist11_frac_x_uid12_fpSqrtTest_b_13_rdcnt_eq == 1'b1) - begin - redist11_frac_x_uid12_fpSqrtTest_b_13_rdcnt_i <= $unsigned(redist11_frac_x_uid12_fpSqrtTest_b_13_rdcnt_i) + $unsigned(4'd8); - end - else - begin - redist11_frac_x_uid12_fpSqrtTest_b_13_rdcnt_i <= $unsigned(redist11_frac_x_uid12_fpSqrtTest_b_13_rdcnt_i) + $unsigned(4'd1); - end - end - end - assign redist11_frac_x_uid12_fpSqrtTest_b_13_rdcnt_q = redist11_frac_x_uid12_fpSqrtTest_b_13_rdcnt_i[3:0]; - - // redist11_frac_x_uid12_fpSqrtTest_b_13_rdmux(MUX,154) - assign redist11_frac_x_uid12_fpSqrtTest_b_13_rdmux_s = en; - always @(redist11_frac_x_uid12_fpSqrtTest_b_13_rdmux_s or redist11_frac_x_uid12_fpSqrtTest_b_13_wraddr_q or redist11_frac_x_uid12_fpSqrtTest_b_13_rdcnt_q) - begin - unique case (redist11_frac_x_uid12_fpSqrtTest_b_13_rdmux_s) - 1'b0 : redist11_frac_x_uid12_fpSqrtTest_b_13_rdmux_q = redist11_frac_x_uid12_fpSqrtTest_b_13_wraddr_q; - 1'b1 : redist11_frac_x_uid12_fpSqrtTest_b_13_rdmux_q = redist11_frac_x_uid12_fpSqrtTest_b_13_rdcnt_q; - default : redist11_frac_x_uid12_fpSqrtTest_b_13_rdmux_q = 4'b0; - endcase - end - - // frac_x_uid12_fpSqrtTest(BITSELECT,11)@0 - assign frac_x_uid12_fpSqrtTest_b = a[22:0]; - - // redist10_frac_x_uid12_fpSqrtTest_b_2(DELAY,135) - dspba_delay_ver #( .width(23), .depth(2), .reset_kind("ASYNC") ) - redist10_frac_x_uid12_fpSqrtTest_b_2 ( .xin(frac_x_uid12_fpSqrtTest_b), .xout(redist10_frac_x_uid12_fpSqrtTest_b_2_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // redist11_frac_x_uid12_fpSqrtTest_b_13_wraddr(REG,155) - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - redist11_frac_x_uid12_fpSqrtTest_b_13_wraddr_q <= 4'b1000; - end - else - begin - redist11_frac_x_uid12_fpSqrtTest_b_13_wraddr_q <= redist11_frac_x_uid12_fpSqrtTest_b_13_rdmux_q; - end - end - - // redist11_frac_x_uid12_fpSqrtTest_b_13_mem(DUALMEM,152) - assign redist11_frac_x_uid12_fpSqrtTest_b_13_mem_ia = redist10_frac_x_uid12_fpSqrtTest_b_2_q; - assign redist11_frac_x_uid12_fpSqrtTest_b_13_mem_aa = redist11_frac_x_uid12_fpSqrtTest_b_13_wraddr_q; - assign redist11_frac_x_uid12_fpSqrtTest_b_13_mem_ab = redist11_frac_x_uid12_fpSqrtTest_b_13_rdmux_q; - assign redist11_frac_x_uid12_fpSqrtTest_b_13_mem_reset0 = areset; - altera_syncram #( - .ram_block_type("MLAB"), - .operation_mode("DUAL_PORT"), - .width_a(23), - .widthad_a(4), - .numwords_a(9), - .width_b(23), - .widthad_b(4), - .numwords_b(9), - .lpm_type("altera_syncram"), - .width_byteena_a(1), - .address_reg_b("CLOCK0"), - .indata_reg_b("CLOCK0"), - .rdcontrol_reg_b("CLOCK0"), - .byteena_reg_b("CLOCK0"), - .outdata_reg_b("CLOCK1"), - .outdata_aclr_b("CLEAR1"), - .clock_enable_input_a("NORMAL"), - .clock_enable_input_b("NORMAL"), - .clock_enable_output_b("NORMAL"), - .read_during_write_mode_mixed_ports("DONT_CARE"), - .power_up_uninitialized("TRUE"), - .intended_device_family("Arria 10") - ) redist11_frac_x_uid12_fpSqrtTest_b_13_mem_dmem ( - .clocken1(redist11_frac_x_uid12_fpSqrtTest_b_13_enaAnd_q[0]), - .clocken0(VCC_q[0]), - .clock0(clk), - .aclr1(redist11_frac_x_uid12_fpSqrtTest_b_13_mem_reset0), - .clock1(clk), - .address_a(redist11_frac_x_uid12_fpSqrtTest_b_13_mem_aa), - .data_a(redist11_frac_x_uid12_fpSqrtTest_b_13_mem_ia), - .wren_a(en[0]), - .address_b(redist11_frac_x_uid12_fpSqrtTest_b_13_mem_ab), - .q_b(redist11_frac_x_uid12_fpSqrtTest_b_13_mem_iq), - .wren_b(), - .rden_a(), - .rden_b(), - .data_b(), - .clocken2(), - .clocken3(), - .aclr0(), - .addressstall_a(), - .addressstall_b(), - .byteena_a(), - .byteena_b(), - .eccencbypass(), - .eccencparity(), - .sclr(), - .address2_a(), - .address2_b(), - .q_a(), - .eccstatus() - ); - assign redist11_frac_x_uid12_fpSqrtTest_b_13_mem_q = redist11_frac_x_uid12_fpSqrtTest_b_13_mem_iq[22:0]; - - // redist11_frac_x_uid12_fpSqrtTest_b_13_outputreg(DELAY,151) - dspba_delay_ver #( .width(23), .depth(1), .reset_kind("ASYNC") ) - redist11_frac_x_uid12_fpSqrtTest_b_13_outputreg ( .xin(redist11_frac_x_uid12_fpSqrtTest_b_13_mem_q), .xout(redist11_frac_x_uid12_fpSqrtTest_b_13_outputreg_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // oFracX_uid44_fpSqrtTest(BITJOIN,43)@13 - assign oFracX_uid44_fpSqrtTest_q = {VCC_q, redist11_frac_x_uid12_fpSqrtTest_b_13_outputreg_q}; - - // oFracXZ_mergedSignalTM_uid47_fpSqrtTest(BITJOIN,46)@13 - assign oFracXZ_mergedSignalTM_uid47_fpSqrtTest_q = {oFracX_uid44_fpSqrtTest_q, GND_q}; - - // oFracXSignExt_mergedSignalTM_uid52_fpSqrtTest(BITJOIN,51)@13 - assign oFracXSignExt_mergedSignalTM_uid52_fpSqrtTest_q = {GND_q, oFracX_uid44_fpSqrtTest_q}; - // expX0PS_uid29_fpSqrtTest(BITSELECT,28)@0 assign expX0PS_uid29_fpSqrtTest_in = expX_uid6_fpSqrtTest_b[0:0]; assign expX0PS_uid29_fpSqrtTest_b = expX0PS_uid29_fpSqrtTest_in[0:0]; @@ -655,26 +254,8 @@ module acl_fsqrt ( // expOddSelect_uid30_fpSqrtTest(LOGICAL,29)@0 assign expOddSelect_uid30_fpSqrtTest_q = ~ (expX0PS_uid29_fpSqrtTest_b); - // redist9_expOddSelect_uid30_fpSqrtTest_q_13(DELAY,134) - dspba_delay_ver #( .width(1), .depth(13), .reset_kind("ASYNC") ) - redist9_expOddSelect_uid30_fpSqrtTest_q_13 ( .xin(expOddSelect_uid30_fpSqrtTest_q), .xout(redist9_expOddSelect_uid30_fpSqrtTest_q_13_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // normalizedXForComp_uid54_fpSqrtTest(MUX,53)@13 - assign normalizedXForComp_uid54_fpSqrtTest_s = redist9_expOddSelect_uid30_fpSqrtTest_q_13_q; - always @(normalizedXForComp_uid54_fpSqrtTest_s or en or oFracXSignExt_mergedSignalTM_uid52_fpSqrtTest_q or oFracXZ_mergedSignalTM_uid47_fpSqrtTest_q) - begin - unique case (normalizedXForComp_uid54_fpSqrtTest_s) - 1'b0 : normalizedXForComp_uid54_fpSqrtTest_q = oFracXSignExt_mergedSignalTM_uid52_fpSqrtTest_q; - 1'b1 : normalizedXForComp_uid54_fpSqrtTest_q = oFracXZ_mergedSignalTM_uid47_fpSqrtTest_q; - default : normalizedXForComp_uid54_fpSqrtTest_q = 25'b0; - endcase - end - - // paddingY_uid55_fpSqrtTest(CONSTANT,54) - assign paddingY_uid55_fpSqrtTest_q = 25'b0000000000000000000000000; - - // updatedY_uid56_fpSqrtTest(BITJOIN,55)@13 - assign updatedY_uid56_fpSqrtTest_q = {normalizedXForComp_uid54_fpSqrtTest_q, paddingY_uid55_fpSqrtTest_q}; + // frac_x_uid12_fpSqrtTest(BITSELECT,11)@0 + assign frac_x_uid12_fpSqrtTest_b = a[22:0]; // addrFull_uid33_fpSqrtTest(BITJOIN,32)@0 assign addrFull_uid33_fpSqrtTest_q = {expOddSelect_uid30_fpSqrtTest_q, frac_x_uid12_fpSqrtTest_b}; @@ -682,10 +263,10 @@ module acl_fsqrt ( // yAddr_uid35_fpSqrtTest(BITSELECT,34)@0 assign yAddr_uid35_fpSqrtTest_b = addrFull_uid33_fpSqrtTest_q[23:16]; - // memoryC2_uid94_sqrtTables_lutmem(DUALMEM,120)@0 + 2 + // memoryC2_uid68_sqrtTables_lutmem(DUALMEM,94)@0 + 2 // in j@20000000 - assign memoryC2_uid94_sqrtTables_lutmem_aa = yAddr_uid35_fpSqrtTest_b; - assign memoryC2_uid94_sqrtTables_lutmem_reset0 = areset; + assign memoryC2_uid68_sqrtTables_lutmem_aa = yAddr_uid35_fpSqrtTest_b; + assign memoryC2_uid68_sqrtTables_lutmem_reset0 = areset; altera_syncram #( .ram_block_type("M20K"), .operation_mode("ROM"), @@ -698,15 +279,15 @@ module acl_fsqrt ( .outdata_aclr_a("CLEAR0"), .clock_enable_input_a("NORMAL"), .power_up_uninitialized("FALSE"), - .init_file("acl_fsqrt_memoryC2_uid94_sqrtTables_lutmem.hex"), + .init_file("acl_fsqrt_memoryC2_uid68_sqrtTables_lutmem.hex"), .init_file_layout("PORT_A"), .intended_device_family("Arria 10") - ) memoryC2_uid94_sqrtTables_lutmem_dmem ( + ) memoryC2_uid68_sqrtTables_lutmem_dmem ( .clocken0(en[0]), - .aclr0(memoryC2_uid94_sqrtTables_lutmem_reset0), + .aclr0(memoryC2_uid68_sqrtTables_lutmem_reset0), .clock0(clk), - .address_a(memoryC2_uid94_sqrtTables_lutmem_aa), - .q_a(memoryC2_uid94_sqrtTables_lutmem_ir), + .address_a(memoryC2_uid68_sqrtTables_lutmem_aa), + .q_a(memoryC2_uid68_sqrtTables_lutmem_ir), .wren_a(), .wren_b(), .rden_a(), @@ -731,39 +312,43 @@ module acl_fsqrt ( .q_b(), .eccstatus() ); - assign memoryC2_uid94_sqrtTables_lutmem_r = memoryC2_uid94_sqrtTables_lutmem_ir[11:0]; + assign memoryC2_uid68_sqrtTables_lutmem_r = memoryC2_uid68_sqrtTables_lutmem_ir[11:0]; - // yForPe_uid36_fpSqrtTest(BITSELECT,35)@2 - assign yForPe_uid36_fpSqrtTest_in = redist10_frac_x_uid12_fpSqrtTest_b_2_q[15:0]; + // yForPe_uid36_fpSqrtTest(BITSELECT,35)@0 + assign yForPe_uid36_fpSqrtTest_in = frac_x_uid12_fpSqrtTest_b[15:0]; assign yForPe_uid36_fpSqrtTest_b = yForPe_uid36_fpSqrtTest_in[15:0]; - // yT1_uid100_invPolyEval(BITSELECT,99)@2 - assign yT1_uid100_invPolyEval_b = yForPe_uid36_fpSqrtTest_b[15:4]; + // redist5_yForPe_uid36_fpSqrtTest_b_2(DELAY,102) + dspba_delay_ver #( .width(16), .depth(2), .reset_kind("ASYNC") ) + redist5_yForPe_uid36_fpSqrtTest_b_2 ( .xin(yForPe_uid36_fpSqrtTest_b), .xout(redist5_yForPe_uid36_fpSqrtTest_b_2_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - // prodXY_uid113_pT1_uid101_invPolyEval_cma(CHAINMULTADD,122)@2 + 3 - assign prodXY_uid113_pT1_uid101_invPolyEval_cma_reset = areset; - assign prodXY_uid113_pT1_uid101_invPolyEval_cma_ena0 = en[0]; - assign prodXY_uid113_pT1_uid101_invPolyEval_cma_ena1 = prodXY_uid113_pT1_uid101_invPolyEval_cma_ena0; - assign prodXY_uid113_pT1_uid101_invPolyEval_cma_ena2 = prodXY_uid113_pT1_uid101_invPolyEval_cma_ena0; - assign prodXY_uid113_pT1_uid101_invPolyEval_cma_l[0] = $signed({1'b0, prodXY_uid113_pT1_uid101_invPolyEval_cma_a1[0][11:0]}); - assign prodXY_uid113_pT1_uid101_invPolyEval_cma_p[0] = prodXY_uid113_pT1_uid101_invPolyEval_cma_l[0] * prodXY_uid113_pT1_uid101_invPolyEval_cma_c1[0]; - assign prodXY_uid113_pT1_uid101_invPolyEval_cma_u[0] = prodXY_uid113_pT1_uid101_invPolyEval_cma_p[0][24:0]; - assign prodXY_uid113_pT1_uid101_invPolyEval_cma_w[0] = prodXY_uid113_pT1_uid101_invPolyEval_cma_u[0]; - assign prodXY_uid113_pT1_uid101_invPolyEval_cma_x[0] = prodXY_uid113_pT1_uid101_invPolyEval_cma_w[0]; - assign prodXY_uid113_pT1_uid101_invPolyEval_cma_y[0] = prodXY_uid113_pT1_uid101_invPolyEval_cma_x[0]; + // yT1_uid74_invPolyEval(BITSELECT,73)@2 + assign yT1_uid74_invPolyEval_b = redist5_yForPe_uid36_fpSqrtTest_b_2_q[15:4]; + + // prodXY_uid87_pT1_uid75_invPolyEval_cma(CHAINMULTADD,95)@2 + 3 + assign prodXY_uid87_pT1_uid75_invPolyEval_cma_reset = areset; + assign prodXY_uid87_pT1_uid75_invPolyEval_cma_ena0 = en[0]; + assign prodXY_uid87_pT1_uid75_invPolyEval_cma_ena1 = prodXY_uid87_pT1_uid75_invPolyEval_cma_ena0; + assign prodXY_uid87_pT1_uid75_invPolyEval_cma_ena2 = prodXY_uid87_pT1_uid75_invPolyEval_cma_ena0; + assign prodXY_uid87_pT1_uid75_invPolyEval_cma_l[0] = $signed({1'b0, prodXY_uid87_pT1_uid75_invPolyEval_cma_a1[0][11:0]}); + assign prodXY_uid87_pT1_uid75_invPolyEval_cma_p[0] = prodXY_uid87_pT1_uid75_invPolyEval_cma_l[0] * prodXY_uid87_pT1_uid75_invPolyEval_cma_c1[0]; + assign prodXY_uid87_pT1_uid75_invPolyEval_cma_u[0] = prodXY_uid87_pT1_uid75_invPolyEval_cma_p[0][24:0]; + assign prodXY_uid87_pT1_uid75_invPolyEval_cma_w[0] = prodXY_uid87_pT1_uid75_invPolyEval_cma_u[0]; + assign prodXY_uid87_pT1_uid75_invPolyEval_cma_x[0] = prodXY_uid87_pT1_uid75_invPolyEval_cma_w[0]; + assign prodXY_uid87_pT1_uid75_invPolyEval_cma_y[0] = prodXY_uid87_pT1_uid75_invPolyEval_cma_x[0]; always @ (posedge clk or posedge areset) begin if (areset) begin - prodXY_uid113_pT1_uid101_invPolyEval_cma_a0 <= '{default: '0}; - prodXY_uid113_pT1_uid101_invPolyEval_cma_c0 <= '{default: '0}; + prodXY_uid87_pT1_uid75_invPolyEval_cma_a0 <= '{default: '0}; + prodXY_uid87_pT1_uid75_invPolyEval_cma_c0 <= '{default: '0}; end else begin - if (prodXY_uid113_pT1_uid101_invPolyEval_cma_ena0 == 1'b1) + if (prodXY_uid87_pT1_uid75_invPolyEval_cma_ena0 == 1'b1) begin - prodXY_uid113_pT1_uid101_invPolyEval_cma_a0[0] <= yT1_uid100_invPolyEval_b; - prodXY_uid113_pT1_uid101_invPolyEval_cma_c0[0] <= memoryC2_uid94_sqrtTables_lutmem_r; + prodXY_uid87_pT1_uid75_invPolyEval_cma_a0[0] <= yT1_uid74_invPolyEval_b; + prodXY_uid87_pT1_uid75_invPolyEval_cma_c0[0] <= memoryC2_uid68_sqrtTables_lutmem_r; end end end @@ -771,15 +356,15 @@ module acl_fsqrt ( begin if (areset) begin - prodXY_uid113_pT1_uid101_invPolyEval_cma_a1 <= '{default: '0}; - prodXY_uid113_pT1_uid101_invPolyEval_cma_c1 <= '{default: '0}; + prodXY_uid87_pT1_uid75_invPolyEval_cma_a1 <= '{default: '0}; + prodXY_uid87_pT1_uid75_invPolyEval_cma_c1 <= '{default: '0}; end else begin - if (prodXY_uid113_pT1_uid101_invPolyEval_cma_ena2 == 1'b1) + if (prodXY_uid87_pT1_uid75_invPolyEval_cma_ena2 == 1'b1) begin - prodXY_uid113_pT1_uid101_invPolyEval_cma_a1 <= prodXY_uid113_pT1_uid101_invPolyEval_cma_a0; - prodXY_uid113_pT1_uid101_invPolyEval_cma_c1 <= prodXY_uid113_pT1_uid101_invPolyEval_cma_c0; + prodXY_uid87_pT1_uid75_invPolyEval_cma_a1 <= prodXY_uid87_pT1_uid75_invPolyEval_cma_a0; + prodXY_uid87_pT1_uid75_invPolyEval_cma_c1 <= prodXY_uid87_pT1_uid75_invPolyEval_cma_c0; end end end @@ -787,34 +372,34 @@ module acl_fsqrt ( begin if (areset) begin - prodXY_uid113_pT1_uid101_invPolyEval_cma_s <= '{default: '0}; + prodXY_uid87_pT1_uid75_invPolyEval_cma_s <= '{default: '0}; end else begin - if (prodXY_uid113_pT1_uid101_invPolyEval_cma_ena1 == 1'b1) + if (prodXY_uid87_pT1_uid75_invPolyEval_cma_ena1 == 1'b1) begin - prodXY_uid113_pT1_uid101_invPolyEval_cma_s[0] <= prodXY_uid113_pT1_uid101_invPolyEval_cma_y[0]; + prodXY_uid87_pT1_uid75_invPolyEval_cma_s[0] <= prodXY_uid87_pT1_uid75_invPolyEval_cma_y[0]; end end end dspba_delay_ver #( .width(24), .depth(0), .reset_kind("ASYNC") ) - prodXY_uid113_pT1_uid101_invPolyEval_cma_delay ( .xin(prodXY_uid113_pT1_uid101_invPolyEval_cma_s[0][23:0]), .xout(prodXY_uid113_pT1_uid101_invPolyEval_cma_qq), .ena(en[0]), .clk(clk), .aclr(areset) ); - assign prodXY_uid113_pT1_uid101_invPolyEval_cma_q = prodXY_uid113_pT1_uid101_invPolyEval_cma_qq[23:0]; + prodXY_uid87_pT1_uid75_invPolyEval_cma_delay ( .xin(prodXY_uid87_pT1_uid75_invPolyEval_cma_s[0][23:0]), .xout(prodXY_uid87_pT1_uid75_invPolyEval_cma_qq), .ena(en[0]), .clk(clk), .aclr(areset) ); + assign prodXY_uid87_pT1_uid75_invPolyEval_cma_q = prodXY_uid87_pT1_uid75_invPolyEval_cma_qq[23:0]; - // osig_uid114_pT1_uid101_invPolyEval(BITSELECT,113)@5 - assign osig_uid114_pT1_uid101_invPolyEval_b = prodXY_uid113_pT1_uid101_invPolyEval_cma_q[23:11]; + // osig_uid88_pT1_uid75_invPolyEval(BITSELECT,87)@5 + assign osig_uid88_pT1_uid75_invPolyEval_b = prodXY_uid87_pT1_uid75_invPolyEval_cma_q[23:11]; - // highBBits_uid103_invPolyEval(BITSELECT,102)@5 - assign highBBits_uid103_invPolyEval_b = osig_uid114_pT1_uid101_invPolyEval_b[12:1]; + // highBBits_uid77_invPolyEval(BITSELECT,76)@5 + assign highBBits_uid77_invPolyEval_b = osig_uid88_pT1_uid75_invPolyEval_b[12:1]; - // redist6_yAddr_uid35_fpSqrtTest_b_3(DELAY,131) + // redist7_yAddr_uid35_fpSqrtTest_b_3(DELAY,104) dspba_delay_ver #( .width(8), .depth(3), .reset_kind("ASYNC") ) - redist6_yAddr_uid35_fpSqrtTest_b_3 ( .xin(yAddr_uid35_fpSqrtTest_b), .xout(redist6_yAddr_uid35_fpSqrtTest_b_3_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + redist7_yAddr_uid35_fpSqrtTest_b_3 ( .xin(yAddr_uid35_fpSqrtTest_b), .xout(redist7_yAddr_uid35_fpSqrtTest_b_3_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - // memoryC1_uid91_sqrtTables_lutmem(DUALMEM,119)@3 + 2 + // memoryC1_uid65_sqrtTables_lutmem(DUALMEM,93)@3 + 2 // in j@20000000 - assign memoryC1_uid91_sqrtTables_lutmem_aa = redist6_yAddr_uid35_fpSqrtTest_b_3_q; - assign memoryC1_uid91_sqrtTables_lutmem_reset0 = areset; + assign memoryC1_uid65_sqrtTables_lutmem_aa = redist7_yAddr_uid35_fpSqrtTest_b_3_q; + assign memoryC1_uid65_sqrtTables_lutmem_reset0 = areset; altera_syncram #( .ram_block_type("M20K"), .operation_mode("ROM"), @@ -827,15 +412,15 @@ module acl_fsqrt ( .outdata_aclr_a("CLEAR0"), .clock_enable_input_a("NORMAL"), .power_up_uninitialized("FALSE"), - .init_file("acl_fsqrt_memoryC1_uid91_sqrtTables_lutmem.hex"), + .init_file("acl_fsqrt_memoryC1_uid65_sqrtTables_lutmem.hex"), .init_file_layout("PORT_A"), .intended_device_family("Arria 10") - ) memoryC1_uid91_sqrtTables_lutmem_dmem ( + ) memoryC1_uid65_sqrtTables_lutmem_dmem ( .clocken0(en[0]), - .aclr0(memoryC1_uid91_sqrtTables_lutmem_reset0), + .aclr0(memoryC1_uid65_sqrtTables_lutmem_reset0), .clock0(clk), - .address_a(memoryC1_uid91_sqrtTables_lutmem_aa), - .q_a(memoryC1_uid91_sqrtTables_lutmem_ir), + .address_a(memoryC1_uid65_sqrtTables_lutmem_aa), + .q_a(memoryC1_uid65_sqrtTables_lutmem_ir), .wren_a(), .wren_b(), .rden_a(), @@ -860,136 +445,139 @@ module acl_fsqrt ( .q_b(), .eccstatus() ); - assign memoryC1_uid91_sqrtTables_lutmem_r = memoryC1_uid91_sqrtTables_lutmem_ir[20:0]; + assign memoryC1_uid65_sqrtTables_lutmem_r = memoryC1_uid65_sqrtTables_lutmem_ir[20:0]; - // s1sumAHighB_uid104_invPolyEval(ADD,103)@5 + 1 - assign s1sumAHighB_uid104_invPolyEval_a = {{1{memoryC1_uid91_sqrtTables_lutmem_r[20]}}, memoryC1_uid91_sqrtTables_lutmem_r}; - assign s1sumAHighB_uid104_invPolyEval_b = {{10{highBBits_uid103_invPolyEval_b[11]}}, highBBits_uid103_invPolyEval_b}; + // s1sumAHighB_uid78_invPolyEval(ADD,77)@5 + 1 + assign s1sumAHighB_uid78_invPolyEval_a = {{1{memoryC1_uid65_sqrtTables_lutmem_r[20]}}, memoryC1_uid65_sqrtTables_lutmem_r}; + assign s1sumAHighB_uid78_invPolyEval_b = {{10{highBBits_uid77_invPolyEval_b[11]}}, highBBits_uid77_invPolyEval_b}; always @ (posedge clk or posedge areset) begin if (areset) begin - s1sumAHighB_uid104_invPolyEval_o <= 22'b0; + s1sumAHighB_uid78_invPolyEval_o <= 22'b0; end else if (en == 1'b1) begin - s1sumAHighB_uid104_invPolyEval_o <= $signed(s1sumAHighB_uid104_invPolyEval_a) + $signed(s1sumAHighB_uid104_invPolyEval_b); + s1sumAHighB_uid78_invPolyEval_o <= $signed(s1sumAHighB_uid78_invPolyEval_a) + $signed(s1sumAHighB_uid78_invPolyEval_b); end end - assign s1sumAHighB_uid104_invPolyEval_q = s1sumAHighB_uid104_invPolyEval_o[21:0]; + assign s1sumAHighB_uid78_invPolyEval_q = s1sumAHighB_uid78_invPolyEval_o[21:0]; - // lowRangeB_uid102_invPolyEval(BITSELECT,101)@5 - assign lowRangeB_uid102_invPolyEval_in = osig_uid114_pT1_uid101_invPolyEval_b[0:0]; - assign lowRangeB_uid102_invPolyEval_b = lowRangeB_uid102_invPolyEval_in[0:0]; + // lowRangeB_uid76_invPolyEval(BITSELECT,75)@5 + assign lowRangeB_uid76_invPolyEval_in = osig_uid88_pT1_uid75_invPolyEval_b[0:0]; + assign lowRangeB_uid76_invPolyEval_b = lowRangeB_uid76_invPolyEval_in[0:0]; - // redist1_lowRangeB_uid102_invPolyEval_b_1(DELAY,126) + // redist0_lowRangeB_uid76_invPolyEval_b_1(DELAY,97) dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - redist1_lowRangeB_uid102_invPolyEval_b_1 ( .xin(lowRangeB_uid102_invPolyEval_b), .xout(redist1_lowRangeB_uid102_invPolyEval_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + redist0_lowRangeB_uid76_invPolyEval_b_1 ( .xin(lowRangeB_uid76_invPolyEval_b), .xout(redist0_lowRangeB_uid76_invPolyEval_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - // s1_uid105_invPolyEval(BITJOIN,104)@6 - assign s1_uid105_invPolyEval_q = {s1sumAHighB_uid104_invPolyEval_q, redist1_lowRangeB_uid102_invPolyEval_b_1_q}; + // s1_uid79_invPolyEval(BITJOIN,78)@6 + assign s1_uid79_invPolyEval_q = {s1sumAHighB_uid78_invPolyEval_q, redist0_lowRangeB_uid76_invPolyEval_b_1_q}; - // redist5_yForPe_uid36_fpSqrtTest_b_4_notEnable(LOGICAL,147) - assign redist5_yForPe_uid36_fpSqrtTest_b_4_notEnable_q = ~ (en); + // redist6_yForPe_uid36_fpSqrtTest_b_6_notEnable(LOGICAL,115) + assign redist6_yForPe_uid36_fpSqrtTest_b_6_notEnable_q = ~ (en); - // redist5_yForPe_uid36_fpSqrtTest_b_4_nor(LOGICAL,148) - assign redist5_yForPe_uid36_fpSqrtTest_b_4_nor_q = ~ (redist5_yForPe_uid36_fpSqrtTest_b_4_notEnable_q | redist5_yForPe_uid36_fpSqrtTest_b_4_sticky_ena_q); + // redist6_yForPe_uid36_fpSqrtTest_b_6_nor(LOGICAL,116) + assign redist6_yForPe_uid36_fpSqrtTest_b_6_nor_q = ~ (redist6_yForPe_uid36_fpSqrtTest_b_6_notEnable_q | redist6_yForPe_uid36_fpSqrtTest_b_6_sticky_ena_q); - // redist5_yForPe_uid36_fpSqrtTest_b_4_mem_last(CONSTANT,144) - assign redist5_yForPe_uid36_fpSqrtTest_b_4_mem_last_q = 2'b01; + // redist6_yForPe_uid36_fpSqrtTest_b_6_mem_last(CONSTANT,112) + assign redist6_yForPe_uid36_fpSqrtTest_b_6_mem_last_q = 2'b01; - // redist5_yForPe_uid36_fpSqrtTest_b_4_cmp(LOGICAL,145) - assign redist5_yForPe_uid36_fpSqrtTest_b_4_cmp_q = redist5_yForPe_uid36_fpSqrtTest_b_4_mem_last_q == redist5_yForPe_uid36_fpSqrtTest_b_4_rdmux_q ? 1'b1 : 1'b0; + // redist6_yForPe_uid36_fpSqrtTest_b_6_cmp(LOGICAL,113) + assign redist6_yForPe_uid36_fpSqrtTest_b_6_cmp_q = redist6_yForPe_uid36_fpSqrtTest_b_6_mem_last_q == redist6_yForPe_uid36_fpSqrtTest_b_6_rdmux_q ? 1'b1 : 1'b0; - // redist5_yForPe_uid36_fpSqrtTest_b_4_cmpReg(REG,146) + // redist6_yForPe_uid36_fpSqrtTest_b_6_cmpReg(REG,114) always @ (posedge clk or posedge areset) begin if (areset) begin - redist5_yForPe_uid36_fpSqrtTest_b_4_cmpReg_q <= 1'b0; + redist6_yForPe_uid36_fpSqrtTest_b_6_cmpReg_q <= 1'b0; end else if (en == 1'b1) begin - redist5_yForPe_uid36_fpSqrtTest_b_4_cmpReg_q <= redist5_yForPe_uid36_fpSqrtTest_b_4_cmp_q; + redist6_yForPe_uid36_fpSqrtTest_b_6_cmpReg_q <= redist6_yForPe_uid36_fpSqrtTest_b_6_cmp_q; end end - // redist5_yForPe_uid36_fpSqrtTest_b_4_sticky_ena(REG,149) + // redist6_yForPe_uid36_fpSqrtTest_b_6_sticky_ena(REG,117) always @ (posedge clk or posedge areset) begin if (areset) begin - redist5_yForPe_uid36_fpSqrtTest_b_4_sticky_ena_q <= 1'b0; + redist6_yForPe_uid36_fpSqrtTest_b_6_sticky_ena_q <= 1'b0; end - else if (redist5_yForPe_uid36_fpSqrtTest_b_4_nor_q == 1'b1) + else if (redist6_yForPe_uid36_fpSqrtTest_b_6_nor_q == 1'b1) begin - redist5_yForPe_uid36_fpSqrtTest_b_4_sticky_ena_q <= redist5_yForPe_uid36_fpSqrtTest_b_4_cmpReg_q; + redist6_yForPe_uid36_fpSqrtTest_b_6_sticky_ena_q <= redist6_yForPe_uid36_fpSqrtTest_b_6_cmpReg_q; end end - // redist5_yForPe_uid36_fpSqrtTest_b_4_enaAnd(LOGICAL,150) - assign redist5_yForPe_uid36_fpSqrtTest_b_4_enaAnd_q = redist5_yForPe_uid36_fpSqrtTest_b_4_sticky_ena_q & en; + // redist6_yForPe_uid36_fpSqrtTest_b_6_enaAnd(LOGICAL,118) + assign redist6_yForPe_uid36_fpSqrtTest_b_6_enaAnd_q = redist6_yForPe_uid36_fpSqrtTest_b_6_sticky_ena_q & en; - // redist5_yForPe_uid36_fpSqrtTest_b_4_rdcnt(COUNTER,141) + // redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt(COUNTER,109) // low=0, high=2, step=1, init=0 always @ (posedge clk or posedge areset) begin if (areset) begin - redist5_yForPe_uid36_fpSqrtTest_b_4_rdcnt_i <= 2'd0; - redist5_yForPe_uid36_fpSqrtTest_b_4_rdcnt_eq <= 1'b0; + redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_i <= 2'd0; + redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_eq <= 1'b0; end else if (en == 1'b1) begin - if (redist5_yForPe_uid36_fpSqrtTest_b_4_rdcnt_i == 2'd1) + if (redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_i == 2'd1) begin - redist5_yForPe_uid36_fpSqrtTest_b_4_rdcnt_eq <= 1'b1; + redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_eq <= 1'b1; end else begin - redist5_yForPe_uid36_fpSqrtTest_b_4_rdcnt_eq <= 1'b0; + redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_eq <= 1'b0; end - if (redist5_yForPe_uid36_fpSqrtTest_b_4_rdcnt_eq == 1'b1) + if (redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_eq == 1'b1) begin - redist5_yForPe_uid36_fpSqrtTest_b_4_rdcnt_i <= $unsigned(redist5_yForPe_uid36_fpSqrtTest_b_4_rdcnt_i) + $unsigned(2'd2); + redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_i <= $unsigned(redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_i) + $unsigned(2'd2); end else begin - redist5_yForPe_uid36_fpSqrtTest_b_4_rdcnt_i <= $unsigned(redist5_yForPe_uid36_fpSqrtTest_b_4_rdcnt_i) + $unsigned(2'd1); + redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_i <= $unsigned(redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_i) + $unsigned(2'd1); end end end - assign redist5_yForPe_uid36_fpSqrtTest_b_4_rdcnt_q = redist5_yForPe_uid36_fpSqrtTest_b_4_rdcnt_i[1:0]; + assign redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_q = redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_i[1:0]; - // redist5_yForPe_uid36_fpSqrtTest_b_4_rdmux(MUX,142) - assign redist5_yForPe_uid36_fpSqrtTest_b_4_rdmux_s = en; - always @(redist5_yForPe_uid36_fpSqrtTest_b_4_rdmux_s or redist5_yForPe_uid36_fpSqrtTest_b_4_wraddr_q or redist5_yForPe_uid36_fpSqrtTest_b_4_rdcnt_q) + // redist6_yForPe_uid36_fpSqrtTest_b_6_rdmux(MUX,110) + assign redist6_yForPe_uid36_fpSqrtTest_b_6_rdmux_s = en; + always @(redist6_yForPe_uid36_fpSqrtTest_b_6_rdmux_s or redist6_yForPe_uid36_fpSqrtTest_b_6_wraddr_q or redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_q) begin - unique case (redist5_yForPe_uid36_fpSqrtTest_b_4_rdmux_s) - 1'b0 : redist5_yForPe_uid36_fpSqrtTest_b_4_rdmux_q = redist5_yForPe_uid36_fpSqrtTest_b_4_wraddr_q; - 1'b1 : redist5_yForPe_uid36_fpSqrtTest_b_4_rdmux_q = redist5_yForPe_uid36_fpSqrtTest_b_4_rdcnt_q; - default : redist5_yForPe_uid36_fpSqrtTest_b_4_rdmux_q = 2'b0; + unique case (redist6_yForPe_uid36_fpSqrtTest_b_6_rdmux_s) + 1'b0 : redist6_yForPe_uid36_fpSqrtTest_b_6_rdmux_q = redist6_yForPe_uid36_fpSqrtTest_b_6_wraddr_q; + 1'b1 : redist6_yForPe_uid36_fpSqrtTest_b_6_rdmux_q = redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_q; + default : redist6_yForPe_uid36_fpSqrtTest_b_6_rdmux_q = 2'b0; endcase end - // redist5_yForPe_uid36_fpSqrtTest_b_4_wraddr(REG,143) + // VCC(CONSTANT,1) + assign VCC_q = 1'b1; + + // redist6_yForPe_uid36_fpSqrtTest_b_6_wraddr(REG,111) always @ (posedge clk or posedge areset) begin if (areset) begin - redist5_yForPe_uid36_fpSqrtTest_b_4_wraddr_q <= 2'b10; + redist6_yForPe_uid36_fpSqrtTest_b_6_wraddr_q <= 2'b10; end else begin - redist5_yForPe_uid36_fpSqrtTest_b_4_wraddr_q <= redist5_yForPe_uid36_fpSqrtTest_b_4_rdmux_q; + redist6_yForPe_uid36_fpSqrtTest_b_6_wraddr_q <= redist6_yForPe_uid36_fpSqrtTest_b_6_rdmux_q; end end - // redist5_yForPe_uid36_fpSqrtTest_b_4_mem(DUALMEM,140) - assign redist5_yForPe_uid36_fpSqrtTest_b_4_mem_ia = yForPe_uid36_fpSqrtTest_b; - assign redist5_yForPe_uid36_fpSqrtTest_b_4_mem_aa = redist5_yForPe_uid36_fpSqrtTest_b_4_wraddr_q; - assign redist5_yForPe_uid36_fpSqrtTest_b_4_mem_ab = redist5_yForPe_uid36_fpSqrtTest_b_4_rdmux_q; - assign redist5_yForPe_uid36_fpSqrtTest_b_4_mem_reset0 = areset; + // redist6_yForPe_uid36_fpSqrtTest_b_6_mem(DUALMEM,108) + assign redist6_yForPe_uid36_fpSqrtTest_b_6_mem_ia = redist5_yForPe_uid36_fpSqrtTest_b_2_q; + assign redist6_yForPe_uid36_fpSqrtTest_b_6_mem_aa = redist6_yForPe_uid36_fpSqrtTest_b_6_wraddr_q; + assign redist6_yForPe_uid36_fpSqrtTest_b_6_mem_ab = redist6_yForPe_uid36_fpSqrtTest_b_6_rdmux_q; + assign redist6_yForPe_uid36_fpSqrtTest_b_6_mem_reset0 = areset; altera_syncram #( .ram_block_type("MLAB"), .operation_mode("DUAL_PORT"), @@ -1013,17 +601,17 @@ module acl_fsqrt ( .read_during_write_mode_mixed_ports("DONT_CARE"), .power_up_uninitialized("TRUE"), .intended_device_family("Arria 10") - ) redist5_yForPe_uid36_fpSqrtTest_b_4_mem_dmem ( - .clocken1(redist5_yForPe_uid36_fpSqrtTest_b_4_enaAnd_q[0]), + ) redist6_yForPe_uid36_fpSqrtTest_b_6_mem_dmem ( + .clocken1(redist6_yForPe_uid36_fpSqrtTest_b_6_enaAnd_q[0]), .clocken0(VCC_q[0]), .clock0(clk), - .aclr1(redist5_yForPe_uid36_fpSqrtTest_b_4_mem_reset0), + .aclr1(redist6_yForPe_uid36_fpSqrtTest_b_6_mem_reset0), .clock1(clk), - .address_a(redist5_yForPe_uid36_fpSqrtTest_b_4_mem_aa), - .data_a(redist5_yForPe_uid36_fpSqrtTest_b_4_mem_ia), + .address_a(redist6_yForPe_uid36_fpSqrtTest_b_6_mem_aa), + .data_a(redist6_yForPe_uid36_fpSqrtTest_b_6_mem_ia), .wren_a(en[0]), - .address_b(redist5_yForPe_uid36_fpSqrtTest_b_4_mem_ab), - .q_b(redist5_yForPe_uid36_fpSqrtTest_b_4_mem_iq), + .address_b(redist6_yForPe_uid36_fpSqrtTest_b_6_mem_ab), + .q_b(redist6_yForPe_uid36_fpSqrtTest_b_6_mem_iq), .wren_b(), .rden_a(), .rden_b(), @@ -1043,32 +631,35 @@ module acl_fsqrt ( .q_a(), .eccstatus() ); - assign redist5_yForPe_uid36_fpSqrtTest_b_4_mem_q = redist5_yForPe_uid36_fpSqrtTest_b_4_mem_iq[15:0]; + assign redist6_yForPe_uid36_fpSqrtTest_b_6_mem_q = redist6_yForPe_uid36_fpSqrtTest_b_6_mem_iq[15:0]; - // prodXY_uid116_pT2_uid107_invPolyEval_cma(CHAINMULTADD,123)@6 + 3 - assign prodXY_uid116_pT2_uid107_invPolyEval_cma_reset = areset; - assign prodXY_uid116_pT2_uid107_invPolyEval_cma_ena0 = en[0]; - assign prodXY_uid116_pT2_uid107_invPolyEval_cma_ena1 = prodXY_uid116_pT2_uid107_invPolyEval_cma_ena0; - assign prodXY_uid116_pT2_uid107_invPolyEval_cma_ena2 = prodXY_uid116_pT2_uid107_invPolyEval_cma_ena0; - assign prodXY_uid116_pT2_uid107_invPolyEval_cma_l[0] = $signed({1'b0, prodXY_uid116_pT2_uid107_invPolyEval_cma_a1[0][15:0]}); - assign prodXY_uid116_pT2_uid107_invPolyEval_cma_p[0] = prodXY_uid116_pT2_uid107_invPolyEval_cma_l[0] * prodXY_uid116_pT2_uid107_invPolyEval_cma_c1[0]; - assign prodXY_uid116_pT2_uid107_invPolyEval_cma_u[0] = prodXY_uid116_pT2_uid107_invPolyEval_cma_p[0][39:0]; - assign prodXY_uid116_pT2_uid107_invPolyEval_cma_w[0] = prodXY_uid116_pT2_uid107_invPolyEval_cma_u[0]; - assign prodXY_uid116_pT2_uid107_invPolyEval_cma_x[0] = prodXY_uid116_pT2_uid107_invPolyEval_cma_w[0]; - assign prodXY_uid116_pT2_uid107_invPolyEval_cma_y[0] = prodXY_uid116_pT2_uid107_invPolyEval_cma_x[0]; + // GND(CONSTANT,0) + assign GND_q = 1'b0; + + // prodXY_uid90_pT2_uid81_invPolyEval_cma(CHAINMULTADD,96)@6 + 3 + assign prodXY_uid90_pT2_uid81_invPolyEval_cma_reset = areset; + assign prodXY_uid90_pT2_uid81_invPolyEval_cma_ena0 = en[0]; + assign prodXY_uid90_pT2_uid81_invPolyEval_cma_ena1 = prodXY_uid90_pT2_uid81_invPolyEval_cma_ena0; + assign prodXY_uid90_pT2_uid81_invPolyEval_cma_ena2 = prodXY_uid90_pT2_uid81_invPolyEval_cma_ena0; + assign prodXY_uid90_pT2_uid81_invPolyEval_cma_l[0] = $signed({1'b0, prodXY_uid90_pT2_uid81_invPolyEval_cma_a1[0][15:0]}); + assign prodXY_uid90_pT2_uid81_invPolyEval_cma_p[0] = prodXY_uid90_pT2_uid81_invPolyEval_cma_l[0] * prodXY_uid90_pT2_uid81_invPolyEval_cma_c1[0]; + assign prodXY_uid90_pT2_uid81_invPolyEval_cma_u[0] = prodXY_uid90_pT2_uid81_invPolyEval_cma_p[0][39:0]; + assign prodXY_uid90_pT2_uid81_invPolyEval_cma_w[0] = prodXY_uid90_pT2_uid81_invPolyEval_cma_u[0]; + assign prodXY_uid90_pT2_uid81_invPolyEval_cma_x[0] = prodXY_uid90_pT2_uid81_invPolyEval_cma_w[0]; + assign prodXY_uid90_pT2_uid81_invPolyEval_cma_y[0] = prodXY_uid90_pT2_uid81_invPolyEval_cma_x[0]; always @ (posedge clk or posedge areset) begin if (areset) begin - prodXY_uid116_pT2_uid107_invPolyEval_cma_a0 <= '{default: '0}; - prodXY_uid116_pT2_uid107_invPolyEval_cma_c0 <= '{default: '0}; + prodXY_uid90_pT2_uid81_invPolyEval_cma_a0 <= '{default: '0}; + prodXY_uid90_pT2_uid81_invPolyEval_cma_c0 <= '{default: '0}; end else begin - if (prodXY_uid116_pT2_uid107_invPolyEval_cma_ena0 == 1'b1) + if (prodXY_uid90_pT2_uid81_invPolyEval_cma_ena0 == 1'b1) begin - prodXY_uid116_pT2_uid107_invPolyEval_cma_a0[0] <= redist5_yForPe_uid36_fpSqrtTest_b_4_mem_q; - prodXY_uid116_pT2_uid107_invPolyEval_cma_c0[0] <= s1_uid105_invPolyEval_q; + prodXY_uid90_pT2_uid81_invPolyEval_cma_a0[0] <= redist6_yForPe_uid36_fpSqrtTest_b_6_mem_q; + prodXY_uid90_pT2_uid81_invPolyEval_cma_c0[0] <= s1_uid79_invPolyEval_q; end end end @@ -1076,15 +667,15 @@ module acl_fsqrt ( begin if (areset) begin - prodXY_uid116_pT2_uid107_invPolyEval_cma_a1 <= '{default: '0}; - prodXY_uid116_pT2_uid107_invPolyEval_cma_c1 <= '{default: '0}; + prodXY_uid90_pT2_uid81_invPolyEval_cma_a1 <= '{default: '0}; + prodXY_uid90_pT2_uid81_invPolyEval_cma_c1 <= '{default: '0}; end else begin - if (prodXY_uid116_pT2_uid107_invPolyEval_cma_ena2 == 1'b1) + if (prodXY_uid90_pT2_uid81_invPolyEval_cma_ena2 == 1'b1) begin - prodXY_uid116_pT2_uid107_invPolyEval_cma_a1 <= prodXY_uid116_pT2_uid107_invPolyEval_cma_a0; - prodXY_uid116_pT2_uid107_invPolyEval_cma_c1 <= prodXY_uid116_pT2_uid107_invPolyEval_cma_c0; + prodXY_uid90_pT2_uid81_invPolyEval_cma_a1 <= prodXY_uid90_pT2_uid81_invPolyEval_cma_a0; + prodXY_uid90_pT2_uid81_invPolyEval_cma_c1 <= prodXY_uid90_pT2_uid81_invPolyEval_cma_c0; end end end @@ -1092,34 +683,34 @@ module acl_fsqrt ( begin if (areset) begin - prodXY_uid116_pT2_uid107_invPolyEval_cma_s <= '{default: '0}; + prodXY_uid90_pT2_uid81_invPolyEval_cma_s <= '{default: '0}; end else begin - if (prodXY_uid116_pT2_uid107_invPolyEval_cma_ena1 == 1'b1) + if (prodXY_uid90_pT2_uid81_invPolyEval_cma_ena1 == 1'b1) begin - prodXY_uid116_pT2_uid107_invPolyEval_cma_s[0] <= prodXY_uid116_pT2_uid107_invPolyEval_cma_y[0]; + prodXY_uid90_pT2_uid81_invPolyEval_cma_s[0] <= prodXY_uid90_pT2_uid81_invPolyEval_cma_y[0]; end end end dspba_delay_ver #( .width(39), .depth(0), .reset_kind("ASYNC") ) - prodXY_uid116_pT2_uid107_invPolyEval_cma_delay ( .xin(prodXY_uid116_pT2_uid107_invPolyEval_cma_s[0][38:0]), .xout(prodXY_uid116_pT2_uid107_invPolyEval_cma_qq), .ena(en[0]), .clk(clk), .aclr(areset) ); - assign prodXY_uid116_pT2_uid107_invPolyEval_cma_q = prodXY_uid116_pT2_uid107_invPolyEval_cma_qq[38:0]; + prodXY_uid90_pT2_uid81_invPolyEval_cma_delay ( .xin(prodXY_uid90_pT2_uid81_invPolyEval_cma_s[0][38:0]), .xout(prodXY_uid90_pT2_uid81_invPolyEval_cma_qq), .ena(en[0]), .clk(clk), .aclr(areset) ); + assign prodXY_uid90_pT2_uid81_invPolyEval_cma_q = prodXY_uid90_pT2_uid81_invPolyEval_cma_qq[38:0]; - // osig_uid117_pT2_uid107_invPolyEval(BITSELECT,116)@9 - assign osig_uid117_pT2_uid107_invPolyEval_b = prodXY_uid116_pT2_uid107_invPolyEval_cma_q[38:15]; + // osig_uid91_pT2_uid81_invPolyEval(BITSELECT,90)@9 + assign osig_uid91_pT2_uid81_invPolyEval_b = prodXY_uid90_pT2_uid81_invPolyEval_cma_q[38:15]; - // highBBits_uid109_invPolyEval(BITSELECT,108)@9 - assign highBBits_uid109_invPolyEval_b = osig_uid117_pT2_uid107_invPolyEval_b[23:2]; + // highBBits_uid83_invPolyEval(BITSELECT,82)@9 + assign highBBits_uid83_invPolyEval_b = osig_uid91_pT2_uid81_invPolyEval_b[23:2]; - // redist7_yAddr_uid35_fpSqrtTest_b_7(DELAY,132) + // redist8_yAddr_uid35_fpSqrtTest_b_7(DELAY,105) dspba_delay_ver #( .width(8), .depth(4), .reset_kind("ASYNC") ) - redist7_yAddr_uid35_fpSqrtTest_b_7 ( .xin(redist6_yAddr_uid35_fpSqrtTest_b_3_q), .xout(redist7_yAddr_uid35_fpSqrtTest_b_7_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + redist8_yAddr_uid35_fpSqrtTest_b_7 ( .xin(redist7_yAddr_uid35_fpSqrtTest_b_3_q), .xout(redist8_yAddr_uid35_fpSqrtTest_b_7_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - // memoryC0_uid88_sqrtTables_lutmem(DUALMEM,118)@7 + 2 + // memoryC0_uid62_sqrtTables_lutmem(DUALMEM,92)@7 + 2 // in j@20000000 - assign memoryC0_uid88_sqrtTables_lutmem_aa = redist7_yAddr_uid35_fpSqrtTest_b_7_q; - assign memoryC0_uid88_sqrtTables_lutmem_reset0 = areset; + assign memoryC0_uid62_sqrtTables_lutmem_aa = redist8_yAddr_uid35_fpSqrtTest_b_7_q; + assign memoryC0_uid62_sqrtTables_lutmem_reset0 = areset; altera_syncram #( .ram_block_type("M20K"), .operation_mode("ROM"), @@ -1132,15 +723,15 @@ module acl_fsqrt ( .outdata_aclr_a("CLEAR0"), .clock_enable_input_a("NORMAL"), .power_up_uninitialized("FALSE"), - .init_file("acl_fsqrt_memoryC0_uid88_sqrtTables_lutmem.hex"), + .init_file("acl_fsqrt_memoryC0_uid62_sqrtTables_lutmem.hex"), .init_file_layout("PORT_A"), .intended_device_family("Arria 10") - ) memoryC0_uid88_sqrtTables_lutmem_dmem ( + ) memoryC0_uid62_sqrtTables_lutmem_dmem ( .clocken0(en[0]), - .aclr0(memoryC0_uid88_sqrtTables_lutmem_reset0), + .aclr0(memoryC0_uid62_sqrtTables_lutmem_reset0), .clock0(clk), - .address_a(memoryC0_uid88_sqrtTables_lutmem_aa), - .q_a(memoryC0_uid88_sqrtTables_lutmem_ir), + .address_a(memoryC0_uid62_sqrtTables_lutmem_aa), + .q_a(memoryC0_uid62_sqrtTables_lutmem_ir), .wren_a(), .wren_b(), .rden_a(), @@ -1165,174 +756,139 @@ module acl_fsqrt ( .q_b(), .eccstatus() ); - assign memoryC0_uid88_sqrtTables_lutmem_r = memoryC0_uid88_sqrtTables_lutmem_ir[28:0]; + assign memoryC0_uid62_sqrtTables_lutmem_r = memoryC0_uid62_sqrtTables_lutmem_ir[28:0]; - // s2sumAHighB_uid110_invPolyEval(ADD,109)@9 - assign s2sumAHighB_uid110_invPolyEval_a = {{1{memoryC0_uid88_sqrtTables_lutmem_r[28]}}, memoryC0_uid88_sqrtTables_lutmem_r}; - assign s2sumAHighB_uid110_invPolyEval_b = {{8{highBBits_uid109_invPolyEval_b[21]}}, highBBits_uid109_invPolyEval_b}; - assign s2sumAHighB_uid110_invPolyEval_o = $signed(s2sumAHighB_uid110_invPolyEval_a) + $signed(s2sumAHighB_uid110_invPolyEval_b); - assign s2sumAHighB_uid110_invPolyEval_q = s2sumAHighB_uid110_invPolyEval_o[29:0]; + // s2sumAHighB_uid84_invPolyEval(ADD,83)@9 + assign s2sumAHighB_uid84_invPolyEval_a = {{1{memoryC0_uid62_sqrtTables_lutmem_r[28]}}, memoryC0_uid62_sqrtTables_lutmem_r}; + assign s2sumAHighB_uid84_invPolyEval_b = {{8{highBBits_uid83_invPolyEval_b[21]}}, highBBits_uid83_invPolyEval_b}; + assign s2sumAHighB_uid84_invPolyEval_o = $signed(s2sumAHighB_uid84_invPolyEval_a) + $signed(s2sumAHighB_uid84_invPolyEval_b); + assign s2sumAHighB_uid84_invPolyEval_q = s2sumAHighB_uid84_invPolyEval_o[29:0]; - // lowRangeB_uid108_invPolyEval(BITSELECT,107)@9 - assign lowRangeB_uid108_invPolyEval_in = osig_uid117_pT2_uid107_invPolyEval_b[1:0]; - assign lowRangeB_uid108_invPolyEval_b = lowRangeB_uid108_invPolyEval_in[1:0]; + // lowRangeB_uid82_invPolyEval(BITSELECT,81)@9 + assign lowRangeB_uid82_invPolyEval_in = osig_uid91_pT2_uid81_invPolyEval_b[1:0]; + assign lowRangeB_uid82_invPolyEval_b = lowRangeB_uid82_invPolyEval_in[1:0]; - // s2_uid111_invPolyEval(BITJOIN,110)@9 - assign s2_uid111_invPolyEval_q = {s2sumAHighB_uid110_invPolyEval_q, lowRangeB_uid108_invPolyEval_b}; + // s2_uid85_invPolyEval(BITJOIN,84)@9 + assign s2_uid85_invPolyEval_q = {s2sumAHighB_uid84_invPolyEval_q, lowRangeB_uid82_invPolyEval_b}; - // fracRPreCR_uid39_fpSqrtTest(BITSELECT,38)@9 - assign fracRPreCR_uid39_fpSqrtTest_in = s2_uid111_invPolyEval_q[28:0]; - assign fracRPreCR_uid39_fpSqrtTest_b = fracRPreCR_uid39_fpSqrtTest_in[28:5]; + // expInc_uid38_fpSqrtTest(BITSELECT,37)@9 + assign expInc_uid38_fpSqrtTest_in = s2_uid85_invPolyEval_q[30:0]; + assign expInc_uid38_fpSqrtTest_b = expInc_uid38_fpSqrtTest_in[30:30]; - // redist2_fracRPreCR_uid39_fpSqrtTest_b_1(DELAY,127) - dspba_delay_ver #( .width(24), .depth(1), .reset_kind("ASYNC") ) - redist2_fracRPreCR_uid39_fpSqrtTest_b_1 ( .xin(fracRPreCR_uid39_fpSqrtTest_b), .xout(redist2_fracRPreCR_uid39_fpSqrtTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + // redist4_expInc_uid38_fpSqrtTest_b_1(DELAY,101) + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + redist4_expInc_uid38_fpSqrtTest_b_1 ( .xin(expInc_uid38_fpSqrtTest_b), .xout(redist4_expInc_uid38_fpSqrtTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - // fracPaddingOne_uid41_fpSqrtTest(BITJOIN,40)@10 - assign fracPaddingOne_uid41_fpSqrtTest_q = {VCC_q, redist2_fracRPreCR_uid39_fpSqrtTest_b_1_q}; + // redist9_expRMux_uid31_fpSqrtTest_q_10_notEnable(LOGICAL,127) + assign redist9_expRMux_uid31_fpSqrtTest_q_10_notEnable_q = ~ (en); - // squaredResult_uid42_fpSqrtTest_cma(CHAINMULTADD,121)@10 + 3 - assign squaredResult_uid42_fpSqrtTest_cma_reset = areset; - assign squaredResult_uid42_fpSqrtTest_cma_ena0 = en[0]; - assign squaredResult_uid42_fpSqrtTest_cma_ena1 = squaredResult_uid42_fpSqrtTest_cma_ena0; - assign squaredResult_uid42_fpSqrtTest_cma_ena2 = squaredResult_uid42_fpSqrtTest_cma_ena0; - assign squaredResult_uid42_fpSqrtTest_cma_p[0] = squaredResult_uid42_fpSqrtTest_cma_a1[0] * squaredResult_uid42_fpSqrtTest_cma_c1[0]; - assign squaredResult_uid42_fpSqrtTest_cma_u[0] = squaredResult_uid42_fpSqrtTest_cma_p[0][49:0]; - assign squaredResult_uid42_fpSqrtTest_cma_w[0] = squaredResult_uid42_fpSqrtTest_cma_u[0]; - assign squaredResult_uid42_fpSqrtTest_cma_x[0] = squaredResult_uid42_fpSqrtTest_cma_w[0]; - assign squaredResult_uid42_fpSqrtTest_cma_y[0] = squaredResult_uid42_fpSqrtTest_cma_x[0]; + // redist9_expRMux_uid31_fpSqrtTest_q_10_nor(LOGICAL,128) + assign redist9_expRMux_uid31_fpSqrtTest_q_10_nor_q = ~ (redist9_expRMux_uid31_fpSqrtTest_q_10_notEnable_q | redist9_expRMux_uid31_fpSqrtTest_q_10_sticky_ena_q); + + // redist9_expRMux_uid31_fpSqrtTest_q_10_mem_last(CONSTANT,124) + assign redist9_expRMux_uid31_fpSqrtTest_q_10_mem_last_q = 4'b0101; + + // redist9_expRMux_uid31_fpSqrtTest_q_10_cmp(LOGICAL,125) + assign redist9_expRMux_uid31_fpSqrtTest_q_10_cmp_b = {1'b0, redist9_expRMux_uid31_fpSqrtTest_q_10_rdmux_q}; + assign redist9_expRMux_uid31_fpSqrtTest_q_10_cmp_q = redist9_expRMux_uid31_fpSqrtTest_q_10_mem_last_q == redist9_expRMux_uid31_fpSqrtTest_q_10_cmp_b ? 1'b1 : 1'b0; + + // redist9_expRMux_uid31_fpSqrtTest_q_10_cmpReg(REG,126) always @ (posedge clk or posedge areset) begin if (areset) begin - squaredResult_uid42_fpSqrtTest_cma_a0 <= '{default: '0}; - squaredResult_uid42_fpSqrtTest_cma_c0 <= '{default: '0}; - end - else - begin - if (squaredResult_uid42_fpSqrtTest_cma_ena0 == 1'b1) - begin - squaredResult_uid42_fpSqrtTest_cma_a0[0] <= fracPaddingOne_uid41_fpSqrtTest_q; - squaredResult_uid42_fpSqrtTest_cma_c0[0] <= fracPaddingOne_uid41_fpSqrtTest_q; - end - end - end - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - squaredResult_uid42_fpSqrtTest_cma_a1 <= '{default: '0}; - squaredResult_uid42_fpSqrtTest_cma_c1 <= '{default: '0}; - end - else - begin - if (squaredResult_uid42_fpSqrtTest_cma_ena2 == 1'b1) - begin - squaredResult_uid42_fpSqrtTest_cma_a1 <= squaredResult_uid42_fpSqrtTest_cma_a0; - squaredResult_uid42_fpSqrtTest_cma_c1 <= squaredResult_uid42_fpSqrtTest_cma_c0; - end - end - end - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - squaredResult_uid42_fpSqrtTest_cma_s <= '{default: '0}; - end - else - begin - if (squaredResult_uid42_fpSqrtTest_cma_ena1 == 1'b1) - begin - squaredResult_uid42_fpSqrtTest_cma_s[0] <= squaredResult_uid42_fpSqrtTest_cma_y[0]; - end - end - end - dspba_delay_ver #( .width(50), .depth(0), .reset_kind("ASYNC") ) - squaredResult_uid42_fpSqrtTest_cma_delay ( .xin(squaredResult_uid42_fpSqrtTest_cma_s[0][49:0]), .xout(squaredResult_uid42_fpSqrtTest_cma_qq), .ena(en[0]), .clk(clk), .aclr(areset) ); - assign squaredResult_uid42_fpSqrtTest_cma_q = squaredResult_uid42_fpSqrtTest_cma_qq[49:0]; - - // squaredResultGTEIn_uid55_fpSqrtTest(COMPARE,56)@13 + 1 - assign squaredResultGTEIn_uid55_fpSqrtTest_a = {2'b00, squaredResult_uid42_fpSqrtTest_cma_q}; - assign squaredResultGTEIn_uid55_fpSqrtTest_b = {2'b00, updatedY_uid56_fpSqrtTest_q}; - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - squaredResultGTEIn_uid55_fpSqrtTest_o <= 52'b0; + redist9_expRMux_uid31_fpSqrtTest_q_10_cmpReg_q <= 1'b0; end else if (en == 1'b1) begin - squaredResultGTEIn_uid55_fpSqrtTest_o <= $unsigned(squaredResultGTEIn_uid55_fpSqrtTest_a) - $unsigned(squaredResultGTEIn_uid55_fpSqrtTest_b); + redist9_expRMux_uid31_fpSqrtTest_q_10_cmpReg_q <= redist9_expRMux_uid31_fpSqrtTest_q_10_cmp_q; end end - assign squaredResultGTEIn_uid55_fpSqrtTest_n[0] = ~ (squaredResultGTEIn_uid55_fpSqrtTest_o[51]); - // pLTOne_uid58_fpSqrtTest(LOGICAL,57)@14 - assign pLTOne_uid58_fpSqrtTest_q = ~ (squaredResultGTEIn_uid55_fpSqrtTest_n); + // redist9_expRMux_uid31_fpSqrtTest_q_10_sticky_ena(REG,129) + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist9_expRMux_uid31_fpSqrtTest_q_10_sticky_ena_q <= 1'b0; + end + else if (redist9_expRMux_uid31_fpSqrtTest_q_10_nor_q == 1'b1) + begin + redist9_expRMux_uid31_fpSqrtTest_q_10_sticky_ena_q <= redist9_expRMux_uid31_fpSqrtTest_q_10_cmpReg_q; + end + end - // redist3_fracRPreCR_uid39_fpSqrtTest_b_5_inputreg(DELAY,139) - dspba_delay_ver #( .width(24), .depth(1), .reset_kind("ASYNC") ) - redist3_fracRPreCR_uid39_fpSqrtTest_b_5_inputreg ( .xin(redist2_fracRPreCR_uid39_fpSqrtTest_b_1_q), .xout(redist3_fracRPreCR_uid39_fpSqrtTest_b_5_inputreg_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + // redist9_expRMux_uid31_fpSqrtTest_q_10_enaAnd(LOGICAL,130) + assign redist9_expRMux_uid31_fpSqrtTest_q_10_enaAnd_q = redist9_expRMux_uid31_fpSqrtTest_q_10_sticky_ena_q & en; - // redist3_fracRPreCR_uid39_fpSqrtTest_b_5(DELAY,128) - dspba_delay_ver #( .width(24), .depth(3), .reset_kind("ASYNC") ) - redist3_fracRPreCR_uid39_fpSqrtTest_b_5 ( .xin(redist3_fracRPreCR_uid39_fpSqrtTest_b_5_inputreg_q), .xout(redist3_fracRPreCR_uid39_fpSqrtTest_b_5_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + // redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt(COUNTER,121) + // low=0, high=6, step=1, init=0 + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_i <= 3'd0; + redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_eq <= 1'b0; + end + else if (en == 1'b1) + begin + if (redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_i == 3'd5) + begin + redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_eq <= 1'b1; + end + else + begin + redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_eq <= 1'b0; + end + if (redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_eq == 1'b1) + begin + redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_i <= $unsigned(redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_i) + $unsigned(3'd2); + end + else + begin + redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_i <= $unsigned(redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_i) + $unsigned(3'd1); + end + end + end + assign redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_q = redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_i[2:0]; - // fxpSqrtResPostUpdateE_uid60_fpSqrtTest(ADD,59)@14 - assign fxpSqrtResPostUpdateE_uid60_fpSqrtTest_a = {1'b0, redist3_fracRPreCR_uid39_fpSqrtTest_b_5_q}; - assign fxpSqrtResPostUpdateE_uid60_fpSqrtTest_b = {24'b000000000000000000000000, pLTOne_uid58_fpSqrtTest_q}; - assign fxpSqrtResPostUpdateE_uid60_fpSqrtTest_o = $unsigned(fxpSqrtResPostUpdateE_uid60_fpSqrtTest_a) + $unsigned(fxpSqrtResPostUpdateE_uid60_fpSqrtTest_b); - assign fxpSqrtResPostUpdateE_uid60_fpSqrtTest_q = fxpSqrtResPostUpdateE_uid60_fpSqrtTest_o[24:0]; - - // expUpdateCRU_uid61_fpSqrtTest_merged_bit_select(BITSELECT,124)@14 - assign expUpdateCRU_uid61_fpSqrtTest_merged_bit_select_b = fxpSqrtResPostUpdateE_uid60_fpSqrtTest_q[24:24]; - assign expUpdateCRU_uid61_fpSqrtTest_merged_bit_select_c = fxpSqrtResPostUpdateE_uid60_fpSqrtTest_q[23:1]; - - // fracPENotOne_uid62_fpSqrtTest(LOGICAL,61)@14 - assign fracPENotOne_uid62_fpSqrtTest_q = ~ (redist4_expIncPEOnly_uid38_fpSqrtTest_b_5_q); - - // fracPENotOneAndCRRoundsExp_uid63_fpSqrtTest(LOGICAL,62)@14 - assign fracPENotOneAndCRRoundsExp_uid63_fpSqrtTest_q = fracPENotOne_uid62_fpSqrtTest_q & expUpdateCRU_uid61_fpSqrtTest_merged_bit_select_b; - - // expIncPEOnly_uid38_fpSqrtTest(BITSELECT,37)@9 - assign expIncPEOnly_uid38_fpSqrtTest_in = s2_uid111_invPolyEval_q[30:0]; - assign expIncPEOnly_uid38_fpSqrtTest_b = expIncPEOnly_uid38_fpSqrtTest_in[30:30]; - - // redist4_expIncPEOnly_uid38_fpSqrtTest_b_5(DELAY,129) - dspba_delay_ver #( .width(1), .depth(5), .reset_kind("ASYNC") ) - redist4_expIncPEOnly_uid38_fpSqrtTest_b_5 ( .xin(expIncPEOnly_uid38_fpSqrtTest_b), .xout(redist4_expIncPEOnly_uid38_fpSqrtTest_b_5_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // expInc_uid64_fpSqrtTest(LOGICAL,63)@14 + 1 - assign expInc_uid64_fpSqrtTest_qi = redist4_expIncPEOnly_uid38_fpSqrtTest_b_5_q | fracPENotOneAndCRRoundsExp_uid63_fpSqrtTest_q; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - expInc_uid64_fpSqrtTest_delay ( .xin(expInc_uid64_fpSqrtTest_qi), .xout(expInc_uid64_fpSqrtTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + // redist9_expRMux_uid31_fpSqrtTest_q_10_rdmux(MUX,122) + assign redist9_expRMux_uid31_fpSqrtTest_q_10_rdmux_s = en; + always @(redist9_expRMux_uid31_fpSqrtTest_q_10_rdmux_s or redist9_expRMux_uid31_fpSqrtTest_q_10_wraddr_q or redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_q) + begin + unique case (redist9_expRMux_uid31_fpSqrtTest_q_10_rdmux_s) + 1'b0 : redist9_expRMux_uid31_fpSqrtTest_q_10_rdmux_q = redist9_expRMux_uid31_fpSqrtTest_q_10_wraddr_q; + 1'b1 : redist9_expRMux_uid31_fpSqrtTest_q_10_rdmux_q = redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_q; + default : redist9_expRMux_uid31_fpSqrtTest_q_10_rdmux_q = 3'b0; + endcase + end // sBiasM1_uid26_fpSqrtTest(CONSTANT,25) assign sBiasM1_uid26_fpSqrtTest_q = 8'b01111110; - // expOddSig_uid27_fpSqrtTest(ADD,26)@13 - assign expOddSig_uid27_fpSqrtTest_a = {1'b0, redist13_expX_uid6_fpSqrtTest_b_13_outputreg_q}; + // expOddSig_uid27_fpSqrtTest(ADD,26)@0 + assign expOddSig_uid27_fpSqrtTest_a = {1'b0, expX_uid6_fpSqrtTest_b}; assign expOddSig_uid27_fpSqrtTest_b = {1'b0, sBiasM1_uid26_fpSqrtTest_q}; assign expOddSig_uid27_fpSqrtTest_o = $unsigned(expOddSig_uid27_fpSqrtTest_a) + $unsigned(expOddSig_uid27_fpSqrtTest_b); assign expOddSig_uid27_fpSqrtTest_q = expOddSig_uid27_fpSqrtTest_o[8:0]; - // expROdd_uid28_fpSqrtTest(BITSELECT,27)@13 + // expROdd_uid28_fpSqrtTest(BITSELECT,27)@0 assign expROdd_uid28_fpSqrtTest_b = expOddSig_uid27_fpSqrtTest_q[8:1]; // sBias_uid22_fpSqrtTest(CONSTANT,21) assign sBias_uid22_fpSqrtTest_q = 8'b01111111; - // expEvenSig_uid24_fpSqrtTest(ADD,23)@13 - assign expEvenSig_uid24_fpSqrtTest_a = {1'b0, redist13_expX_uid6_fpSqrtTest_b_13_outputreg_q}; + // expEvenSig_uid24_fpSqrtTest(ADD,23)@0 + assign expEvenSig_uid24_fpSqrtTest_a = {1'b0, expX_uid6_fpSqrtTest_b}; assign expEvenSig_uid24_fpSqrtTest_b = {1'b0, sBias_uid22_fpSqrtTest_q}; assign expEvenSig_uid24_fpSqrtTest_o = $unsigned(expEvenSig_uid24_fpSqrtTest_a) + $unsigned(expEvenSig_uid24_fpSqrtTest_b); assign expEvenSig_uid24_fpSqrtTest_q = expEvenSig_uid24_fpSqrtTest_o[8:0]; - // expREven_uid25_fpSqrtTest(BITSELECT,24)@13 + // expREven_uid25_fpSqrtTest(BITSELECT,24)@0 assign expREven_uid25_fpSqrtTest_b = expEvenSig_uid24_fpSqrtTest_q[8:1]; - // expRMux_uid31_fpSqrtTest(MUX,30)@13 + 1 - assign expRMux_uid31_fpSqrtTest_s = redist9_expOddSelect_uid30_fpSqrtTest_q_13_q; + // expRMux_uid31_fpSqrtTest(MUX,30)@0 + 1 + assign expRMux_uid31_fpSqrtTest_s = expOddSelect_uid30_fpSqrtTest_q; always @ (posedge clk or posedge areset) begin if (areset) @@ -1349,143 +905,224 @@ module acl_fsqrt ( end end - // redist8_expRMux_uid31_fpSqrtTest_q_2(DELAY,133) - dspba_delay_ver #( .width(8), .depth(1), .reset_kind("ASYNC") ) - redist8_expRMux_uid31_fpSqrtTest_q_2 ( .xin(expRMux_uid31_fpSqrtTest_q), .xout(redist8_expRMux_uid31_fpSqrtTest_q_2_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // expR_uid66_fpSqrtTest(ADD,65)@15 - assign expR_uid66_fpSqrtTest_a = {1'b0, redist8_expRMux_uid31_fpSqrtTest_q_2_q}; - assign expR_uid66_fpSqrtTest_b = {8'b00000000, expInc_uid64_fpSqrtTest_q}; - assign expR_uid66_fpSqrtTest_o = $unsigned(expR_uid66_fpSqrtTest_a) + $unsigned(expR_uid66_fpSqrtTest_b); - assign expR_uid66_fpSqrtTest_q = expR_uid66_fpSqrtTest_o[8:0]; - - // expRR_uid77_fpSqrtTest(BITSELECT,76)@15 - assign expRR_uid77_fpSqrtTest_in = expR_uid66_fpSqrtTest_q[7:0]; - assign expRR_uid77_fpSqrtTest_b = expRR_uid77_fpSqrtTest_in[7:0]; - - // expXIsMax_uid14_fpSqrtTest(LOGICAL,13)@13 + 1 - assign expXIsMax_uid14_fpSqrtTest_qi = redist13_expX_uid6_fpSqrtTest_b_13_outputreg_q == cstAllOWE_uid8_fpSqrtTest_q ? 1'b1 : 1'b0; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - expXIsMax_uid14_fpSqrtTest_delay ( .xin(expXIsMax_uid14_fpSqrtTest_qi), .xout(expXIsMax_uid14_fpSqrtTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // invExpXIsMax_uid19_fpSqrtTest(LOGICAL,18)@14 - assign invExpXIsMax_uid19_fpSqrtTest_q = ~ (expXIsMax_uid14_fpSqrtTest_q); - - // InvExpXIsZero_uid20_fpSqrtTest(LOGICAL,19)@14 - assign InvExpXIsZero_uid20_fpSqrtTest_q = ~ (excZ_x_uid13_fpSqrtTest_q); - - // excR_x_uid21_fpSqrtTest(LOGICAL,20)@14 - assign excR_x_uid21_fpSqrtTest_q = InvExpXIsZero_uid20_fpSqrtTest_q & invExpXIsMax_uid19_fpSqrtTest_q; - - // minReg_uid69_fpSqrtTest(LOGICAL,68)@14 - assign minReg_uid69_fpSqrtTest_q = excR_x_uid21_fpSqrtTest_q & redist12_signX_uid7_fpSqrtTest_b_14_q; - - // cstZeroWF_uid9_fpSqrtTest(CONSTANT,8) - assign cstZeroWF_uid9_fpSqrtTest_q = 23'b00000000000000000000000; - - // fracXIsZero_uid15_fpSqrtTest(LOGICAL,14)@13 + 1 - assign fracXIsZero_uid15_fpSqrtTest_qi = cstZeroWF_uid9_fpSqrtTest_q == redist11_frac_x_uid12_fpSqrtTest_b_13_outputreg_q ? 1'b1 : 1'b0; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - fracXIsZero_uid15_fpSqrtTest_delay ( .xin(fracXIsZero_uid15_fpSqrtTest_qi), .xout(fracXIsZero_uid15_fpSqrtTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // excI_x_uid17_fpSqrtTest(LOGICAL,16)@14 - assign excI_x_uid17_fpSqrtTest_q = expXIsMax_uid14_fpSqrtTest_q & fracXIsZero_uid15_fpSqrtTest_q; - - // minInf_uid70_fpSqrtTest(LOGICAL,69)@14 - assign minInf_uid70_fpSqrtTest_q = excI_x_uid17_fpSqrtTest_q & redist12_signX_uid7_fpSqrtTest_b_14_q; - - // fracXIsNotZero_uid16_fpSqrtTest(LOGICAL,15)@14 - assign fracXIsNotZero_uid16_fpSqrtTest_q = ~ (fracXIsZero_uid15_fpSqrtTest_q); - - // excN_x_uid18_fpSqrtTest(LOGICAL,17)@14 - assign excN_x_uid18_fpSqrtTest_q = expXIsMax_uid14_fpSqrtTest_q & fracXIsNotZero_uid16_fpSqrtTest_q; - - // excRNaN_uid71_fpSqrtTest(LOGICAL,70)@14 - assign excRNaN_uid71_fpSqrtTest_q = excN_x_uid18_fpSqrtTest_q | minInf_uid70_fpSqrtTest_q | minReg_uid69_fpSqrtTest_q; - - // invSignX_uid67_fpSqrtTest(LOGICAL,66)@14 - assign invSignX_uid67_fpSqrtTest_q = ~ (redist12_signX_uid7_fpSqrtTest_b_14_q); - - // inInfAndNotNeg_uid68_fpSqrtTest(LOGICAL,67)@14 - assign inInfAndNotNeg_uid68_fpSqrtTest_q = excI_x_uid17_fpSqrtTest_q & invSignX_uid67_fpSqrtTest_q; - - // excConc_uid72_fpSqrtTest(BITJOIN,71)@14 - assign excConc_uid72_fpSqrtTest_q = {excRNaN_uid71_fpSqrtTest_q, inInfAndNotNeg_uid68_fpSqrtTest_q, excZ_x_uid13_fpSqrtTest_q}; - - // fracSelIn_uid73_fpSqrtTest(BITJOIN,72)@14 - assign fracSelIn_uid73_fpSqrtTest_q = {redist12_signX_uid7_fpSqrtTest_b_14_q, excConc_uid72_fpSqrtTest_q}; - - // fracSel_uid74_fpSqrtTest(LOOKUP,73)@14 + 1 + // redist9_expRMux_uid31_fpSqrtTest_q_10_wraddr(REG,123) always @ (posedge clk or posedge areset) begin if (areset) begin - fracSel_uid74_fpSqrtTest_q <= 2'b01; + redist9_expRMux_uid31_fpSqrtTest_q_10_wraddr_q <= 3'b110; + end + else + begin + redist9_expRMux_uid31_fpSqrtTest_q_10_wraddr_q <= redist9_expRMux_uid31_fpSqrtTest_q_10_rdmux_q; + end + end + + // redist9_expRMux_uid31_fpSqrtTest_q_10_mem(DUALMEM,120) + assign redist9_expRMux_uid31_fpSqrtTest_q_10_mem_ia = expRMux_uid31_fpSqrtTest_q; + assign redist9_expRMux_uid31_fpSqrtTest_q_10_mem_aa = redist9_expRMux_uid31_fpSqrtTest_q_10_wraddr_q; + assign redist9_expRMux_uid31_fpSqrtTest_q_10_mem_ab = redist9_expRMux_uid31_fpSqrtTest_q_10_rdmux_q; + assign redist9_expRMux_uid31_fpSqrtTest_q_10_mem_reset0 = areset; + altera_syncram #( + .ram_block_type("MLAB"), + .operation_mode("DUAL_PORT"), + .width_a(8), + .widthad_a(3), + .numwords_a(7), + .width_b(8), + .widthad_b(3), + .numwords_b(7), + .lpm_type("altera_syncram"), + .width_byteena_a(1), + .address_reg_b("CLOCK0"), + .indata_reg_b("CLOCK0"), + .rdcontrol_reg_b("CLOCK0"), + .byteena_reg_b("CLOCK0"), + .outdata_reg_b("CLOCK1"), + .outdata_aclr_b("CLEAR1"), + .clock_enable_input_a("NORMAL"), + .clock_enable_input_b("NORMAL"), + .clock_enable_output_b("NORMAL"), + .read_during_write_mode_mixed_ports("DONT_CARE"), + .power_up_uninitialized("TRUE"), + .intended_device_family("Arria 10") + ) redist9_expRMux_uid31_fpSqrtTest_q_10_mem_dmem ( + .clocken1(redist9_expRMux_uid31_fpSqrtTest_q_10_enaAnd_q[0]), + .clocken0(VCC_q[0]), + .clock0(clk), + .aclr1(redist9_expRMux_uid31_fpSqrtTest_q_10_mem_reset0), + .clock1(clk), + .address_a(redist9_expRMux_uid31_fpSqrtTest_q_10_mem_aa), + .data_a(redist9_expRMux_uid31_fpSqrtTest_q_10_mem_ia), + .wren_a(en[0]), + .address_b(redist9_expRMux_uid31_fpSqrtTest_q_10_mem_ab), + .q_b(redist9_expRMux_uid31_fpSqrtTest_q_10_mem_iq), + .wren_b(), + .rden_a(), + .rden_b(), + .data_b(), + .clocken2(), + .clocken3(), + .aclr0(), + .addressstall_a(), + .addressstall_b(), + .byteena_a(), + .byteena_b(), + .eccencbypass(), + .eccencparity(), + .sclr(), + .address2_a(), + .address2_b(), + .q_a(), + .eccstatus() + ); + assign redist9_expRMux_uid31_fpSqrtTest_q_10_mem_q = redist9_expRMux_uid31_fpSqrtTest_q_10_mem_iq[7:0]; + + // redist9_expRMux_uid31_fpSqrtTest_q_10_outputreg(DELAY,119) + dspba_delay_ver #( .width(8), .depth(1), .reset_kind("ASYNC") ) + redist9_expRMux_uid31_fpSqrtTest_q_10_outputreg ( .xin(redist9_expRMux_uid31_fpSqrtTest_q_10_mem_q), .xout(redist9_expRMux_uid31_fpSqrtTest_q_10_outputreg_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // expR_uid40_fpSqrtTest(ADD,39)@10 + assign expR_uid40_fpSqrtTest_a = {1'b0, redist9_expRMux_uid31_fpSqrtTest_q_10_outputreg_q}; + assign expR_uid40_fpSqrtTest_b = {8'b00000000, redist4_expInc_uid38_fpSqrtTest_b_1_q}; + assign expR_uid40_fpSqrtTest_o = $unsigned(expR_uid40_fpSqrtTest_a) + $unsigned(expR_uid40_fpSqrtTest_b); + assign expR_uid40_fpSqrtTest_q = expR_uid40_fpSqrtTest_o[8:0]; + + // expRR_uid51_fpSqrtTest(BITSELECT,50)@10 + assign expRR_uid51_fpSqrtTest_in = expR_uid40_fpSqrtTest_q[7:0]; + assign expRR_uid51_fpSqrtTest_b = expRR_uid51_fpSqrtTest_in[7:0]; + + // expXIsMax_uid14_fpSqrtTest(LOGICAL,13)@0 + 1 + assign expXIsMax_uid14_fpSqrtTest_qi = expX_uid6_fpSqrtTest_b == cstAllOWE_uid8_fpSqrtTest_q ? 1'b1 : 1'b0; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + expXIsMax_uid14_fpSqrtTest_delay ( .xin(expXIsMax_uid14_fpSqrtTest_qi), .xout(expXIsMax_uid14_fpSqrtTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // invExpXIsMax_uid19_fpSqrtTest(LOGICAL,18)@1 + assign invExpXIsMax_uid19_fpSqrtTest_q = ~ (expXIsMax_uid14_fpSqrtTest_q); + + // InvExpXIsZero_uid20_fpSqrtTest(LOGICAL,19)@1 + assign InvExpXIsZero_uid20_fpSqrtTest_q = ~ (excZ_x_uid13_fpSqrtTest_q); + + // excR_x_uid21_fpSqrtTest(LOGICAL,20)@1 + assign excR_x_uid21_fpSqrtTest_q = InvExpXIsZero_uid20_fpSqrtTest_q & invExpXIsMax_uid19_fpSqrtTest_q; + + // minReg_uid43_fpSqrtTest(LOGICAL,42)@1 + assign minReg_uid43_fpSqrtTest_q = excR_x_uid21_fpSqrtTest_q & redist10_signX_uid7_fpSqrtTest_b_1_q; + + // cstZeroWF_uid9_fpSqrtTest(CONSTANT,8) + assign cstZeroWF_uid9_fpSqrtTest_q = 23'b00000000000000000000000; + + // fracXIsZero_uid15_fpSqrtTest(LOGICAL,14)@0 + 1 + assign fracXIsZero_uid15_fpSqrtTest_qi = cstZeroWF_uid9_fpSqrtTest_q == frac_x_uid12_fpSqrtTest_b ? 1'b1 : 1'b0; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + fracXIsZero_uid15_fpSqrtTest_delay ( .xin(fracXIsZero_uid15_fpSqrtTest_qi), .xout(fracXIsZero_uid15_fpSqrtTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // excI_x_uid17_fpSqrtTest(LOGICAL,16)@1 + assign excI_x_uid17_fpSqrtTest_q = expXIsMax_uid14_fpSqrtTest_q & fracXIsZero_uid15_fpSqrtTest_q; + + // minInf_uid44_fpSqrtTest(LOGICAL,43)@1 + assign minInf_uid44_fpSqrtTest_q = excI_x_uid17_fpSqrtTest_q & redist10_signX_uid7_fpSqrtTest_b_1_q; + + // fracXIsNotZero_uid16_fpSqrtTest(LOGICAL,15)@1 + assign fracXIsNotZero_uid16_fpSqrtTest_q = ~ (fracXIsZero_uid15_fpSqrtTest_q); + + // excN_x_uid18_fpSqrtTest(LOGICAL,17)@1 + assign excN_x_uid18_fpSqrtTest_q = expXIsMax_uid14_fpSqrtTest_q & fracXIsNotZero_uid16_fpSqrtTest_q; + + // excRNaN_uid45_fpSqrtTest(LOGICAL,44)@1 + assign excRNaN_uid45_fpSqrtTest_q = excN_x_uid18_fpSqrtTest_q | minInf_uid44_fpSqrtTest_q | minReg_uid43_fpSqrtTest_q; + + // invSignX_uid41_fpSqrtTest(LOGICAL,40)@1 + assign invSignX_uid41_fpSqrtTest_q = ~ (redist10_signX_uid7_fpSqrtTest_b_1_q); + + // inInfAndNotNeg_uid42_fpSqrtTest(LOGICAL,41)@1 + assign inInfAndNotNeg_uid42_fpSqrtTest_q = excI_x_uid17_fpSqrtTest_q & invSignX_uid41_fpSqrtTest_q; + + // excConc_uid46_fpSqrtTest(BITJOIN,45)@1 + assign excConc_uid46_fpSqrtTest_q = {excRNaN_uid45_fpSqrtTest_q, inInfAndNotNeg_uid42_fpSqrtTest_q, excZ_x_uid13_fpSqrtTest_q}; + + // fracSelIn_uid47_fpSqrtTest(BITJOIN,46)@1 + assign fracSelIn_uid47_fpSqrtTest_q = {redist10_signX_uid7_fpSqrtTest_b_1_q, excConc_uid46_fpSqrtTest_q}; + + // fracSel_uid48_fpSqrtTest(LOOKUP,47)@1 + 1 + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + fracSel_uid48_fpSqrtTest_q <= 2'b01; end else if (en == 1'b1) begin - unique case (fracSelIn_uid73_fpSqrtTest_q) - 4'b0000 : fracSel_uid74_fpSqrtTest_q <= 2'b01; - 4'b0001 : fracSel_uid74_fpSqrtTest_q <= 2'b00; - 4'b0010 : fracSel_uid74_fpSqrtTest_q <= 2'b10; - 4'b0011 : fracSel_uid74_fpSqrtTest_q <= 2'b00; - 4'b0100 : fracSel_uid74_fpSqrtTest_q <= 2'b11; - 4'b0101 : fracSel_uid74_fpSqrtTest_q <= 2'b00; - 4'b0110 : fracSel_uid74_fpSqrtTest_q <= 2'b10; - 4'b0111 : fracSel_uid74_fpSqrtTest_q <= 2'b00; - 4'b1000 : fracSel_uid74_fpSqrtTest_q <= 2'b11; - 4'b1001 : fracSel_uid74_fpSqrtTest_q <= 2'b00; - 4'b1010 : fracSel_uid74_fpSqrtTest_q <= 2'b11; - 4'b1011 : fracSel_uid74_fpSqrtTest_q <= 2'b11; - 4'b1100 : fracSel_uid74_fpSqrtTest_q <= 2'b11; - 4'b1101 : fracSel_uid74_fpSqrtTest_q <= 2'b11; - 4'b1110 : fracSel_uid74_fpSqrtTest_q <= 2'b11; - 4'b1111 : fracSel_uid74_fpSqrtTest_q <= 2'b11; + unique case (fracSelIn_uid47_fpSqrtTest_q) + 4'b0000 : fracSel_uid48_fpSqrtTest_q <= 2'b01; + 4'b0001 : fracSel_uid48_fpSqrtTest_q <= 2'b00; + 4'b0010 : fracSel_uid48_fpSqrtTest_q <= 2'b10; + 4'b0011 : fracSel_uid48_fpSqrtTest_q <= 2'b00; + 4'b0100 : fracSel_uid48_fpSqrtTest_q <= 2'b11; + 4'b0101 : fracSel_uid48_fpSqrtTest_q <= 2'b00; + 4'b0110 : fracSel_uid48_fpSqrtTest_q <= 2'b10; + 4'b0111 : fracSel_uid48_fpSqrtTest_q <= 2'b00; + 4'b1000 : fracSel_uid48_fpSqrtTest_q <= 2'b11; + 4'b1001 : fracSel_uid48_fpSqrtTest_q <= 2'b00; + 4'b1010 : fracSel_uid48_fpSqrtTest_q <= 2'b11; + 4'b1011 : fracSel_uid48_fpSqrtTest_q <= 2'b11; + 4'b1100 : fracSel_uid48_fpSqrtTest_q <= 2'b11; + 4'b1101 : fracSel_uid48_fpSqrtTest_q <= 2'b11; + 4'b1110 : fracSel_uid48_fpSqrtTest_q <= 2'b11; + 4'b1111 : fracSel_uid48_fpSqrtTest_q <= 2'b11; default : begin // unreachable - fracSel_uid74_fpSqrtTest_q <= 2'bxx; + fracSel_uid48_fpSqrtTest_q <= 2'bxx; end endcase end end - // expRPostExc_uid79_fpSqrtTest(MUX,78)@15 - assign expRPostExc_uid79_fpSqrtTest_s = fracSel_uid74_fpSqrtTest_q; - always @(expRPostExc_uid79_fpSqrtTest_s or en or cstAllZWE_uid10_fpSqrtTest_q or expRR_uid77_fpSqrtTest_b or cstAllOWE_uid8_fpSqrtTest_q) + // redist2_fracSel_uid48_fpSqrtTest_q_9(DELAY,99) + dspba_delay_ver #( .width(2), .depth(8), .reset_kind("ASYNC") ) + redist2_fracSel_uid48_fpSqrtTest_q_9 ( .xin(fracSel_uid48_fpSqrtTest_q), .xout(redist2_fracSel_uid48_fpSqrtTest_q_9_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // expRPostExc_uid53_fpSqrtTest(MUX,52)@10 + assign expRPostExc_uid53_fpSqrtTest_s = redist2_fracSel_uid48_fpSqrtTest_q_9_q; + always @(expRPostExc_uid53_fpSqrtTest_s or en or cstAllZWE_uid10_fpSqrtTest_q or expRR_uid51_fpSqrtTest_b or cstAllOWE_uid8_fpSqrtTest_q) begin - unique case (expRPostExc_uid79_fpSqrtTest_s) - 2'b00 : expRPostExc_uid79_fpSqrtTest_q = cstAllZWE_uid10_fpSqrtTest_q; - 2'b01 : expRPostExc_uid79_fpSqrtTest_q = expRR_uid77_fpSqrtTest_b; - 2'b10 : expRPostExc_uid79_fpSqrtTest_q = cstAllOWE_uid8_fpSqrtTest_q; - 2'b11 : expRPostExc_uid79_fpSqrtTest_q = cstAllOWE_uid8_fpSqrtTest_q; - default : expRPostExc_uid79_fpSqrtTest_q = 8'b0; + unique case (expRPostExc_uid53_fpSqrtTest_s) + 2'b00 : expRPostExc_uid53_fpSqrtTest_q = cstAllZWE_uid10_fpSqrtTest_q; + 2'b01 : expRPostExc_uid53_fpSqrtTest_q = expRR_uid51_fpSqrtTest_b; + 2'b10 : expRPostExc_uid53_fpSqrtTest_q = cstAllOWE_uid8_fpSqrtTest_q; + 2'b11 : expRPostExc_uid53_fpSqrtTest_q = cstAllOWE_uid8_fpSqrtTest_q; + default : expRPostExc_uid53_fpSqrtTest_q = 8'b0; endcase end - // fracNaN_uid80_fpSqrtTest(CONSTANT,79) - assign fracNaN_uid80_fpSqrtTest_q = 23'b00000000000000000000001; + // fracNaN_uid54_fpSqrtTest(CONSTANT,53) + assign fracNaN_uid54_fpSqrtTest_q = 23'b00000000000000000000001; - // redist0_expUpdateCRU_uid61_fpSqrtTest_merged_bit_select_c_1(DELAY,125) + // fracRPostProcessings_uid39_fpSqrtTest(BITSELECT,38)@9 + assign fracRPostProcessings_uid39_fpSqrtTest_in = s2_uid85_invPolyEval_q[28:0]; + assign fracRPostProcessings_uid39_fpSqrtTest_b = fracRPostProcessings_uid39_fpSqrtTest_in[28:6]; + + // redist3_fracRPostProcessings_uid39_fpSqrtTest_b_1(DELAY,100) dspba_delay_ver #( .width(23), .depth(1), .reset_kind("ASYNC") ) - redist0_expUpdateCRU_uid61_fpSqrtTest_merged_bit_select_c_1 ( .xin(expUpdateCRU_uid61_fpSqrtTest_merged_bit_select_c), .xout(redist0_expUpdateCRU_uid61_fpSqrtTest_merged_bit_select_c_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + redist3_fracRPostProcessings_uid39_fpSqrtTest_b_1 ( .xin(fracRPostProcessings_uid39_fpSqrtTest_b), .xout(redist3_fracRPostProcessings_uid39_fpSqrtTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - // fracRPostExc_uid84_fpSqrtTest(MUX,83)@15 - assign fracRPostExc_uid84_fpSqrtTest_s = fracSel_uid74_fpSqrtTest_q; - always @(fracRPostExc_uid84_fpSqrtTest_s or en or cstZeroWF_uid9_fpSqrtTest_q or redist0_expUpdateCRU_uid61_fpSqrtTest_merged_bit_select_c_1_q or fracNaN_uid80_fpSqrtTest_q) + // fracRPostExc_uid58_fpSqrtTest(MUX,57)@10 + assign fracRPostExc_uid58_fpSqrtTest_s = redist2_fracSel_uid48_fpSqrtTest_q_9_q; + always @(fracRPostExc_uid58_fpSqrtTest_s or en or cstZeroWF_uid9_fpSqrtTest_q or redist3_fracRPostProcessings_uid39_fpSqrtTest_b_1_q or fracNaN_uid54_fpSqrtTest_q) begin - unique case (fracRPostExc_uid84_fpSqrtTest_s) - 2'b00 : fracRPostExc_uid84_fpSqrtTest_q = cstZeroWF_uid9_fpSqrtTest_q; - 2'b01 : fracRPostExc_uid84_fpSqrtTest_q = redist0_expUpdateCRU_uid61_fpSqrtTest_merged_bit_select_c_1_q; - 2'b10 : fracRPostExc_uid84_fpSqrtTest_q = cstZeroWF_uid9_fpSqrtTest_q; - 2'b11 : fracRPostExc_uid84_fpSqrtTest_q = fracNaN_uid80_fpSqrtTest_q; - default : fracRPostExc_uid84_fpSqrtTest_q = 23'b0; + unique case (fracRPostExc_uid58_fpSqrtTest_s) + 2'b00 : fracRPostExc_uid58_fpSqrtTest_q = cstZeroWF_uid9_fpSqrtTest_q; + 2'b01 : fracRPostExc_uid58_fpSqrtTest_q = redist3_fracRPostProcessings_uid39_fpSqrtTest_b_1_q; + 2'b10 : fracRPostExc_uid58_fpSqrtTest_q = cstZeroWF_uid9_fpSqrtTest_q; + 2'b11 : fracRPostExc_uid58_fpSqrtTest_q = fracNaN_uid54_fpSqrtTest_q; + default : fracRPostExc_uid58_fpSqrtTest_q = 23'b0; endcase end - // RSqrt_uid86_fpSqrtTest(BITJOIN,85)@15 - assign RSqrt_uid86_fpSqrtTest_q = {negZero_uid85_fpSqrtTest_q, expRPostExc_uid79_fpSqrtTest_q, fracRPostExc_uid84_fpSqrtTest_q}; + // RSqrt_uid60_fpSqrtTest(BITJOIN,59)@10 + assign RSqrt_uid60_fpSqrtTest_q = {redist1_negZero_uid59_fpSqrtTest_q_9_q, expRPostExc_uid53_fpSqrtTest_q, fracRPostExc_uid58_fpSqrtTest_q}; - // xOut(GPOUT,4)@15 - assign q = RSqrt_uid86_fpSqrtTest_q; + // xOut(GPOUT,4)@10 + assign q = RSqrt_uid60_fpSqrtTest_q; endmodule diff --git a/hw/rtl/fp_cores/altera/arria10/acl_gen.log b/hw/rtl/fp_cores/altera/arria10/acl_gen.log index ce8c8447..ca4112b7 100644 --- a/hw/rtl/fp_cores/altera/arria10/acl_gen.log +++ b/hw/rtl/fp_cores/altera/arria10/acl_gen.log @@ -4,97 +4,7 @@ argc=22 Generation context: Will not generate valid and channel signals HardFP is enabled enabling set to true - Correct rounding constraint detected - Will not generate valid and channel signals - The new component name is acl_fadd - Frequency 250MHz - Deployment FPGA Arria10 -Estimated resources LUTs 0, DSPs 2, RAMBits 0, RAMBlocks 0 -The pipeline depth of the block is 3 cycle(s) -@@start -@name FPAdd@ -@latency 3@ -@LUT 0@ -@DSP 2@ -@RAMBits 0@ -@RAMBlockUsage 0@ -@enable 1@ -@subnormals 0@ -@error 0.50@ -@rounding RNE@ -@method single path@ -@inPort 0 fpieee 8 23@ -@inPort 1 fpieee 8 23@ -@outPort 0 fpieee 8 23@ -@nochanvalid 1@ -@@end -starting execution ... -build model options ... -argc=22 -Generation context: - Will not generate valid and channel signals - HardFP is enabled enabling set to true - Correct rounding constraint detected - Will not generate valid and channel signals - The new component name is acl_fsub - Frequency 250MHz - Deployment FPGA Arria10 -Estimated resources LUTs 0, DSPs 2, RAMBits 0, RAMBlocks 0 -The pipeline depth of the block is 3 cycle(s) -@@start -@name FPSub@ -@latency 3@ -@LUT 0@ -@DSP 2@ -@RAMBits 0@ -@RAMBlockUsage 0@ -@enable 1@ -@subnormals 0@ -@error 0.50@ -@rounding RNE@ -@method single path@ -@inPort 0 fpieee 8 23@ -@inPort 1 fpieee 8 23@ -@outPort 0 fpieee 8 23@ -@nochanvalid 1@ -@@end -starting execution ... -build model options ... -argc=22 -Generation context: - Will not generate valid and channel signals - HardFP is enabled enabling set to true - Correct rounding constraint detected - Will not generate valid and channel signals - The new component name is acl_fmul - Frequency 250MHz - Deployment FPGA Arria10 -Estimated resources LUTs 0, DSPs 2, RAMBits 0, RAMBlocks 0 -The pipeline depth of the block is 3 cycle(s) -@@start -@name FPMul@ -@latency 3@ -@LUT 0@ -@DSP 2@ -@RAMBits 0@ -@RAMBlockUsage 0@ -@enable 1@ -@subnormals 0@ -@error 0.50@ -@rounding RNE@ -@method default@ -@inPort 0 fpieee 8 23@ -@inPort 1 fpieee 8 23@ -@outPort 0 fpieee 8 23@ -@nochanvalid 1@ -@@end -starting execution ... -build model options ... -argc=22 -Generation context: - Will not generate valid and channel signals - HardFP is enabled enabling set to true - Correct rounding constraint detected + Faithful rounding constraint detected Will not generate valid and channel signals The new component name is acl_fmadd Frequency 250MHz @@ -110,8 +20,8 @@ The pipeline depth of the block is 4 cycle(s) @RAMBlockUsage 0@ @enable 1@ @subnormals 0@ -@error 0.50@ -@rounding RNE@ +@error 1.00@ +@rounding NA@ @method multadd@ @inPort 0 fpieee 8 23@ @inPort 1 fpieee 8 23@ @@ -125,24 +35,24 @@ argc=23 Generation context: Will not generate valid and channel signals HardFP is enabled enabling set to true - Correct rounding constraint detected + Faithful rounding constraint detected Will not generate valid and channel signals The new component name is acl_fdiv Frequency 250MHz Deployment FPGA Arria10 -Estimated resources LUTs 1067, DSPs 7, RAMBits 34304, RAMBlocks 3 -The pipeline depth of the block is 20 cycle(s) +Estimated resources LUTs 539, DSPs 5, RAMBits 32768, RAMBlocks 3 +The pipeline depth of the block is 15 cycle(s) @@start @name FPDiv@ -@latency 20@ -@LUT 1067@ -@DSP 7@ -@RAMBits 34304@ +@latency 15@ +@LUT 539@ +@DSP 5@ +@RAMBits 32768@ @RAMBlockUsage 3@ @enable 1@ @subnormals 0@ -@error 0.50@ -@rounding RNE@ +@error 1.00@ +@rounding NA@ @method polynomial approximation@ @inPort 0 fpieee 8 23@ @inPort 1 fpieee 8 23@ @@ -155,142 +65,26 @@ argc=22 Generation context: Will not generate valid and channel signals HardFP is enabled enabling set to true - Correct rounding constraint detected + Faithful rounding constraint detected Will not generate valid and channel signals The new component name is acl_fsqrt Frequency 250MHz Deployment FPGA Arria10 -Estimated resources LUTs 518, DSPs 5, RAMBits 15872, RAMBlocks 3 -The pipeline depth of the block is 15 cycle(s) +Estimated resources LUTs 271, DSPs 3, RAMBits 15872, RAMBlocks 3 +The pipeline depth of the block is 10 cycle(s) @@start @name FPSqrt@ -@latency 15@ -@LUT 518@ -@DSP 5@ +@latency 10@ +@LUT 271@ +@DSP 3@ @RAMBits 15872@ @RAMBlockUsage 3@ @enable 1@ @subnormals 0@ -@error 0.50@ -@rounding RNE@ +@error 1.00@ +@rounding NA@ @method polynomial approximation@ @inPort 0 fpieee 8 23@ @outPort 0 fpieee 8 23@ @nochanvalid 1@ @@end -starting execution ... -build model options ... -argc=25 -Generation context: - Will not generate valid and channel signals - HardFP is enabled enabling set to true - Correct rounding constraint detected - Will not generate valid and channel signals - The new component name is acl_ftoi - Frequency 250MHz - Deployment FPGA Arria10 -Estimated resources LUTs 327, DSPs 0, RAMBits 0, RAMBlocks 0 -The pipeline depth of the block is 3 cycle(s) -@@start -@name FPToFXP@ -@latency 3@ -@LUT 327@ -@DSP 0@ -@RAMBits 0@ -@RAMBlockUsage 0@ -@enable 1@ -@subnormals 0@ -@error 0.50@ -@rounding RNE@ -@method default@ -@inPort 0 fpieee 8 23@ -@outPort 0 fxp 32 0 1@ -@nochanvalid 1@ -@@end -starting execution ... -build model options ... -argc=25 -Generation context: - Will not generate valid and channel signals - HardFP is enabled enabling set to true - Correct rounding constraint detected - Will not generate valid and channel signals - The new component name is acl_ftou - Frequency 250MHz - Deployment FPGA Arria10 -Estimated resources LUTs 287, DSPs 0, RAMBits 0, RAMBlocks 0 -The pipeline depth of the block is 3 cycle(s) -@@start -@name FPToFXP@ -@latency 3@ -@LUT 287@ -@DSP 0@ -@RAMBits 0@ -@RAMBlockUsage 0@ -@enable 1@ -@subnormals 0@ -@error 0.50@ -@rounding RNE@ -@method default@ -@inPort 0 fpieee 8 23@ -@outPort 0 fxp 32 0 0@ -@nochanvalid 1@ -@@end -starting execution ... -build model options ... -argc=25 -Generation context: - Will not generate valid and channel signals - HardFP is enabled enabling set to true - Correct rounding constraint detected - Will not generate valid and channel signals - The new component name is acl_itof - Frequency 250MHz - Deployment FPGA Arria10 -Estimated resources LUTs 397, DSPs 0, RAMBits 0, RAMBlocks 0 -The pipeline depth of the block is 7 cycle(s) -@@start -@name FXPToFP@ -@latency 7@ -@LUT 397@ -@DSP 0@ -@RAMBits 0@ -@RAMBlockUsage 0@ -@enable 1@ -@subnormals 0@ -@error 0.50@ -@rounding RNE@ -@method default@ -@inPort 0 fxp 32 0 1@ -@outPort 0 fpieee 8 23@ -@nochanvalid 1@ -@@end -starting execution ... -build model options ... -argc=25 -Generation context: - Will not generate valid and channel signals - HardFP is enabled enabling set to true - Correct rounding constraint detected - Will not generate valid and channel signals - The new component name is acl_utof - Frequency 300MHz - Deployment FPGA Arria10 -Estimated resources LUTs 363, DSPs 0, RAMBits 0, RAMBlocks 0 -The pipeline depth of the block is 7 cycle(s) -@@start -@name FXPToFP@ -@latency 7@ -@LUT 363@ -@DSP 0@ -@RAMBits 0@ -@RAMBlockUsage 0@ -@enable 1@ -@subnormals 0@ -@error 0.50@ -@rounding RNE@ -@method default@ -@inPort 0 fxp 32 0 0@ -@outPort 0 fpieee 8 23@ -@nochanvalid 1@ -@@end diff --git a/hw/rtl/fp_cores/altera/arria10/acl_gen.sh b/hw/rtl/fp_cores/altera/arria10/acl_gen.sh index 5eb811b9..feafed64 100755 --- a/hw/rtl/fp_cores/altera/arria10/acl_gen.sh +++ b/hw/rtl/fp_cores/altera/arria10/acl_gen.sh @@ -5,7 +5,7 @@ PREFIX=acl CMD_POLY_EVAL_PATH=$QUARTUS_HOME/dspba/backend/linux64 -OPTIONS="-target $FAMILY -noChanValid -enable -enableHardFP 1 -printMachineReadable -lang verilog -correctRounding -noChanValid -enable -speedgrade 2" +OPTIONS="-target $FAMILY -noChanValid -enable -enableHardFP 1 -printMachineReadable -lang verilog -faithfulRounding -noChanValid -enable -speedgrade 2" export LD_LIBRARY_PATH=$CMD_POLY_EVAL_PATH:$LD_LIBRARY_PATH diff --git a/hw/simulate/testbench.cpp b/hw/simulate/testbench.cpp index b4ea5feb..4fc1a579 100644 --- a/hw/simulate/testbench.cpp +++ b/hw/simulate/testbench.cpp @@ -5,153 +5,187 @@ //#define ALL_TESTS +static void show_usage() { + std::cout << "Usage: [-r] [-h: help] programs.." << std::endl; +} + +bool riscv_test = false; +std::vector programs; + +static void parse_args(int argc, char **argv) { + int c; + while ((c = getopt(argc, argv, "rh?")) != -1) { + switch (c) { + case 'r': + riscv_test = true; + break; + case 'h': + case '?': + show_usage(); + exit(0); + break; + default: + show_usage(); + exit(-1); + } + } + for (int i = optind; i < argc; ++i) { + programs.push_back(argv[i]); + } +} + int main(int argc, char **argv) { bool passed = true; if (argc == 1) { -#ifdef ALL_TESTS - std::string tests[] = { - "../../../benchmarks/riscv_tests/isa/rv32ui-p-add.hex", - "../../../benchmarks/riscv_tests/isa/rv32ui-p-addi.hex", - "../../../benchmarks/riscv_tests/isa/rv32ui-p-and.hex", - "../../../benchmarks/riscv_tests/isa/rv32ui-p-andi.hex", - "../../../benchmarks/riscv_tests/isa/rv32ui-p-auipc.hex", - "../../../benchmarks/riscv_tests/isa/rv32ui-p-beq.hex", - "../../../benchmarks/riscv_tests/isa/rv32ui-p-bge.hex", - "../../../benchmarks/riscv_tests/isa/rv32ui-p-bgeu.hex", - "../../../benchmarks/riscv_tests/isa/rv32ui-p-blt.hex", - "../../../benchmarks/riscv_tests/isa/rv32ui-p-bltu.hex", - "../../../benchmarks/riscv_tests/isa/rv32ui-p-bne.hex", - "../../../benchmarks/riscv_tests/isa/rv32ui-p-jal.hex", - "../../../benchmarks/riscv_tests/isa/rv32ui-p-jalr.hex", - "../../../benchmarks/riscv_tests/isa/rv32ui-p-lb.hex", - "../../../benchmarks/riscv_tests/isa/rv32ui-p-lbu.hex", - "../../../benchmarks/riscv_tests/isa/rv32ui-p-lh.hex", - "../../../benchmarks/riscv_tests/isa/rv32ui-p-lhu.hex", - "../../../benchmarks/riscv_tests/isa/rv32ui-p-lui.hex", - "../../../benchmarks/riscv_tests/isa/rv32ui-p-lw.hex", - "../../../benchmarks/riscv_tests/isa/rv32ui-p-or.hex", - "../../../benchmarks/riscv_tests/isa/rv32ui-p-ori.hex", - "../../../benchmarks/riscv_tests/isa/rv32ui-p-sb.hex", - "../../../benchmarks/riscv_tests/isa/rv32ui-p-sh.hex", - "../../../benchmarks/riscv_tests/isa/rv32ui-p-simple.hex", - "../../../benchmarks/riscv_tests/isa/rv32ui-p-sll.hex", - "../../../benchmarks/riscv_tests/isa/rv32ui-p-slli.hex", - "../../../benchmarks/riscv_tests/isa/rv32ui-p-slt.hex", - "../../../benchmarks/riscv_tests/isa/rv32ui-p-slti.hex", - "../../../benchmarks/riscv_tests/isa/rv32ui-p-sltiu.hex", - "../../../benchmarks/riscv_tests/isa/rv32ui-p-sltu.hex", - "../../../benchmarks/riscv_tests/isa/rv32ui-p-sra.hex", - "../../../benchmarks/riscv_tests/isa/rv32ui-p-srai.hex", - "../../../benchmarks/riscv_tests/isa/rv32ui-p-srl.hex", - "../../../benchmarks/riscv_tests/isa/rv32ui-p-srli.hex", - "../../../benchmarks/riscv_tests/isa/rv32ui-p-sub.hex", - "../../../benchmarks/riscv_tests/isa/rv32ui-p-sw.hex", - "../../../benchmarks/riscv_tests/isa/rv32ui-p-xor.hex", - "../../../benchmarks/riscv_tests/isa/rv32ui-p-xori.hex", -#ifdef EXT_M_ENABLE - "../../../benchmarks/riscv_tests/isa/rv32um-p-div.hex", - "../../../benchmarks/riscv_tests/isa/rv32um-p-divu.hex", - "../../../benchmarks/riscv_tests/isa/rv32um-p-mul.hex", - "../../../benchmarks/riscv_tests/isa/rv32um-p-mulh.hex", - "../../../benchmarks/riscv_tests/isa/rv32um-p-mulhsu.hex", - "../../../benchmarks/riscv_tests/isa/rv32um-p-mulhu.hex", - "../../../benchmarks/riscv_tests/isa/rv32um-p-rem.hex", - "../../../benchmarks/riscv_tests/isa/rv32um-p-remu.hex", -#endif - }; + #ifdef ALL_TESTS + std::string tests[] = { + "../../../benchmarks/riscv_tests/isa/rv32ui-p-add.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-addi.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-and.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-andi.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-auipc.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-beq.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-bge.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-bgeu.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-blt.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-bltu.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-bne.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-jal.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-jalr.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-lb.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-lbu.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-lh.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-lhu.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-lui.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-lw.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-or.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-ori.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-sb.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-sh.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-simple.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-sll.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-slli.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-slt.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-slti.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-sltiu.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-sltu.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-sra.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-srai.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-srl.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-srli.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-sub.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-sw.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-xor.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-xori.hex", + #ifdef EXT_M_ENABLE + "../../../benchmarks/riscv_tests/isa/rv32um-p-div.hex", + "../../../benchmarks/riscv_tests/isa/rv32um-p-divu.hex", + "../../../benchmarks/riscv_tests/isa/rv32um-p-mul.hex", + "../../../benchmarks/riscv_tests/isa/rv32um-p-mulh.hex", + "../../../benchmarks/riscv_tests/isa/rv32um-p-mulhsu.hex", + "../../../benchmarks/riscv_tests/isa/rv32um-p-mulhu.hex", + "../../../benchmarks/riscv_tests/isa/rv32um-p-rem.hex", + "../../../benchmarks/riscv_tests/isa/rv32um-p-remu.hex", + #endif + }; - std::string tests_fp[] = { -#ifdef EXT_F_ENABLE - "../../../benchmarks/riscv_tests/isa/rv32uf-p-fadd.hex", - "../../../benchmarks/riscv_tests/isa/rv32uf-p-fdiv.hex", - "../../../benchmarks/riscv_tests/isa/rv32uf-p-fmadd.hex", - "../../../benchmarks/riscv_tests/isa/rv32uf-p-fmin.hex", - "../../../benchmarks/riscv_tests/isa/rv32uf-p-fcmp.hex", - "../../../benchmarks/riscv_tests/isa/rv32uf-p-ldst.hex", - "../../../benchmarks/riscv_tests/isa/rv32uf-p-fcvt.hex", - "../../../benchmarks/riscv_tests/isa/rv32uf-p-fcvt_w.hex", - "../../../benchmarks/riscv_tests/isa/rv32uf-p-fclass.hex", - "../../../benchmarks/riscv_tests/isa/rv32uf-p-move.hex", - "../../../benchmarks/riscv_tests/isa/rv32uf-p-recoding.hex", -#endif - }; + std::string tests_fp[] = { + #ifdef EXT_F_ENABLE + "../../../benchmarks/riscv_tests/isa/rv32uf-p-fadd.hex", + "../../../benchmarks/riscv_tests/isa/rv32uf-p-fmadd.hex", + "../../../benchmarks/riscv_tests/isa/rv32uf-p-fmin.hex", + "../../../benchmarks/riscv_tests/isa/rv32uf-p-fcmp.hex", + "../../../benchmarks/riscv_tests/isa/rv32uf-p-ldst.hex", + "../../../benchmarks/riscv_tests/isa/rv32uf-p-fcvt.hex", + "../../../benchmarks/riscv_tests/isa/rv32uf-p-fcvt_w.hex", + "../../../benchmarks/riscv_tests/isa/rv32uf-p-move.hex", + "../../../benchmarks/riscv_tests/isa/rv32uf-p-recoding.hex", + "../../../benchmarks/riscv_tests/isa/rv32uf-p-fdiv.hex", + "../../../benchmarks/riscv_tests/isa/rv32uf-p-fclass.hex", + #endif + }; - for (std::string test : tests) { - std::cout << "\n---------------------------------------\n"; + for (std::string test : tests) { + std::cout << "\n---------------------------------------\n"; + + std::cout << test << std::endl; + + RAM ram; + Simulator simulator; + simulator.attach_ram(&ram); + simulator.load_ihex(test.c_str()); + simulator.run(); + + bool status = (1 == simulator.get_last_wb_value(3)); + + if (status) std::cout << "Passed: " << test << std::endl; + if (!status) std::cout << "Failed: " << test << std::endl; + passed = passed && status; + if (!passed) + break; + } + + for (std::string test : tests_fp) { + std::cout << "\n---------------------------------------\n"; + + std::cout << test << std::endl; + + RAM ram; + Simulator simulator; + simulator.attach_ram(&ram); + simulator.load_ihex(test.c_str()); + simulator.run(); + + bool status = (1 == simulator.get_last_wb_value(3)); + + if (status) std::cout << "Passed: " << test << std::endl; + if (!status) std::cout << "Failed: " << test << std::endl; + passed = passed && status; + if (!passed) + break; + } + + std::cout << "\n***************************************\n"; + + if (passed) std::cout << "PASSED ALL TESTS\n"; + if (!passed) std::cout << "Failed one or more tests\n"; + + #else + + char test[] = "../../../runtime/tests/simple/vx_simple.hex"; std::cout << test << std::endl; RAM ram; Simulator simulator; simulator.attach_ram(&ram); - simulator.load_ihex(test.c_str()); + simulator.load_ihex(test); simulator.run(); - bool status = (1 == simulator.get_last_wb_value(3)); + #endif - if (status) std::cout << "Passed: " << test << std::endl; - if (!status) std::cout << "Failed: " << test << std::endl; - passed = passed && status; - if (!passed) - break; - } + } else { + parse_args(argc, argv); - for (std::string test : tests_fp) { - std::cout << "\n---------------------------------------\n"; + for (auto program : programs) { + std::cout << "Running " << program << " .." << std::endl; - std::cout << test << std::endl; - - RAM ram; - Simulator simulator; - simulator.attach_ram(&ram); - simulator.load_ihex(test.c_str()); - simulator.run(); - - bool status = (1 == simulator.get_last_wb_value(3)); - - if (status) std::cout << "Passed: " << test << std::endl; - if (!status) std::cout << "Failed: " << test << std::endl; - passed = passed && status; - if (!passed) - break; - } - - std::cout << "\n***************************************\n"; - - if (passed) std::cout << "PASSED ALL TESTS\n"; - if (!passed) std::cout << "Failed one or more tests\n"; - - return !passed; - -#else - - char test[] = "../../../runtime/tests/simple/vx_simple.hex"; - - std::cout << test << std::endl; - - RAM ram; - Simulator simulator; - simulator.attach_ram(&ram); - simulator.load_ihex(test); - simulator.run(); - - return 0; - -#endif - -} else { - std::vector tests(argv+2, argv+argc); - for (std::string test : tests) { - std::cout << test << std::endl; - - RAM ram; - Simulator simulator; - simulator.attach_ram(&ram); - simulator.load_ihex(test.c_str()); - simulator.run(); + RAM ram; + Simulator simulator; + simulator.attach_ram(&ram); + simulator.load_ihex(program); + simulator.run(); + + if (riscv_test) { + bool status = (1 == simulator.get_last_wb_value(3)); + if (status) std::cout << "Passed." << std::endl; + if (!status) std::cout << "Failed." << std::endl; + passed = passed && status; + if (!passed) + break; + } + } } - return 0; -} - + return !passed; } diff --git a/runtime/tests/dev/Makefile b/runtime/tests/dev/Makefile index 649a80f2..d75be63e 100644 --- a/runtime/tests/dev/Makefile +++ b/runtime/tests/dev/Makefile @@ -28,7 +28,7 @@ $(PROJECT).elf: $(SRCS) $(CC) $(CFLAGS) $(SRCS) $(LDFLAGS) -o $(PROJECT).elf run: $(PROJECT).hex - (cd ../../../hw/simulate/obj_dir && ./VVortex -f ../../../runtime/tests/dev/$(PROJECT).hex) + (cd ../../../hw/simulate/obj_dir && ./VVortex ../../../runtime/tests/dev/$(PROJECT).hex) .depend: $(SRCS) $(CC) $(CFLAGS) -MM $^ > .depend; diff --git a/runtime/tests/hello/Makefile b/runtime/tests/hello/Makefile index 855795f8..e7abca97 100644 --- a/runtime/tests/hello/Makefile +++ b/runtime/tests/hello/Makefile @@ -28,7 +28,7 @@ $(PROJECT).elf: $(SRCS) $(CC) $(CFLAGS) $(SRCS) $(LDFLAGS) -o $(PROJECT).elf run: $(PROJECT).hex - (cd ../../../hw/simulate/obj_dir && ./VVortex -f ../../../runtime/tests/hello/$(PROJECT).hex) + (cd ../../../hw/simulate/obj_dir && ./VVortex ../../../runtime/tests/hello/$(PROJECT).hex) .depend: $(SRCS) $(CC) $(CFLAGS) -MM $^ > .depend; diff --git a/runtime/tests/nlTest/Makefile b/runtime/tests/nlTest/Makefile index 46a317a3..82200195 100644 --- a/runtime/tests/nlTest/Makefile +++ b/runtime/tests/nlTest/Makefile @@ -28,7 +28,7 @@ $(PROJECT).elf: $(SRCS) $(CC) $(CFLAGS) $(SRCS) $(LDFLAGS) -o $(PROJECT).elf run: $(PROJECT).hex - (cd ../../../hw/simulate/obj_dir && ./VVortex -f ../../../runtime/tests/nlTest/$(PROJECT).hex) + (cd ../../../hw/simulate/obj_dir && ./VVortex ../../../runtime/tests/nlTest/$(PROJECT).hex) .depend: $(SRCS) $(CC) $(CFLAGS) -MM $^ > .depend; diff --git a/runtime/tests/simple/Makefile b/runtime/tests/simple/Makefile index 9d26ab8a..4c061392 100644 --- a/runtime/tests/simple/Makefile +++ b/runtime/tests/simple/Makefile @@ -28,7 +28,7 @@ $(PROJECT).elf: $(SRCS) $(CC) $(CFLAGS) $(SRCS) $(LDFLAGS) -o $(PROJECT).elf run: $(PROJECT).hex - (cd ../../../hw/simulate/obj_dir && ./VVortex -f ../../../runtime/tests/simple/$(PROJECT).hex) + (cd ../../../hw/simulate/obj_dir && ./VVortex ../../../runtime/tests/simple/$(PROJECT).hex) .depend: $(SRCS) $(CC) $(CFLAGS) -MM $^ > .depend;