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code refactoring

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This commit is contained in:
Blaise Tine
2022-02-04 00:07:24 -05:00
parent 212ee21b54
commit cf2a0a5f39
58 changed files with 426 additions and 391 deletions
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2
sim/common/mem.cpp
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@@ -276,7 +276,7 @@ void RAM::loadHexImage(const char* filename) {
ifs.seekg(0, ifs.beg);
ifs.read(content.data(), size);
int offset = 0;
uint32_t offset = 0;
char *line = content.data();
this->clear();

1
sim/common/mem.h
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@@ -1,5 +1,6 @@
#pragma once
#include <cstdint>
#include <vector>
#include <unordered_map>

78
sim/common/rvfloats.cpp
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@@ -86,7 +86,7 @@ uint64_t rv_fmadd_d(uint64_t a, uint64_t b, uint64_t c, uint32_t frm, uint32_t*
uint32_t rv_fmsub_s(uint32_t a, uint32_t b, uint32_t c, uint32_t frm, uint32_t* fflags) {
softfloat_roundingMode = frm;
int c_neg = c ^ F32_SIGN;
auto c_neg = c ^ F32_SIGN;
auto r = f32_mulAdd(to_float32_t(a), to_float32_t(b), to_float32_t(c_neg));
if (fflags) { *fflags = get_fflags(); }
return from_float32_t(r);
@@ -94,7 +94,7 @@ uint32_t rv_fmsub_s(uint32_t a, uint32_t b, uint32_t c, uint32_t frm, uint32_t*
uint64_t rv_fmsub_d(uint64_t a, uint64_t b, uint64_t c, uint32_t frm, uint32_t* fflags) {
softfloat_roundingMode = frm;
long c_neg = c ^ F64_SIGN;
auto c_neg = c ^ F64_SIGN;
auto r = f64_mulAdd(to_float64_t(a), to_float64_t(b), to_float64_t(c_neg));
if (fflags) { *fflags = get_fflags(); }
return from_float64_t(r);
@@ -102,8 +102,8 @@ uint64_t rv_fmsub_d(uint64_t a, uint64_t b, uint64_t c, uint32_t frm, uint32_t*
uint32_t rv_fnmadd_s(uint32_t a, uint32_t b, uint32_t c, uint32_t frm, uint32_t* fflags) {
softfloat_roundingMode = frm;
int a_neg = a ^ F32_SIGN;
int c_neg = c ^ F32_SIGN;
auto a_neg = a ^ F32_SIGN;
auto c_neg = c ^ F32_SIGN;
auto r = f32_mulAdd(to_float32_t(a_neg), to_float32_t(b), to_float32_t(c_neg));
if (fflags) { *fflags = get_fflags(); }
return from_float32_t(r);
@@ -111,8 +111,8 @@ uint32_t rv_fnmadd_s(uint32_t a, uint32_t b, uint32_t c, uint32_t frm, uint32_t*
uint64_t rv_fnmadd_d(uint64_t a, uint64_t b, uint64_t c, uint32_t frm, uint32_t* fflags) {
softfloat_roundingMode = frm;
long a_neg = a ^ F64_SIGN;
long c_neg = c ^ F64_SIGN;
auto a_neg = a ^ F64_SIGN;
auto c_neg = c ^ F64_SIGN;
auto r = f64_mulAdd(to_float64_t(a_neg), to_float64_t(b), to_float64_t(c_neg));
if (fflags) { *fflags = get_fflags(); }
return from_float64_t(r);
@@ -120,7 +120,7 @@ uint64_t rv_fnmadd_d(uint64_t a, uint64_t b, uint64_t c, uint32_t frm, uint32_t*
uint32_t rv_fnmsub_s(uint32_t a, uint32_t b, uint32_t c, uint32_t frm, uint32_t* fflags) {
softfloat_roundingMode = frm;
int a_neg = a ^ F32_SIGN;
auto a_neg = a ^ F32_SIGN;
auto r = f32_mulAdd(to_float32_t(a_neg), to_float32_t(b), to_float32_t(c));
if (fflags) { *fflags = get_fflags(); }
return from_float32_t(r);
@@ -128,7 +128,7 @@ uint32_t rv_fnmsub_s(uint32_t a, uint32_t b, uint32_t c, uint32_t frm, uint32_t*
uint64_t rv_fnmsub_d(uint64_t a, uint64_t b, uint64_t c, uint32_t frm, uint32_t* fflags) {
softfloat_roundingMode = frm;
long a_neg = a ^ F64_SIGN;
auto a_neg = a ^ F64_SIGN;
auto r = f64_mulAdd(to_float64_t(a_neg), to_float64_t(b), to_float64_t(c));
if (fflags) { *fflags = get_fflags(); }
return from_float64_t(r);
@@ -312,7 +312,7 @@ uint64_t rv_feq_d(uint64_t a, uint64_t b, uint32_t* fflags) {
}
uint32_t rv_fmin_s(uint32_t a, uint32_t b, uint32_t* fflags) {
long r;
uint32_t r;
if (isNaNF32UI(a) && isNaNF32UI(b)) {
r = defaultNaNF32UI;
} else {
@@ -330,7 +330,7 @@ uint32_t rv_fmin_s(uint32_t a, uint32_t b, uint32_t* fflags) {
}
uint64_t rv_fmin_d(uint64_t a, uint64_t b, uint32_t* fflags) {
long r;
uint64_t r;
if (isNaNF64UI(a) && isNaNF64UI(b)) {
r = defaultNaNF64UI;
} else {
@@ -348,7 +348,7 @@ uint64_t rv_fmin_d(uint64_t a, uint64_t b, uint32_t* fflags) {
}
uint32_t rv_fmax_s(uint32_t a, uint32_t b, uint32_t* fflags) {
long r;
uint32_t r;
if (isNaNF32UI(a) && isNaNF32UI(b)) {
r = defaultNaNF32UI;
} else {
@@ -366,7 +366,7 @@ uint32_t rv_fmax_s(uint32_t a, uint32_t b, uint32_t* fflags) {
}
uint64_t rv_fmax_d(uint64_t a, uint64_t b, uint32_t* fflags) {
long r;
uint64_t r;
if (isNaNF64UI(a) && isNaNF64UI(b)) {
r = defaultNaNF64UI;
} else {
@@ -391,7 +391,7 @@ uint32_t rv_fclss_s(uint32_t a) {
bool isNaN = isNaNF32UI(a);
bool isSNaN = softfloat_isSigNaNF32UI(a);
int r =
uint32_t r =
( sign && infOrNaN && fracZero ) << 0 |
( sign && !infOrNaN && !subnormOrZero ) << 1 |
( sign && subnormOrZero && !fracZero ) << 2 |
@@ -406,7 +406,7 @@ uint32_t rv_fclss_s(uint32_t a) {
return r;
}
uint64_t rv_fclss_d(uint64_t a) {
uint32_t rv_fclss_d(uint64_t a) {
auto infOrNaN = (0x7ff == expF64UI(a));
auto subnormOrZero = (0 == expF64UI(a));
bool sign = signF64UI(a);
@@ -414,7 +414,7 @@ uint64_t rv_fclss_d(uint64_t a) {
bool isNaN = isNaNF64UI(a);
bool isSNaN = softfloat_isSigNaNF64UI(a);
int r =
uint32_t r =
( sign && infOrNaN && fracZero ) << 0 |
( sign && !infOrNaN && !subnormOrZero ) << 1 |
( sign && subnormOrZero && !fracZero ) << 2 |
@@ -430,63 +430,49 @@ uint64_t rv_fclss_d(uint64_t a) {
}
uint32_t rv_fsgnj_s(uint32_t a, uint32_t b) {
int sign = b & F32_SIGN;
int r = sign | (a & ~F32_SIGN);
auto sign = b & F32_SIGN;
auto r = sign | (a & ~F32_SIGN);
return r;
}
uint64_t rv_fsgnj_d(uint64_t a, uint64_t b) {
long sign = b & F64_SIGN;
long r = sign | (a & ~F64_SIGN);
uint64_t rv_fsgnj_d(uint64_t a, uint64_t b) {
auto sign = b & F64_SIGN;
auto r = sign | (a & ~F64_SIGN);
return r;
}
uint32_t rv_fsgnjn_s(uint32_t a, uint32_t b) {
int sign = ~b & F32_SIGN;
int r = sign | (a & ~F32_SIGN);
auto sign = ~b & F32_SIGN;
auto r = sign | (a & ~F32_SIGN);
return r;
}
uint64_t rv_fsgnjn_d(uint64_t a, uint64_t b) {
long sign = ~b & F64_SIGN;
long r = sign | (a & ~F64_SIGN);
uint64_t rv_fsgnjn_d(uint64_t a, uint64_t b) {
auto sign = ~b & F64_SIGN;
auto r = sign | (a & ~F64_SIGN);
return r;
}
uint32_t rv_fsgnjx_s(uint32_t a, uint32_t b) {
int sign1 = a & F32_SIGN;
int sign2 = b & F32_SIGN;
int r = (sign1 ^ sign2) | (a & ~F32_SIGN);
auto sign1 = a & F32_SIGN;
auto sign2 = b & F32_SIGN;
auto r = (sign1 ^ sign2) | (a & ~F32_SIGN);
return r;
}
uint64_t rv_fsgnjx_d(uint64_t a, uint64_t b) {
long sign1 = a & F64_SIGN;
long sign2 = b & F64_SIGN;
long r = (sign1 ^ sign2) | (a & ~F64_SIGN);
uint64_t rv_fsgnjx_d(uint64_t a, uint64_t b) {
auto sign1 = a & F64_SIGN;
auto sign2 = b & F64_SIGN;
auto r = (sign1 ^ sign2) | (a & ~F64_SIGN);
return r;
}
uint32_t rv_dtof(uint64_t a) {
auto r = f64_to_f32(to_float64_t(a));
return from_float32_t(r);
}
uint64_t rv_ftod(uint32_t a) {
auto r = f32_to_f64(to_float32_t(a));
return from_float64_t(r);
}

3
sim/common/rvfloats.h
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@@ -38,6 +38,7 @@ uint32_t rv_feq_s(uint32_t a, uint32_t b, uint32_t* fflags);
uint32_t rv_fmin_s(uint32_t a, uint32_t b, uint32_t* fflags);
uint32_t rv_fmax_s(uint32_t a, uint32_t b, uint32_t* fflags);
///////////////////////////////////////////////////////////////////////////////
uint64_t rv_fadd_d(uint64_t a, uint64_t b, uint32_t frm, uint32_t* fflags);
uint64_t rv_fsub_d(uint64_t a, uint64_t b, uint32_t frm, uint32_t* fflags);
@@ -59,7 +60,7 @@ uint64_t rv_utof_d(uint64_t a, uint32_t frm, uint32_t* fflags);
uint64_t rv_ltof_d(uint64_t a, uint32_t frm, uint32_t* fflags);
uint64_t rv_lutof_d(uint64_t a, uint32_t frm, uint32_t* fflags);
uint64_t rv_fclss_d(uint64_t a);
uint32_t rv_fclss_d(uint64_t a);
uint64_t rv_fsgnj_d(uint64_t a, uint64_t b);
uint64_t rv_fsgnjn_d(uint64_t a, uint64_t b);
uint64_t rv_fsgnjx_d(uint64_t a, uint64_t b);

2
sim/common/texturing.h
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@@ -56,7 +56,7 @@ inline void Unpack8888(TexFormat format,
uint32_t texel,
uint32_t* lo,
uint32_t* hi) {
int r, g, b, a;
uint32_t r, g, b, a;
switch (format) {
case TexFormat::A8R8G8B8:
r = (texel >> 16) & 0xff;

5
sim/simx/Makefile
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@@ -36,11 +36,6 @@ ifdef XLEN
CXXFLAGS += -DXLEN=$(XLEN)
endif
# FLEN parameterization
ifdef FLEN
CXXFLAGS += -DFLEN=$(FLEN)
endif
PROJECT = simx
all: $(DESTDIR)/$(PROJECT)

4
sim/simx/archdef.h
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@@ -21,8 +21,7 @@ private:
uint16_t num_barriers_;
public:
ArchDef(const std::string& /*arch*/,
uint16_t num_cores,
ArchDef(uint16_t num_cores,
uint16_t num_warps,
uint16_t num_threads)
: num_cores_(num_cores)
@@ -67,4 +66,5 @@ public:
return num_cores_;
}
};
}

8
sim/simx/cache.cpp
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@@ -42,7 +42,7 @@ struct params_t {
assert(config.ports_per_bank <= this->words_per_block);
// uint32_t select
// Word select
this->word_select_addr_start = config.W;
this->word_select_addr_end = (this->word_select_addr_start+offset_bits-1);
@@ -488,11 +488,11 @@ private:
} else {
bool hit = false;
bool found_free_block = false;
int hit_block_id = 0;
int repl_block_id = 0;
uint32_t hit_block_id = 0;
uint32_t repl_block_id = 0;
uint32_t max_cnt = 0;
for (int i = 0, n = set.blocks.size(); i < n; ++i) {
for (uint32_t i = 0, n = set.blocks.size(); i < n; ++i) {
auto& block = set.blocks.at(i);
if (block.valid) {
if (block.tag == pipeline_req.tag) {

18
sim/simx/core.cpp
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@@ -73,7 +73,7 @@ Core::Core(const SimContext& ctx, const ArchDef &arch, uint32_t id)
, decode_latch_("decode")
, pending_icache_(arch_.num_warps())
{
for (int i = 0; i < arch_.num_warps(); ++i) {
for (uint32_t i = 0; i < arch_.num_warps(); ++i) {
warps_.at(i) = std::make_shared<Warp>(this, i);
}
@@ -195,7 +195,7 @@ void Core::tick() {
void Core::schedule() {
bool foundSchedule = false;
int scheduled_warp = last_schedule_wid_;
uint32_t scheduled_warp = last_schedule_wid_;
// round robin scheduling
for (size_t wid = 0, nw = arch_.num_warps(); wid < nw; ++wid) {
@@ -367,11 +367,11 @@ void Core::commit() {
}
}
WarpMask Core::wspawn(int num_warps, int nextPC) {
WarpMask Core::wspawn(uint32_t num_warps, uint32_t nextPC) {
WarpMask ret(1);
int active_warps = std::min<int>(num_warps, arch_.num_warps());
uint32_t active_warps = std::min<uint32_t>(num_warps, arch_.num_warps());
DP(3, "*** Activate " << (active_warps-1) << " warps at PC: " << std::hex << nextPC);
for (int i = 1; i < active_warps; ++i) {
for (uint32_t i = 1; i < active_warps; ++i) {
auto warp = warps_.at(i);
warp->setPC(nextPC);
warp->setTmask(0, true);
@@ -380,7 +380,7 @@ WarpMask Core::wspawn(int num_warps, int nextPC) {
return std::move(ret);
}
WarpMask Core::barrier(int bar_id, int count, int warp_id) {
WarpMask Core::barrier(uint32_t bar_id, uint32_t count, uint32_t warp_id) {
WarpMask ret(0);
auto& barrier = barriers_.at(bar_id);
barrier.set(warp_id);
@@ -389,7 +389,7 @@ WarpMask Core::barrier(int bar_id, int count, int warp_id) {
DP(3, "*** Suspend warp #" << warp_id << " at barrier #" << bar_id);
return std::move(ret);
}
for (int i = 0; i < arch_.num_warps(); ++i) {
for (uint32_t i = 0; i < arch_.num_warps(); ++i) {
if (barrier.test(i)) {
DP(3, "*** Resume warp #" << i << " at barrier #" << bar_id);
warps_.at(i)->activate();
@@ -446,7 +446,7 @@ void Core::writeToStdOut(Addr addr, uint32_t data) {
}
}
uint32_t Core::get_csr(Addr addr, int tid, int wid) {
uint32_t Core::get_csr(Addr addr, uint32_t tid, uint32_t wid) {
switch (addr) {
case CSR_SATP:
case CSR_PMPCFG0:
@@ -644,7 +644,7 @@ uint32_t Core::get_csr(Addr addr, int tid, int wid) {
return 0;
}
void Core::set_csr(Addr addr, uint32_t value, int /*tid*/, int wid) {
void Core::set_csr(Addr addr, uint32_t value, uint32_t /*tid*/, uint32_t wid) {
if (addr == CSR_FFLAGS) {
fcsrs_.at(wid) = (fcsrs_.at(wid) & ~0x1F) | (value & 0x1F);
} else if (addr == CSR_FRM) {

8
sim/simx/core.h
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@@ -99,13 +99,13 @@ public:
return warps_.at(0)->getIRegValue(reg);
}
uint32_t get_csr(Addr addr, int tid, int wid);
uint32_t get_csr(Addr addr, uint32_t tid, uint32_t wid);
void set_csr(Addr addr, uint32_t value, int tid, int wid);
void set_csr(Addr addr, uint32_t value, uint32_t tid, uint32_t wid);
WarpMask wspawn(int num_warps, int nextPC);
WarpMask wspawn(uint32_t num_warps, uint32_t nextPC);
WarpMask barrier(int bar_id, int count, int warp_id);
WarpMask barrier(uint32_t bar_id, uint32_t count, uint32_t warp_id);
uint32_t icache_read(Addr, Size);

4
sim/simx/decode.cpp
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@@ -351,7 +351,7 @@ std::ostream &operator<<(std::ostream &os, const Instr &instr) {
if (instr.getRDType() != RegType::None) {
os << instr.getRDType() << std::dec << instr.getRDest() << " <- ";
}
int i = 0;
uint32_t i = 0;
for (; i < instr.getNRSrc(); ++i) {
if (i) os << ", ";
os << instr.getRSType(i) << std::dec << instr.getRSrc(i);
@@ -552,7 +552,7 @@ std::shared_ptr<Instr> Decoder::decode(uint32_t code) const {
uint32_t bit_11 = (unordered >> 8) & 0x1;
uint32_t bits_10_1 = (unordered >> 9) & 0x3ff;
uint32_t bit_20 = (unordered >> 19) & 0x1;
Word imm = (Word) 0 | (bits_10_1 << 1) | (bit_11 << 11) | (bits_19_12 << 12) | (bit_20 << 20);
Word imm = (bits_10_1 << 1) | (bit_11 << 11) | (bits_19_12 << 12) | (bit_20 << 20);
if (bit_20) {
imm |= ~j_imm_mask_;
}

320
sim/simx/execute.cpp
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File diff suppressed because it is too large Load Diff

28
sim/simx/instr.h
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@@ -59,19 +59,19 @@ public:
, rdest_(0)
, func3_(0)
, func7_(0) {
for (int i = 0; i < MAX_REG_SOURCES; ++i) {
for (uint32_t i = 0; i < MAX_REG_SOURCES; ++i) {
rsrc_type_[i] = RegType::None;
}
}
/* Setters used to "craft" the instruction. */
void setOpcode(Opcode opcode) { opcode_ = opcode; }
void setDestReg(int destReg) { rdest_type_ = RegType::Integer; rdest_ = destReg; }
void setSrcReg(int srcReg) { rsrc_type_[num_rsrcs_] = RegType::Integer; rsrc_[num_rsrcs_++] = srcReg; }
void setDestFReg(int destReg) { rdest_type_ = RegType::Float; rdest_ = destReg; }
void setSrcFReg(int srcReg) { rsrc_type_[num_rsrcs_] = RegType::Float; rsrc_[num_rsrcs_++] = srcReg; }
void setDestVReg(int destReg) { rdest_type_ = RegType::Vector; rdest_ = destReg; }
void setSrcVReg(int srcReg) { rsrc_type_[num_rsrcs_] = RegType::Vector; rsrc_[num_rsrcs_++] = srcReg; }
void setDestReg(uint32_t destReg) { rdest_type_ = RegType::Integer; rdest_ = destReg; }
void setSrcReg(uint32_t srcReg) { rsrc_type_[num_rsrcs_] = RegType::Integer; rsrc_[num_rsrcs_++] = srcReg; }
void setDestFReg(uint32_t destReg) { rdest_type_ = RegType::Float; rdest_ = destReg; }
void setSrcFReg(uint32_t srcReg) { rsrc_type_[num_rsrcs_] = RegType::Float; rsrc_[num_rsrcs_++] = srcReg; }
void setDestVReg(uint32_t destReg) { rdest_type_ = RegType::Vector; rdest_ = destReg; }
void setSrcVReg(uint32_t srcReg) { rsrc_type_[num_rsrcs_] = RegType::Vector; rsrc_[num_rsrcs_++] = srcReg; }
void setFunc2(uint32_t func2) { func2_ = func2; }
void setFunc3(uint32_t func3) { func3_ = func3; }
void setFunc7(uint32_t func7) { func7_ = func7; }
@@ -93,10 +93,10 @@ public:
uint32_t getFunc3() const { return func3_; }
uint32_t getFunc6() const { return func6_; }
uint32_t getFunc7() const { return func7_; }
int getNRSrc() const { return num_rsrcs_; }
int getRSrc(int i) const { return rsrc_[i]; }
RegType getRSType(int i) const { return rsrc_type_[i]; }
int getRDest() const { return rdest_; }
uint32_t getNRSrc() const { return num_rsrcs_; }
uint32_t getRSrc(uint32_t i) const { return rsrc_[i]; }
RegType getRSType(uint32_t i) const { return rsrc_type_[i]; }
uint32_t getRDest() const { return rdest_; }
RegType getRDType() const { return rdest_type_; }
bool hasImm() const { return has_imm_; }
Word getImm() const { return imm_; }
@@ -116,13 +116,13 @@ private:
};
Opcode opcode_;
int num_rsrcs_;
uint32_t num_rsrcs_;
bool has_imm_;
RegType rdest_type_;
Word imm_;
RegType rsrc_type_[MAX_REG_SOURCES];
int rsrc_[MAX_REG_SOURCES];
int rdest_;
uint32_t rsrc_[MAX_REG_SOURCES];
uint32_t rdest_;
uint32_t func2_;
uint32_t func3_;
uint32_t func6_;

5
sim/simx/main.cpp
View File

@@ -18,7 +18,6 @@ using namespace vortex;
int main(int argc, char **argv) {
int exitcode = 0;
std::string archStr("rv32imf");
std::string imgFileName;
int num_cores(NUM_CORES * NUM_CLUSTERS);
int num_warps(NUM_WARPS);
@@ -29,7 +28,6 @@ int main(int argc, char **argv) {
/* Read the command line arguments. */
CommandLineArgFlag fh("-h", "--help", "", showHelp);
CommandLineArgSetter<std::string> fa("-a", "--arch", "", archStr);
CommandLineArgSetter<std::string> fi("-i", "--image", "", imgFileName);
CommandLineArgSetter<int> fc("-c", "--cores", "", num_cores);
CommandLineArgSetter<int> fw("-w", "--warps", "", num_warps);
@@ -45,7 +43,6 @@ int main(int argc, char **argv) {
" -c, --cores <num> Number of cores\n"
" -w, --warps <num> Number of warps\n"
" -t, --threads <num> Number of threads\n"
" -a, --arch <arch string> Architecture string\n"
" -r, --riscv riscv test\n"
" -s, --stats Print stats on exit.\n";
return 0;
@@ -55,7 +52,7 @@ int main(int argc, char **argv) {
{
// create processor configuation
ArchDef arch(archStr, num_cores, num_warps, num_threads);
ArchDef arch(num_cores, num_warps, num_threads);
// create memory module
RAM ram(RAM_PAGE_SIZE);

6
sim/simx/pipeline.h
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@@ -15,8 +15,8 @@ struct pipeline_trace_t {
uint64_t uuid;
//--
int cid;
int wid;
uint32_t cid;
uint32_t wid;
ThreadMask tmask;
Word PC;
@@ -26,7 +26,7 @@ struct pipeline_trace_t {
//--
bool wb;
RegType rdest_type;
int rdest;
uint32_t rdest;
//--
RegMask used_iregs;

2
sim/simx/scoreboard.h
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@@ -28,7 +28,7 @@ public:
}
void clear() {
for (int i = 0, n = in_use_iregs_.size(); i < n; ++i) {
for (uint32_t i = 0, n = in_use_iregs_.size(); i < n; ++i) {
in_use_iregs_.at(i).reset();
in_use_fregs_.at(i).reset();
in_use_vregs_.at(i).reset();

41
sim/simx/types.h
View File

@@ -8,31 +8,28 @@
#include <VX_config.h>
#include <simobject.h>
#if XLEN == 32
#define uintx_t uint32_t
#define intx_t int32_t
#define uintd_t uint64_t
#define intd_t int64_t
#elif XLEN == 64
#define uintx_t uint64_t
#define intx_t int64_t
#define uintd_t __uint128_t
#define intd_t __int128_t
#else
#error unsupported XLEN
#endif
namespace vortex {
typedef uint8_t Byte;
typedef uintx_t Word;
typedef intx_t WordI;
typedef uintd_t DWord;
typedef intd_t DWordI;
typedef uint64_t FWord;
typedef uintx_t Addr;
#if XLEN == 32
typedef uint32_t Word;
typedef int32_t WordI;
typedef uint64_t DWord;
typedef int64_t DWordI;
typedef uint32_t Addr;
typedef uint32_t Size;
typedef uint32_t FWord;
#elif XLEN == 64
typedef uint64_t Word;
typedef int64_t WordI;
typedef __uint128_t DWord;
typedef __int128_t DWordI;
typedef uint64_t Addr;
typedef uint64_t Size;
typedef uint64_t FWord;
#else
#error unsupported XLEN
#endif
typedef std::bitset<32> RegMask;
typedef std::bitset<32> ThreadMask;
@@ -249,7 +246,7 @@ struct MemReq {
inline std::ostream &operator<<(std::ostream &os, const MemReq& req) {
os << "mem-" << (req.write ? "wr" : "rd") << ": ";
os << "addr=" << req.addr << ", tag=" << req.tag << ", core_id=" << req.core_id;
os << "addr=" << std::hex << req.addr << std::dec << ", tag=" << req.tag << ", core_id=" << req.core_id;
os << " (#" << std::dec << req.uuid << ")";
return os;
}

10
sim/simx/warp.cpp
View File

@@ -24,7 +24,7 @@ void Warp::clear() {
active_ = false;
PC_ = STARTUP_ADDR;
tmask_.reset();
for (int i = 0, n = core_->arch().num_threads(); i < n; ++i) {
for (uint32_t i = 0, n = core_->arch().num_threads(); i < n; ++i) {
for (auto& reg : ireg_file_.at(i)) {
reg = 0;
}
@@ -41,7 +41,7 @@ void Warp::eval(pipeline_trace_t *trace) {
assert(tmask_.any());
DPH(2, "Fetch: coreid=" << core_->id() << ", wid=" << id_ << ", tmask=");
for (int i = 0, n = core_->arch().num_threads(); i < n; ++i)
for (uint32_t i = 0, n = core_->arch().num_threads(); i < n; ++i)
DPN(2, tmask_.test(n-i-1));
DPN(2, ", PC=0x" << std::hex << PC_ << " (#" << std::dec << trace->uuid << ")" << std::endl);
@@ -68,15 +68,15 @@ void Warp::eval(pipeline_trace_t *trace) {
this->execute(*instr, trace);
DP(4, "Register state:");
for (int i = 0; i < core_->arch().num_regs(); ++i) {
for (uint32_t i = 0; i < core_->arch().num_regs(); ++i) {
DPN(4, " %r" << std::setfill('0') << std::setw(2) << std::dec << i << ':');
// Integer register file
for (int j = 0; j < core_->arch().num_threads(); ++j) {
for (uint32_t j = 0; j < core_->arch().num_threads(); ++j) {
DPN(4, ' ' << std::setfill('0') << std::setw(XLEN/4) << std::hex << ireg_file_.at(j).at(i) << std::setfill(' ') << ' ');
}
DPN(4, '|');
// Floating point register file
for (int j = 0; j < core_->arch().num_threads(); ++j) {
for (uint32_t j = 0; j < core_->arch().num_threads(); ++j) {
DPN(4, ' ' << std::setfill('0') << std::setw(16) << std::hex << freg_file_.at(j).at(i) << std::setfill(' ') << ' ');
}
DPN(4, std::endl);

12
sim/simx/warp.h
View File

@@ -32,10 +32,10 @@ struct DomStackEntry {
};
struct vtype {
int vill;
int vediv;
int vsew;
int vlmul;
uint32_t vill;
uint32_t vediv;
uint32_t vsew;
uint32_t vlmul;
};
class Warp {
@@ -85,7 +85,7 @@ public:
return 0;
}
uint32_t getIRegValue(int reg) const {
uint32_t getIRegValue(uint32_t reg) const {
return ireg_file_.at(0).at(reg);
}
@@ -108,7 +108,7 @@ private:
std::stack<DomStackEntry> dom_stack_;
struct vtype vtype_;
int vl_;
uint32_t vl_;
};
}