Started on rtl (Finished till decode)
This commit is contained in:
felsabbagh3
304
rtl/obj_dir/Vvortex.cpp
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304
rtl/obj_dir/Vvortex.cpp
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// Verilated -*- C++ -*-
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// DESCRIPTION: Verilator output: Design implementation internals
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// See Vvortex.h for the primary calling header
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#include "Vvortex.h"
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#include "Vvortex__Syms.h"
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//--------------------
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// STATIC VARIABLES
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//--------------------
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VL_CTOR_IMP(Vvortex) {
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Vvortex__Syms* __restrict vlSymsp = __VlSymsp = new Vvortex__Syms(this, name());
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Vvortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
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// Reset internal values
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// Reset structure values
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_ctor_var_reset();
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}
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void Vvortex::__Vconfigure(Vvortex__Syms* vlSymsp, bool first) {
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if (0 && first) {} // Prevent unused
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this->__VlSymsp = vlSymsp;
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}
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Vvortex::~Vvortex() {
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delete __VlSymsp; __VlSymsp=NULL;
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}
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//--------------------
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void Vvortex::eval() {
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VL_DEBUG_IF(VL_DBG_MSGF("+++++TOP Evaluate Vvortex::eval\n"); );
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Vvortex__Syms* __restrict vlSymsp = this->__VlSymsp; // Setup global symbol table
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Vvortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
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#ifdef VL_DEBUG
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// Debug assertions
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_eval_debug_assertions();
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#endif // VL_DEBUG
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// Initialize
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if (VL_UNLIKELY(!vlSymsp->__Vm_didInit)) _eval_initial_loop(vlSymsp);
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// Evaluate till stable
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int __VclockLoop = 0;
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QData __Vchange = 1;
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do {
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VL_DEBUG_IF(VL_DBG_MSGF("+ Clock loop\n"););
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_eval(vlSymsp);
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if (VL_UNLIKELY(++__VclockLoop > 100)) {
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// About to fail, so enable debug to see what's not settling.
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// Note you must run make with OPT=-DVL_DEBUG for debug prints.
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int __Vsaved_debug = Verilated::debug();
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Verilated::debug(1);
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__Vchange = _change_request(vlSymsp);
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Verilated::debug(__Vsaved_debug);
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VL_FATAL_MT(__FILE__,__LINE__,__FILE__,"Verilated model didn't converge");
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} else {
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__Vchange = _change_request(vlSymsp);
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}
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} while (VL_UNLIKELY(__Vchange));
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}
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void Vvortex::_eval_initial_loop(Vvortex__Syms* __restrict vlSymsp) {
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vlSymsp->__Vm_didInit = true;
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_eval_initial(vlSymsp);
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// Evaluate till stable
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int __VclockLoop = 0;
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QData __Vchange = 1;
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do {
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_eval_settle(vlSymsp);
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_eval(vlSymsp);
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if (VL_UNLIKELY(++__VclockLoop > 100)) {
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// About to fail, so enable debug to see what's not settling.
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// Note you must run make with OPT=-DVL_DEBUG for debug prints.
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int __Vsaved_debug = Verilated::debug();
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Verilated::debug(1);
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__Vchange = _change_request(vlSymsp);
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Verilated::debug(__Vsaved_debug);
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VL_FATAL_MT(__FILE__,__LINE__,__FILE__,"Verilated model didn't DC converge");
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} else {
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__Vchange = _change_request(vlSymsp);
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}
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} while (VL_UNLIKELY(__Vchange));
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}
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//--------------------
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// Internal Methods
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void Vvortex::_settle__TOP__1(Vvortex__Syms* __restrict vlSymsp) {
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VL_DEBUG_IF(VL_DBG_MSGF("+ Vvortex::_settle__TOP__1\n"); );
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Vvortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
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// Body
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vlTOPp->fe_delay = 0U;
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vlTOPp->de_instruction = vlTOPp->vortex__DOT__vx_f_d_reg__DOT__instruction;
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}
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VL_INLINE_OPT void Vvortex::_sequent__TOP__2(Vvortex__Syms* __restrict vlSymsp) {
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VL_DEBUG_IF(VL_DBG_MSGF("+ Vvortex::_sequent__TOP__2\n"); );
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Vvortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
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// Body
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// ALWAYS at VX_fetch.v:128
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vlTOPp->vortex__DOT__vx_fetch__DOT__delay_reg = 0U;
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// ALWAYS at VX_fetch.v:128
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vlTOPp->vortex__DOT__vx_fetch__DOT__stall_reg = 0U;
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// ALWAYS at VX_fetch.v:128
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vlTOPp->vortex__DOT__vx_fetch__DOT__JAL_reg = ((IData)(vlTOPp->reset)
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? 0U
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: 4U);
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// ALWAYS at VX_fetch.v:128
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vlTOPp->vortex__DOT__vx_fetch__DOT__BR_reg = ((IData)(vlTOPp->reset)
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? 0U
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: 4U);
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// ALWAYS at VX_fetch.v:128
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vlTOPp->vortex__DOT__vx_fetch__DOT__real_PC = ((IData)(vlTOPp->reset)
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? 0U
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:
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((IData)(4U)
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+ vlTOPp->vortex__DOT__vx_fetch__DOT__PC_to_use));
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// ALWAYS at VX_fetch.v:128
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vlTOPp->vortex__DOT__vx_fetch__DOT__old = ((IData)(vlTOPp->reset)
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? 0U
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: vlTOPp->vortex__DOT__vx_fetch__DOT__PC_to_use);
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// ALWAYS at VX_fetch.v:128
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vlTOPp->vortex__DOT__vx_fetch__DOT__state = ((IData)(vlTOPp->reset)
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? 0U
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:
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((IData)(vlTOPp->vortex__DOT__vx_fetch__DOT__prev_debug)
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? 4U
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: 0U));
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// ALWAYS at VX_fetch.v:128
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vlTOPp->vortex__DOT__vx_fetch__DOT__prev_debug = 0U;
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// ALWAYS at VX_fetch.v:71
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vlTOPp->vortex__DOT__vx_fetch__DOT__PC_to_use =
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((IData)(vlTOPp->vortex__DOT__vx_fetch__DOT__delay_reg)
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? vlTOPp->vortex__DOT__vx_fetch__DOT__old
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: ((IData)(vlTOPp->vortex__DOT__vx_fetch__DOT__stall_reg)
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? vlTOPp->vortex__DOT__vx_fetch__DOT__old
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: ((0x10U & (IData)(vlTOPp->vortex__DOT__vx_fetch__DOT__state))
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? 0U : ((8U & (IData)(vlTOPp->vortex__DOT__vx_fetch__DOT__state))
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? 0U : ((4U & (IData)(vlTOPp->vortex__DOT__vx_fetch__DOT__state))
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? ((2U & (IData)(vlTOPp->vortex__DOT__vx_fetch__DOT__state))
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? 0U : ((1U
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& (IData)(vlTOPp->vortex__DOT__vx_fetch__DOT__state))
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? 0U
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: vlTOPp->vortex__DOT__vx_fetch__DOT__old))
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: ((2U & (IData)(vlTOPp->vortex__DOT__vx_fetch__DOT__state))
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? ((1U & (IData)(vlTOPp->vortex__DOT__vx_fetch__DOT__state))
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? vlTOPp->vortex__DOT__vx_fetch__DOT__real_PC
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: vlTOPp->vortex__DOT__vx_fetch__DOT__BR_reg)
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: ((1U & (IData)(vlTOPp->vortex__DOT__vx_fetch__DOT__state))
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? vlTOPp->vortex__DOT__vx_fetch__DOT__JAL_reg
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: vlTOPp->vortex__DOT__vx_fetch__DOT__real_PC)))))));
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vlTOPp->curr_PC = vlTOPp->vortex__DOT__vx_fetch__DOT__PC_to_use;
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}
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VL_INLINE_OPT void Vvortex::_sequent__TOP__3(Vvortex__Syms* __restrict vlSymsp) {
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VL_DEBUG_IF(VL_DBG_MSGF("+ Vvortex::_sequent__TOP__3\n"); );
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Vvortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
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// Body
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// ALWAYS at VX_f_d_reg.v:17
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VL_WRITEF("Fetch Inst: %10#\tDecode Inst: %10#\n",
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32,vlTOPp->fe_instruction,32,vlTOPp->vortex__DOT__vx_f_d_reg__DOT__instruction);
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}
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void Vvortex::_initial__TOP__4(Vvortex__Syms* __restrict vlSymsp) {
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VL_DEBUG_IF(VL_DBG_MSGF("+ Vvortex::_initial__TOP__4\n"); );
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Vvortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
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// Body
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// INITIAL at VX_fetch.v:44
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vlTOPp->vortex__DOT__vx_fetch__DOT__stall_reg = 0U;
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vlTOPp->vortex__DOT__vx_fetch__DOT__delay_reg = 0U;
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vlTOPp->vortex__DOT__vx_fetch__DOT__old = 0U;
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vlTOPp->vortex__DOT__vx_fetch__DOT__state = 0U;
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vlTOPp->vortex__DOT__vx_fetch__DOT__real_PC = 0U;
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vlTOPp->vortex__DOT__vx_fetch__DOT__JAL_reg = 0U;
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vlTOPp->vortex__DOT__vx_fetch__DOT__BR_reg = 0U;
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vlTOPp->vortex__DOT__vx_fetch__DOT__prev_debug = 0U;
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}
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VL_INLINE_OPT void Vvortex::_sequent__TOP__5(Vvortex__Syms* __restrict vlSymsp) {
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VL_DEBUG_IF(VL_DBG_MSGF("+ Vvortex::_sequent__TOP__5\n"); );
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Vvortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
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// Body
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// ALWAYS at VX_f_d_reg.v:26
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vlTOPp->vortex__DOT__vx_f_d_reg__DOT__instruction
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= ((IData)(vlTOPp->reset) ? 0U : vlTOPp->fe_instruction);
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vlTOPp->de_instruction = vlTOPp->vortex__DOT__vx_f_d_reg__DOT__instruction;
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}
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void Vvortex::_settle__TOP__6(Vvortex__Syms* __restrict vlSymsp) {
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VL_DEBUG_IF(VL_DBG_MSGF("+ Vvortex::_settle__TOP__6\n"); );
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Vvortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
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// Body
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// ALWAYS at VX_fetch.v:71
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vlTOPp->vortex__DOT__vx_fetch__DOT__PC_to_use =
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((IData)(vlTOPp->vortex__DOT__vx_fetch__DOT__delay_reg)
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? vlTOPp->vortex__DOT__vx_fetch__DOT__old
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: ((IData)(vlTOPp->vortex__DOT__vx_fetch__DOT__stall_reg)
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? vlTOPp->vortex__DOT__vx_fetch__DOT__old
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: ((0x10U & (IData)(vlTOPp->vortex__DOT__vx_fetch__DOT__state))
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? 0U : ((8U & (IData)(vlTOPp->vortex__DOT__vx_fetch__DOT__state))
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? 0U : ((4U & (IData)(vlTOPp->vortex__DOT__vx_fetch__DOT__state))
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? ((2U & (IData)(vlTOPp->vortex__DOT__vx_fetch__DOT__state))
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? 0U : ((1U
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& (IData)(vlTOPp->vortex__DOT__vx_fetch__DOT__state))
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? 0U
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: vlTOPp->vortex__DOT__vx_fetch__DOT__old))
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: ((2U & (IData)(vlTOPp->vortex__DOT__vx_fetch__DOT__state))
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? ((1U & (IData)(vlTOPp->vortex__DOT__vx_fetch__DOT__state))
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? vlTOPp->vortex__DOT__vx_fetch__DOT__real_PC
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: vlTOPp->vortex__DOT__vx_fetch__DOT__BR_reg)
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: ((1U & (IData)(vlTOPp->vortex__DOT__vx_fetch__DOT__state))
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? vlTOPp->vortex__DOT__vx_fetch__DOT__JAL_reg
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: vlTOPp->vortex__DOT__vx_fetch__DOT__real_PC)))))));
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vlTOPp->curr_PC = vlTOPp->vortex__DOT__vx_fetch__DOT__PC_to_use;
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}
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void Vvortex::_eval(Vvortex__Syms* __restrict vlSymsp) {
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VL_DEBUG_IF(VL_DBG_MSGF("+ Vvortex::_eval\n"); );
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Vvortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
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// Body
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if ((((IData)(vlTOPp->clk) & (~ (IData)(vlTOPp->__Vclklast__TOP__clk)))
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| ((IData)(vlTOPp->reset) & (~ (IData)(vlTOPp->__Vclklast__TOP__reset))))) {
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vlTOPp->_sequent__TOP__2(vlSymsp);
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}
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if (((IData)(vlTOPp->clk) & (~ (IData)(vlTOPp->__Vclklast__TOP__clk)))) {
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vlTOPp->_sequent__TOP__3(vlSymsp);
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}
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if ((((IData)(vlTOPp->clk) & (~ (IData)(vlTOPp->__Vclklast__TOP__clk)))
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| ((IData)(vlTOPp->reset) & (~ (IData)(vlTOPp->__Vclklast__TOP__reset))))) {
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vlTOPp->_sequent__TOP__5(vlSymsp);
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}
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// Final
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vlTOPp->__Vclklast__TOP__clk = vlTOPp->clk;
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vlTOPp->__Vclklast__TOP__reset = vlTOPp->reset;
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}
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void Vvortex::_eval_initial(Vvortex__Syms* __restrict vlSymsp) {
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VL_DEBUG_IF(VL_DBG_MSGF("+ Vvortex::_eval_initial\n"); );
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Vvortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
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// Body
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vlTOPp->__Vclklast__TOP__clk = vlTOPp->clk;
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vlTOPp->__Vclklast__TOP__reset = vlTOPp->reset;
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vlTOPp->_initial__TOP__4(vlSymsp);
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}
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void Vvortex::final() {
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VL_DEBUG_IF(VL_DBG_MSGF("+ Vvortex::final\n"); );
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// Variables
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Vvortex__Syms* __restrict vlSymsp = this->__VlSymsp;
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Vvortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
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}
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void Vvortex::_eval_settle(Vvortex__Syms* __restrict vlSymsp) {
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VL_DEBUG_IF(VL_DBG_MSGF("+ Vvortex::_eval_settle\n"); );
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Vvortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
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// Body
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vlTOPp->_settle__TOP__1(vlSymsp);
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vlTOPp->_settle__TOP__6(vlSymsp);
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}
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VL_INLINE_OPT QData Vvortex::_change_request(Vvortex__Syms* __restrict vlSymsp) {
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VL_DEBUG_IF(VL_DBG_MSGF("+ Vvortex::_change_request\n"); );
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Vvortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
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// Body
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// Change detection
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QData __req = false; // Logically a bool
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return __req;
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}
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#ifdef VL_DEBUG
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void Vvortex::_eval_debug_assertions() {
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VL_DEBUG_IF(VL_DBG_MSGF("+ Vvortex::_eval_debug_assertions\n"); );
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// Body
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if (VL_UNLIKELY((clk & 0xfeU))) {
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Verilated::overWidthError("clk");}
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if (VL_UNLIKELY((reset & 0xfeU))) {
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Verilated::overWidthError("reset");}
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}
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#endif // VL_DEBUG
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void Vvortex::_ctor_var_reset() {
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VL_DEBUG_IF(VL_DBG_MSGF("+ Vvortex::_ctor_var_reset\n"); );
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// Body
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clk = VL_RAND_RESET_I(1);
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reset = VL_RAND_RESET_I(1);
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fe_instruction = VL_RAND_RESET_I(32);
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curr_PC = VL_RAND_RESET_I(32);
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de_instruction = VL_RAND_RESET_I(32);
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fe_delay = VL_RAND_RESET_I(1);
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vortex__DOT__vx_fetch__DOT__stall_reg = VL_RAND_RESET_I(1);
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vortex__DOT__vx_fetch__DOT__delay_reg = VL_RAND_RESET_I(1);
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vortex__DOT__vx_fetch__DOT__old = VL_RAND_RESET_I(32);
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vortex__DOT__vx_fetch__DOT__state = VL_RAND_RESET_I(5);
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vortex__DOT__vx_fetch__DOT__real_PC = VL_RAND_RESET_I(32);
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vortex__DOT__vx_fetch__DOT__JAL_reg = VL_RAND_RESET_I(32);
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vortex__DOT__vx_fetch__DOT__BR_reg = VL_RAND_RESET_I(32);
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vortex__DOT__vx_fetch__DOT__prev_debug = VL_RAND_RESET_I(1);
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vortex__DOT__vx_fetch__DOT__PC_to_use = VL_RAND_RESET_I(32);
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vortex__DOT__vx_f_d_reg__DOT__instruction = VL_RAND_RESET_I(32);
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}
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