From d1892bd6ec9c86402e79d079841d05817bda5915 Mon Sep 17 00:00:00 2001 From: Santosh Raghav Srivatsan Date: Thu, 11 Nov 2021 13:35:14 -0500 Subject: [PATCH] Added support for a few RV64I instructions --- runtime/Makefile | 13 ++++---- sim/simX/core.cpp | 2 ++ sim/simX/core.h | 5 ++-- sim/simX/decode.cpp | 20 +++++++++++++ sim/simX/execute.cpp | 68 ++++++++++++++++++++++++++++++++++++++++++ sim/simX/instr.h | 4 +++ sim/simX/types.h | 3 +- sim/simX/warp.cpp | 6 ++-- sim/simX/warp.h | 2 +- tests/runtime/Makefile | 4 +-- 10 files changed, 114 insertions(+), 13 deletions(-) diff --git a/runtime/Makefile b/runtime/Makefile index 60c3b398..e9d08b20 100644 --- a/runtime/Makefile +++ b/runtime/Makefile @@ -1,11 +1,14 @@ RISCV_TOOLCHAIN_PATH ?= /opt/riscv-gnu-toolchain +# simx64 +RISCV64_TOOLCHAIN_PATH ?= /nethome/ssrivatsan8/riscv64-unknown-elf-toolchain -CC = $(RISCV_TOOLCHAIN_PATH)/bin/riscv32-unknown-elf-gcc -AR = $(RISCV_TOOLCHAIN_PATH)/bin/riscv32-unknown-elf-gcc-ar -DP = $(RISCV_TOOLCHAIN_PATH)/bin/riscv32-unknown-elf-objdump -CP = $(RISCV_TOOLCHAIN_PATH)/bin/riscv32-unknown-elf-objcopy -CFLAGS += -O3 -march=rv32imf -mabi=ilp32f -Wstack-usage=1024 -fno-exceptions -fdata-sections -ffunction-sections +CC = $(RISCV64_TOOLCHAIN_PATH)/bin/riscv64-unknown-elf-gcc +AR = $(RISCV64_TOOLCHAIN_PATH)/bin/riscv64-unknown-elf-gcc-ar +DP = $(RISCV64_TOOLCHAIN_PATH)/bin/riscv64-unknown-elf-objdump +CP = $(RISCV64_TOOLCHAIN_PATH)/bin/riscv64-unknown-elf-objcopy + +CFLAGS += -O3 -march=rv64imfd -mabi=lp64d -Wstack-usage=1024 -fno-exceptions -fdata-sections -ffunction-sections CFLAGS += -I./include -I../hw PROJECT = libvortexrt diff --git a/sim/simX/core.cpp b/sim/simX/core.cpp index c68ac854..d5c8f1b9 100644 --- a/sim/simX/core.cpp +++ b/sim/simX/core.cpp @@ -321,12 +321,14 @@ void Core::barrier(int bar_id, int count, int warp_id) { barrier.reset(); } +// simx64 Word Core::icache_fetch(Addr addr) { Word data; mem_.read(&data, addr, sizeof(Word), 0); return data; } +// simx64 Word Core::dcache_read(Addr addr, Size size) { ++loads_; Word data = 0; diff --git a/sim/simX/core.h b/sim/simX/core.h index 29de3ec6..84e4a60f 100644 --- a/sim/simX/core.h +++ b/sim/simX/core.h @@ -66,10 +66,11 @@ public: void barrier(int bar_id, int count, int warp_id); + // simx64 Word icache_fetch(Addr); - + // simx64 Word dcache_read(Addr, Size); - + // simx64 void dcache_write(Addr, Word, Size); void trigger_ebreak(); diff --git a/sim/simX/decode.cpp b/sim/simX/decode.cpp index dbc7115a..76f02456 100644 --- a/sim/simX/decode.cpp +++ b/sim/simX/decode.cpp @@ -41,6 +41,8 @@ static const std::unordered_map sc_instTable = { {Opcode::FMNMSUB, {false, InstType::R4_TYPE}}, {Opcode::VSET, {false, InstType::V_TYPE}}, {Opcode::GPGPU, {false, InstType::R_TYPE}}, + {Opcode::R_INST_64, {false, InstType::R_TYPE}}, + {Opcode::I_INST_64, {false, InstType::I_TYPE}}, }; static const char* op_string(const Instr &instr) { @@ -118,6 +120,24 @@ static const char* op_string(const Instr &instr) { default: std::abort(); } + // simx64 + case Opcode::R_INST_64: + switch (func3) { + case 0: return func7 ? "SUBW" : "ADDW"; + case 1: return "SLLW"; + case 5: return func7 ? "SRAW" : "SRLW"; + default: + std::abort(); + } + // simx64 + case Opcode::I_INST_64: + switch (func3) { + case 0: return "ADDIW"; + case 1: return "SLLIW"; + case 5: return func7 ? "SRAIW" : "SRLIW"; + default: + std::abort(); + } case Opcode::SYS_INST: switch (func3) { case 0: return imm ? "EBREAK" : "ECALL"; diff --git a/sim/simX/execute.cpp b/sim/simX/execute.cpp index 7b5ecc5b..4f297b32 100644 --- a/sim/simX/execute.cpp +++ b/sim/simX/execute.cpp @@ -205,6 +205,9 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) { } break; case 1: + // simx64 + // In RV64I, only the low 6 bits of rs2 are considered for the shift amount. + // In RV32I, the value in register rs1 is shifted by the amount held in the lower 5 bits of register rs2. rddata = rsdata[0] << rsdata[1]; break; case 2: @@ -388,6 +391,71 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) { std::abort(); } } break; + // simx64 + case R_INST_64: { + switch (func3) { + case 0: + if (func7){ + // SUBW + rddata = DoubleWord(rsdata[0] - rsdata[1]); + } + else{ + // ADDW + rddata = DoubleWord(rsdata[0] + rsdata[1]); + } + break; + case 1: + // SLLW + // shift amount given by rs2[4:0] + rddata = DoubleWord(rsdata[0] << rsdata[1]); + break; + case 5: + if (func7) { + // SRAW + // shift amount given by rs2[4:0] + rddata = DoubleWord(WordI(rsdata[0]) >> WordI(rsdata[1])); + } else { + // SRLW + // shift amount given by rs2[4:0] + rddata = DoubleWord(Word(rsdata[0]) >> Word(rsdata[1])); + } + break; + default: + std::abort(); + } + } break; + // simx64 + case I_INST_64: { + switch (func3) { + case 0: + // ADDIW + rddata = DoubleWord(rsdata[0] + immsrc); + break; + case 1: + // SLLIW + // rs1 shifted by lower 5 bits of imm + // Illegal exception if imm[5] != 0 + rddata = DoubleWord(rsdata[0] << immsrc); + break; + case 5: + if (func7) { + // SRAI + // rs1 shifted by lower 5 bits of imm + // Illegal exception if imm[5] != 0 + Word result = DoubleWord(WordI(rsdata[0]) >> immsrc); + rddata = result; + } else { + // SRLI + // rs1 shifted by lower 5 bits of imm + // Illegal exception if imm[5] != 0 + Word result = DoubleWord(Word(rsdata[0]) >> immsrc); + rddata = result; + } + break; + default: + std::abort(); + } + } break; case SYS_INST: { Word csr_addr = immsrc & 0x00000FFF; Word csr_value = core_->get_csr(csr_addr, t, id_); diff --git a/sim/simX/instr.h b/sim/simX/instr.h index a93dd61b..167082fd 100644 --- a/sim/simX/instr.h +++ b/sim/simX/instr.h @@ -33,6 +33,10 @@ enum Opcode { VS = 0x27, // GPGPU Extension GPGPU = 0x6b, + // simx64 + // RV64I Extension + R_INST_64 = 0x3b, + I_INST_64 = 0x1b, }; enum InstType { diff --git a/sim/simX/types.h b/sim/simX/types.h index f5b9dd0f..c9bf18fb 100644 --- a/sim/simX/types.h +++ b/sim/simX/types.h @@ -12,7 +12,8 @@ typedef int32_t WordI; // simx64 typedef uint64_t DoubleWord; -typedef uint32_t Addr; +// simx64 +typedef uint64_t Addr; typedef uint32_t Size; typedef std::bitset<32> RegMask; diff --git a/sim/simX/warp.cpp b/sim/simX/warp.cpp index e3e47d97..b5f9c203 100644 --- a/sim/simX/warp.cpp +++ b/sim/simX/warp.cpp @@ -13,8 +13,9 @@ using namespace vortex; Warp::Warp(Core *core, Word id) : id_(id) , core_(core) { + // simx64 iRegFile_.resize(core_->arch().num_threads(), std::vector(core_->arch().num_regs(), 0)); - fRegFile_.resize(core_->arch().num_threads(), std::vector(core_->arch().num_regs(), 0)); + fRegFile_.resize(core_->arch().num_threads(), std::vector(core_->arch().num_regs(), 0)); vRegFile_.resize(core_->arch().num_regs(), std::vector(core_->arch().vsize(), 0)); this->clear(); } @@ -86,7 +87,8 @@ void Warp::step(Pipeline *pipeline) { for (int i = 0; i < core_->arch().num_regs(); ++i) { DPN(4, " %r" << std::setfill('0') << std::setw(2) << std::dec << i << ':'); for (int j = 0; j < core_->arch().num_threads(); ++j) { - DPN(4, ' ' << std::setfill('0') << std::setw(8) << std::hex << iRegFile_[j][i] << std::setfill(' ') << ' '); + // simx64 + DPN(4, ' ' << std::setfill('0') << std::setw(16) << std::hex << iRegFile_[j][i] << std::setfill(' ') << ' '); } DPN(4, std::endl); } diff --git a/sim/simX/warp.h b/sim/simX/warp.h index 757da048..f2a33d90 100644 --- a/sim/simX/warp.h +++ b/sim/simX/warp.h @@ -100,7 +100,7 @@ private: // simx64 std::vector> iRegFile_; - std::vector> fRegFile_; + std::vector> fRegFile_; std::vector> vRegFile_; std::stack domStack_; diff --git a/tests/runtime/Makefile b/tests/runtime/Makefile index f420f31c..a6869135 100644 --- a/tests/runtime/Makefile +++ b/tests/runtime/Makefile @@ -11,10 +11,10 @@ run-simx: run-rtlsim: $(MAKE) -C hello run-rtlsim $(MAKE) -C fibonacci run-rtlsim - $(MAKE) -C simple run-rtlsim + $(MAKE) -C simple run-rtlsim clean: $(MAKE) -C hello clean $(MAKE) -C fibonacci clean - $(MAKE) -C simple clean + $(MAKE) -C simple clean