From d3b788784a5e9bff1a59df92fb8b171418cc7dab Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Tue, 20 Jul 2021 21:06:55 -0700 Subject: [PATCH] memory interface refactoring --- hw/rtl/VX_core.v | 76 ++++++------ hw/rtl/VX_execute.v | 4 +- hw/rtl/VX_fetch.v | 4 +- hw/rtl/VX_icache_stage.v | 12 +- hw/rtl/VX_lsu_unit.v | 4 +- hw/rtl/VX_mem_unit.v | 108 +++++++++--------- hw/rtl/VX_pipeline.v | 64 +++++------ hw/rtl/VX_smem_arb.v | 16 +-- ...cache_core_req_if.v => VX_dcache_req_if.v} | 0 ...cache_core_rsp_if.v => VX_dcache_rsp_if.v} | 0 ...cache_core_req_if.v => VX_icache_req_if.v} | 0 ...cache_core_rsp_if.v => VX_icache_rsp_if.v} | 0 ...{VX_cache_mem_req_if.v => VX_mem_req_if.v} | 0 ...{VX_cache_mem_rsp_if.v => VX_mem_rsp_if.v} | 0 14 files changed, 144 insertions(+), 144 deletions(-) rename hw/rtl/interfaces/{VX_dcache_core_req_if.v => VX_dcache_req_if.v} (100%) rename hw/rtl/interfaces/{VX_dcache_core_rsp_if.v => VX_dcache_rsp_if.v} (100%) rename hw/rtl/interfaces/{VX_icache_core_req_if.v => VX_icache_req_if.v} (100%) rename hw/rtl/interfaces/{VX_icache_core_rsp_if.v => VX_icache_rsp_if.v} (100%) rename hw/rtl/interfaces/{VX_cache_mem_req_if.v => VX_mem_req_if.v} (100%) rename hw/rtl/interfaces/{VX_cache_mem_rsp_if.v => VX_mem_rsp_if.v} (100%) diff --git a/hw/rtl/VX_core.v b/hw/rtl/VX_core.v index 380f89d4..19d16cf7 100644 --- a/hw/rtl/VX_core.v +++ b/hw/rtl/VX_core.v @@ -31,13 +31,13 @@ module VX_core #( VX_perf_memsys_if perf_memsys_if(); `endif - VX_cache_mem_req_if #( + VX_mem_req_if #( .MEM_LINE_WIDTH(`DMEM_LINE_WIDTH), .MEM_ADDR_WIDTH(`DMEM_ADDR_WIDTH), .MEM_TAG_WIDTH(`XMEM_TAG_WIDTH) ) mem_req_if(); - VX_cache_mem_rsp_if #( + VX_mem_rsp_if #( .MEM_LINE_WIDTH(`DMEM_LINE_WIDTH), .MEM_TAG_WIDTH(`XMEM_TAG_WIDTH) ) mem_rsp_if(); @@ -57,27 +57,27 @@ module VX_core #( //-- - VX_dcache_core_req_if #( + VX_dcache_req_if #( .NUM_REQS(`DNUM_REQS), .WORD_SIZE(`DWORD_SIZE), .CORE_TAG_WIDTH(`DCORE_TAG_WIDTH) - ) dcache_core_req_if(); + ) dcache_req_if(); - VX_dcache_core_rsp_if #( + VX_dcache_rsp_if #( .NUM_REQS(`DNUM_REQS), .WORD_SIZE(`DWORD_SIZE), .CORE_TAG_WIDTH(`DCORE_TAG_WIDTH) - ) dcache_core_rsp_if(); + ) dcache_rsp_if(); - VX_icache_core_req_if #( + VX_icache_req_if #( .WORD_SIZE(`IWORD_SIZE), .CORE_TAG_WIDTH(`ICORE_TAG_WIDTH) - ) icache_core_req_if(); + ) icache_req_if(); - VX_icache_core_rsp_if #( + VX_icache_rsp_if #( .WORD_SIZE(`IWORD_SIZE), .CORE_TAG_WIDTH(`ICORE_TAG_WIDTH) - ) icache_core_rsp_if(); + ) icache_rsp_if(); VX_pipeline #( .CORE_ID(CORE_ID) @@ -91,32 +91,32 @@ module VX_core #( .reset(reset), // Dcache core request - .dcache_req_valid (dcache_core_req_if.valid), - .dcache_req_rw (dcache_core_req_if.rw), - .dcache_req_byteen (dcache_core_req_if.byteen), - .dcache_req_addr (dcache_core_req_if.addr), - .dcache_req_data (dcache_core_req_if.data), - .dcache_req_tag (dcache_core_req_if.tag), - .dcache_req_ready (dcache_core_req_if.ready), + .dcache_req_valid (dcache_req_if.valid), + .dcache_req_rw (dcache_req_if.rw), + .dcache_req_byteen (dcache_req_if.byteen), + .dcache_req_addr (dcache_req_if.addr), + .dcache_req_data (dcache_req_if.data), + .dcache_req_tag (dcache_req_if.tag), + .dcache_req_ready (dcache_req_if.ready), // Dcache core reponse - .dcache_rsp_valid (dcache_core_rsp_if.valid), - .dcache_rsp_tmask (dcache_core_rsp_if.tmask), - .dcache_rsp_data (dcache_core_rsp_if.data), - .dcache_rsp_tag (dcache_core_rsp_if.tag), - .dcache_rsp_ready (dcache_core_rsp_if.ready), + .dcache_rsp_valid (dcache_rsp_if.valid), + .dcache_rsp_tmask (dcache_rsp_if.tmask), + .dcache_rsp_data (dcache_rsp_if.data), + .dcache_rsp_tag (dcache_rsp_if.tag), + .dcache_rsp_ready (dcache_rsp_if.ready), // Icache core request - .icache_req_valid (icache_core_req_if.valid), - .icache_req_addr (icache_core_req_if.addr), - .icache_req_tag (icache_core_req_if.tag), - .icache_req_ready (icache_core_req_if.ready), + .icache_req_valid (icache_req_if.valid), + .icache_req_addr (icache_req_if.addr), + .icache_req_tag (icache_req_if.tag), + .icache_req_ready (icache_req_if.ready), // Icache core reponse - .icache_rsp_valid (icache_core_rsp_if.valid), - .icache_rsp_data (icache_core_rsp_if.data), - .icache_rsp_tag (icache_core_rsp_if.tag), - .icache_rsp_ready (icache_core_rsp_if.ready), + .icache_rsp_valid (icache_rsp_if.valid), + .icache_rsp_data (icache_rsp_if.data), + .icache_rsp_tag (icache_rsp_if.tag), + .icache_rsp_ready (icache_rsp_if.ready), // Status .busy(busy) @@ -132,20 +132,20 @@ module VX_core #( .perf_memsys_if (perf_memsys_if), `endif - .clk (clk), - .reset (reset), + .clk (clk), + .reset (reset), // Core <-> Dcache - .dcache_core_req_if (dcache_core_req_if), - .dcache_core_rsp_if (dcache_core_rsp_if), + .dcache_req_if (dcache_req_if), + .dcache_rsp_if (dcache_rsp_if), // Core <-> Icache - .icache_core_req_if (icache_core_req_if), - .icache_core_rsp_if (icache_core_rsp_if), + .icache_req_if (icache_req_if), + .icache_rsp_if (icache_rsp_if), // Memory - .mem_req_if (mem_req_if), - .mem_rsp_if (mem_rsp_if) + .mem_req_if (mem_req_if), + .mem_rsp_if (mem_rsp_if) ); endmodule diff --git a/hw/rtl/VX_execute.v b/hw/rtl/VX_execute.v index c671190a..dbddc1fd 100644 --- a/hw/rtl/VX_execute.v +++ b/hw/rtl/VX_execute.v @@ -9,8 +9,8 @@ module VX_execute #( input wire reset, // Dcache interface - VX_dcache_core_req_if dcache_req_if, - VX_dcache_core_rsp_if dcache_rsp_if, + VX_dcache_req_if dcache_req_if, + VX_dcache_rsp_if dcache_rsp_if, // commit status VX_cmt_to_csr_if cmt_to_csr_if, diff --git a/hw/rtl/VX_fetch.v b/hw/rtl/VX_fetch.v index 34741637..5760beea 100644 --- a/hw/rtl/VX_fetch.v +++ b/hw/rtl/VX_fetch.v @@ -9,8 +9,8 @@ module VX_fetch #( input wire reset, // Icache interface - VX_icache_core_req_if icache_req_if, - VX_icache_core_rsp_if icache_rsp_if, + VX_icache_req_if icache_req_if, + VX_icache_rsp_if icache_rsp_if, // inputs VX_wstall_if wstall_if, diff --git a/hw/rtl/VX_icache_stage.v b/hw/rtl/VX_icache_stage.v index 881528e3..4e099d51 100644 --- a/hw/rtl/VX_icache_stage.v +++ b/hw/rtl/VX_icache_stage.v @@ -5,18 +5,18 @@ module VX_icache_stage #( ) ( `SCOPE_IO_VX_icache_stage - input wire clk, - input wire reset, + input wire clk, + input wire reset, // Icache interface - VX_icache_core_req_if icache_req_if, - VX_icache_core_rsp_if icache_rsp_if, + VX_icache_req_if icache_req_if, + VX_icache_rsp_if icache_rsp_if, // request - VX_ifetch_req_if ifetch_req_if, + VX_ifetch_req_if ifetch_req_if, // reponse - VX_ifetch_rsp_if ifetch_rsp_if + VX_ifetch_rsp_if ifetch_rsp_if ); `UNUSED_PARAM (CORE_ID) diff --git a/hw/rtl/VX_lsu_unit.v b/hw/rtl/VX_lsu_unit.v index fa5f994c..c13d0c0a 100644 --- a/hw/rtl/VX_lsu_unit.v +++ b/hw/rtl/VX_lsu_unit.v @@ -9,8 +9,8 @@ module VX_lsu_unit #( input wire reset, // Dcache interface - VX_dcache_core_req_if dcache_req_if, - VX_dcache_core_rsp_if dcache_rsp_if, + VX_dcache_req_if dcache_req_if, + VX_dcache_rsp_if dcache_rsp_if, // inputs VX_lsu_req_if lsu_req_if, diff --git a/hw/rtl/VX_mem_unit.v b/hw/rtl/VX_mem_unit.v index 54b6505f..c034f45d 100644 --- a/hw/rtl/VX_mem_unit.v +++ b/hw/rtl/VX_mem_unit.v @@ -5,63 +5,63 @@ module VX_mem_unit # ( ) ( `SCOPE_IO_VX_mem_unit - input wire clk, - input wire reset, + input wire clk, + input wire reset, `ifdef PERF_ENABLE - VX_perf_memsys_if perf_memsys_if, + VX_perf_memsys_if perf_memsys_if, `endif // Core <-> Dcache - VX_dcache_core_req_if dcache_core_req_if, - VX_dcache_core_rsp_if dcache_core_rsp_if, + VX_dcache_req_if dcache_req_if, + VX_dcache_rsp_if dcache_rsp_if, // Core <-> Icache - VX_icache_core_req_if icache_core_req_if, - VX_icache_core_rsp_if icache_core_rsp_if, + VX_icache_req_if icache_req_if, + VX_icache_rsp_if icache_rsp_if, // Memory - VX_cache_mem_req_if mem_req_if, - VX_cache_mem_rsp_if mem_rsp_if + VX_mem_req_if mem_req_if, + VX_mem_rsp_if mem_rsp_if ); `ifdef PERF_ENABLE VX_perf_cache_if perf_icache_if(), perf_dcache_if(), perf_smem_if(); `endif - VX_cache_mem_req_if #( + VX_mem_req_if #( .MEM_LINE_WIDTH (`IMEM_LINE_WIDTH), .MEM_ADDR_WIDTH (`IMEM_ADDR_WIDTH), .MEM_TAG_WIDTH (`IMEM_TAG_WIDTH) ) icache_mem_req_if(); - VX_cache_mem_rsp_if #( + VX_mem_rsp_if #( .MEM_LINE_WIDTH (`IMEM_LINE_WIDTH), .MEM_TAG_WIDTH (`IMEM_TAG_WIDTH) ) icache_mem_rsp_if(); - VX_cache_mem_req_if #( + VX_mem_req_if #( .MEM_LINE_WIDTH (`DMEM_LINE_WIDTH), .MEM_ADDR_WIDTH (`DMEM_ADDR_WIDTH), .MEM_TAG_WIDTH (`DMEM_TAG_WIDTH) ) dcache_mem_req_if(); - VX_cache_mem_rsp_if #( + VX_mem_rsp_if #( .MEM_LINE_WIDTH (`DMEM_LINE_WIDTH), .MEM_TAG_WIDTH (`DMEM_TAG_WIDTH) ) dcache_mem_rsp_if(); - VX_dcache_core_req_if #( + VX_dcache_req_if #( .NUM_REQS (`DNUM_REQS), .WORD_SIZE (`DWORD_SIZE), .CORE_TAG_WIDTH (`DCORE_TAG_WIDTH-`SM_ENABLE) - ) dcache_req_if(); + ) dcache_req_tmp_if(); - VX_dcache_core_rsp_if #( + VX_dcache_rsp_if #( .NUM_REQS (`DNUM_REQS), .WORD_SIZE (`DWORD_SIZE), .CORE_TAG_WIDTH (`DCORE_TAG_WIDTH-`SM_ENABLE) - ) dcache_rsp_if(); + ) dcache_rsp_tmp_if(); `RESET_RELAY (icache_reset); `RESET_RELAY (dcache_reset); @@ -89,19 +89,19 @@ module VX_mem_unit # ( .reset (icache_reset), // Core request - .core_req_valid (icache_core_req_if.valid), + .core_req_valid (icache_req_if.valid), .core_req_rw (1'b0), .core_req_byteen ({`IWORD_SIZE{1'b1}}), - .core_req_addr (icache_core_req_if.addr), + .core_req_addr (icache_req_if.addr), .core_req_data ('x), - .core_req_tag (icache_core_req_if.tag), - .core_req_ready (icache_core_req_if.ready), + .core_req_tag (icache_req_if.tag), + .core_req_ready (icache_req_if.ready), // Core response - .core_rsp_valid (icache_core_rsp_if.valid), - .core_rsp_data (icache_core_rsp_if.data), - .core_rsp_tag (icache_core_rsp_if.tag), - .core_rsp_ready (icache_core_rsp_if.ready), + .core_rsp_valid (icache_rsp_if.valid), + .core_rsp_data (icache_rsp_if.data), + .core_rsp_tag (icache_rsp_if.tag), + .core_rsp_ready (icache_rsp_if.ready), `UNUSED_PIN (core_rsp_tmask), `ifdef PERF_ENABLE @@ -149,20 +149,20 @@ module VX_mem_unit # ( .reset (dcache_reset), // Core req - .core_req_valid (dcache_req_if.valid), - .core_req_rw (dcache_req_if.rw), - .core_req_byteen (dcache_req_if.byteen), - .core_req_addr (dcache_req_if.addr), - .core_req_data (dcache_req_if.data), - .core_req_tag (dcache_req_if.tag), - .core_req_ready (dcache_req_if.ready), + .core_req_valid (dcache_req_tmp_if.valid), + .core_req_rw (dcache_req_tmp_if.rw), + .core_req_byteen (dcache_req_tmp_if.byteen), + .core_req_addr (dcache_req_tmp_if.addr), + .core_req_data (dcache_req_tmp_if.data), + .core_req_tag (dcache_req_tmp_if.tag), + .core_req_ready (dcache_req_tmp_if.ready), // Core response - .core_rsp_valid (dcache_rsp_if.valid), - .core_rsp_tmask (dcache_rsp_if.tmask), - .core_rsp_data (dcache_rsp_if.data), - .core_rsp_tag (dcache_rsp_if.tag), - .core_rsp_ready (dcache_rsp_if.ready), + .core_rsp_valid (dcache_rsp_tmp_if.valid), + .core_rsp_tmask (dcache_rsp_tmp_if.tmask), + .core_rsp_data (dcache_rsp_tmp_if.data), + .core_rsp_tag (dcache_rsp_tmp_if.tag), + .core_rsp_ready (dcache_rsp_tmp_if.ready), `ifdef PERF_ENABLE .perf_cache_if (perf_dcache_if), @@ -185,13 +185,13 @@ module VX_mem_unit # ( ); if (`SM_ENABLE) begin - VX_dcache_core_req_if #( + VX_dcache_req_if #( .NUM_REQS (`DNUM_REQS), .WORD_SIZE (`DWORD_SIZE), .CORE_TAG_WIDTH (`DCORE_TAG_WIDTH-`SM_ENABLE) ) smem_req_if(); - VX_dcache_core_rsp_if #( + VX_dcache_rsp_if #( .NUM_REQS (`DNUM_REQS), .WORD_SIZE (`DWORD_SIZE), .CORE_TAG_WIDTH (`DCORE_TAG_WIDTH-`SM_ENABLE) @@ -201,13 +201,13 @@ module VX_mem_unit # ( .clk (clk), .reset (reset), - .core_req_if (dcache_core_req_if), - .cache_req_if (dcache_req_if), + .core_req_if (dcache_req_if), + .cache_req_if (dcache_req_tmp_if), .smem_req_if (smem_req_if), - .cache_rsp_if (dcache_rsp_if), + .cache_rsp_if (dcache_rsp_tmp_if), .smem_rsp_if (smem_rsp_if), - .core_rsp_if (dcache_core_rsp_if) + .core_rsp_if (dcache_rsp_if) ); `RESET_RELAY (smem_reset); @@ -249,19 +249,19 @@ module VX_mem_unit # ( ); end else begin // core to D-cache request - assign dcache_req_if.valid = dcache_core_req_if.valid; - assign dcache_req_if.addr = dcache_core_req_if.addr; - assign dcache_req_if.rw = dcache_core_req_if.rw; - assign dcache_req_if.byteen = dcache_core_req_if.byteen; - assign dcache_req_if.data = dcache_core_req_if.data; - assign dcache_req_if.tag = dcache_core_req_if.tag; - assign dcache_core_req_if.ready = dcache_req_if.ready; + assign dcache_req_tmp_if.valid = dcache_req_if.valid; + assign dcache_req_tmp_if.addr = dcache_req_if.addr; + assign dcache_req_tmp_if.rw = dcache_req_if.rw; + assign dcache_req_tmp_if.byteen = dcache_req_if.byteen; + assign dcache_req_tmp_if.data = dcache_req_if.data; + assign dcache_req_tmp_if.tag = dcache_req_if.tag; + assign dcache_req_tmp_if.ready = dcache_req_if.ready; // D-cache to core reponse - assign dcache_core_rsp_if.valid = dcache_rsp_if.valid; - assign dcache_core_rsp_if.tag = dcache_rsp_if.tag; - assign dcache_core_rsp_if.data = dcache_rsp_if.data; - assign dcache_rsp_if.ready = dcache_core_rsp_if.ready; + assign dcache_rsp_if.valid = dcache_rsp_tmp_if.valid; + assign dcache_rsp_if.tag = dcache_rsp_tmp_if.tag; + assign dcache_rsp_if.data = dcache_rsp_tmp_if.data; + assign dcache_rsp_if.ready = dcache_rsp_tmp_if.ready; end wire [`DMEM_TAG_WIDTH-1:0] icache_mem_req_tag = `DMEM_TAG_WIDTH'(icache_mem_req_if.tag); diff --git a/hw/rtl/VX_pipeline.v b/hw/rtl/VX_pipeline.v index a303982f..66fd23d5 100644 --- a/hw/rtl/VX_pipeline.v +++ b/hw/rtl/VX_pipeline.v @@ -48,63 +48,63 @@ module VX_pipeline #( // Dcache request // - VX_dcache_core_req_if #( + VX_dcache_req_if #( .NUM_REQS(`NUM_THREADS), .WORD_SIZE(4), .CORE_TAG_WIDTH(`DCORE_TAG_WIDTH) - ) dcache_core_req_if(); + ) dcache_req_if(); - assign dcache_req_valid = dcache_core_req_if.valid; - assign dcache_req_rw = dcache_core_req_if.rw; - assign dcache_req_byteen = dcache_core_req_if.byteen; - assign dcache_req_addr = dcache_core_req_if.addr; - assign dcache_req_data = dcache_core_req_if.data; - assign dcache_req_tag = dcache_core_req_if.tag; - assign dcache_core_req_if.ready = dcache_req_ready; + assign dcache_req_valid = dcache_req_if.valid; + assign dcache_req_rw = dcache_req_if.rw; + assign dcache_req_byteen = dcache_req_if.byteen; + assign dcache_req_addr = dcache_req_if.addr; + assign dcache_req_data = dcache_req_if.data; + assign dcache_req_tag = dcache_req_if.tag; + assign dcache_req_if.ready = dcache_req_ready; // // Dcache response // - VX_dcache_core_rsp_if #( + VX_dcache_rsp_if #( .NUM_REQS(`NUM_THREADS), .WORD_SIZE(4), .CORE_TAG_WIDTH(`DCORE_TAG_WIDTH) - ) dcache_core_rsp_if(); + ) dcache_rsp_if(); - assign dcache_core_rsp_if.valid = dcache_rsp_valid; - assign dcache_core_rsp_if.tmask = dcache_rsp_tmask; - assign dcache_core_rsp_if.data = dcache_rsp_data; - assign dcache_core_rsp_if.tag = dcache_rsp_tag; - assign dcache_rsp_ready = dcache_core_rsp_if.ready; + assign dcache_rsp_if.valid = dcache_rsp_valid; + assign dcache_rsp_if.tmask = dcache_rsp_tmask; + assign dcache_rsp_if.data = dcache_rsp_data; + assign dcache_rsp_if.tag = dcache_rsp_tag; + assign dcache_rsp_ready = dcache_rsp_if.ready; // // Icache request // - VX_icache_core_req_if #( + VX_icache_req_if #( .WORD_SIZE(4), .CORE_TAG_WIDTH(`ICORE_TAG_WIDTH) - ) icache_core_req_if(); + ) icache_req_if(); - assign icache_req_valid = icache_core_req_if.valid; - assign icache_req_addr = icache_core_req_if.addr; - assign icache_req_tag = icache_core_req_if.tag; - assign icache_core_req_if.ready = icache_req_ready; + assign icache_req_valid = icache_req_if.valid; + assign icache_req_addr = icache_req_if.addr; + assign icache_req_tag = icache_req_if.tag; + assign icache_req_if.ready = icache_req_ready; // // Icache response // - VX_icache_core_rsp_if #( + VX_icache_rsp_if #( .WORD_SIZE(4), .CORE_TAG_WIDTH(`ICORE_TAG_WIDTH) - ) icache_core_rsp_if(); + ) icache_rsp_if(); - assign icache_core_rsp_if.valid = icache_rsp_valid; - assign icache_core_rsp_if.data = icache_rsp_data; - assign icache_core_rsp_if.tag = icache_rsp_tag; - assign icache_rsp_ready = icache_core_rsp_if.ready; + assign icache_rsp_if.valid = icache_rsp_valid; + assign icache_rsp_if.data = icache_rsp_data; + assign icache_rsp_if.tag = icache_rsp_tag; + assign icache_rsp_ready = icache_rsp_if.ready; /////////////////////////////////////////////////////////////////////////// @@ -144,8 +144,8 @@ module VX_pipeline #( `SCOPE_BIND_VX_pipeline_fetch .clk (clk), .reset (fetch_reset), - .icache_req_if (icache_core_req_if), - .icache_rsp_if (icache_core_rsp_if), + .icache_req_if (icache_req_if), + .icache_rsp_if (icache_rsp_if), .wstall_if (wstall_if), .join_if (join_if), .warp_ctl_if (warp_ctl_if), @@ -200,8 +200,8 @@ module VX_pipeline #( .perf_pipeline_if (perf_pipeline_if), `endif - .dcache_req_if (dcache_core_req_if), - .dcache_rsp_if (dcache_core_rsp_if), + .dcache_req_if (dcache_req_if), + .dcache_rsp_if (dcache_rsp_if), .cmt_to_csr_if (cmt_to_csr_if), diff --git a/hw/rtl/VX_smem_arb.v b/hw/rtl/VX_smem_arb.v index 32bbee4f..2383fa88 100644 --- a/hw/rtl/VX_smem_arb.v +++ b/hw/rtl/VX_smem_arb.v @@ -1,22 +1,22 @@ `include "VX_define.vh" module VX_smem_arb ( - input wire clk, - input wire reset, + input wire clk, + input wire reset, // input request - VX_dcache_core_req_if core_req_if, + VX_dcache_req_if core_req_if, // output requests - VX_dcache_core_req_if cache_req_if, - VX_dcache_core_req_if smem_req_if, + VX_dcache_req_if cache_req_if, + VX_dcache_req_if smem_req_if, // input responses - VX_dcache_core_rsp_if cache_rsp_if, - VX_dcache_core_rsp_if smem_rsp_if, + VX_dcache_rsp_if cache_rsp_if, + VX_dcache_rsp_if smem_rsp_if, // output response - VX_dcache_core_rsp_if core_rsp_if + VX_dcache_rsp_if core_rsp_if ); localparam REQ_DATAW = `DCORE_ADDR_WIDTH + 1 + `DWORD_SIZE + (`DWORD_SIZE*8) + (`DCORE_TAG_WIDTH-1); localparam RSP_DATAW = `NUM_THREADS + `NUM_THREADS * (`DWORD_SIZE*8) + `DCORE_TAG_WIDTH; diff --git a/hw/rtl/interfaces/VX_dcache_core_req_if.v b/hw/rtl/interfaces/VX_dcache_req_if.v similarity index 100% rename from hw/rtl/interfaces/VX_dcache_core_req_if.v rename to hw/rtl/interfaces/VX_dcache_req_if.v diff --git a/hw/rtl/interfaces/VX_dcache_core_rsp_if.v b/hw/rtl/interfaces/VX_dcache_rsp_if.v similarity index 100% rename from hw/rtl/interfaces/VX_dcache_core_rsp_if.v rename to hw/rtl/interfaces/VX_dcache_rsp_if.v diff --git a/hw/rtl/interfaces/VX_icache_core_req_if.v b/hw/rtl/interfaces/VX_icache_req_if.v similarity index 100% rename from hw/rtl/interfaces/VX_icache_core_req_if.v rename to hw/rtl/interfaces/VX_icache_req_if.v diff --git a/hw/rtl/interfaces/VX_icache_core_rsp_if.v b/hw/rtl/interfaces/VX_icache_rsp_if.v similarity index 100% rename from hw/rtl/interfaces/VX_icache_core_rsp_if.v rename to hw/rtl/interfaces/VX_icache_rsp_if.v diff --git a/hw/rtl/interfaces/VX_cache_mem_req_if.v b/hw/rtl/interfaces/VX_mem_req_if.v similarity index 100% rename from hw/rtl/interfaces/VX_cache_mem_req_if.v rename to hw/rtl/interfaces/VX_mem_req_if.v diff --git a/hw/rtl/interfaces/VX_cache_mem_rsp_if.v b/hw/rtl/interfaces/VX_mem_rsp_if.v similarity index 100% rename from hw/rtl/interfaces/VX_cache_mem_rsp_if.v rename to hw/rtl/interfaces/VX_mem_rsp_if.v