Vortex 2.0 changes:
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes
This commit is contained in:
Blaise Tine
379
hw/rtl/core/VX_schedule.sv
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379
hw/rtl/core/VX_schedule.sv
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// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_define.vh"
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module VX_schedule import VX_gpu_pkg::*; #(
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parameter CORE_ID = 0
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) (
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input wire clk,
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input wire reset,
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// configuration
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input base_dcrs_t base_dcrs,
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// inputsdecode_if
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VX_warp_ctl_if.slave warp_ctl_if,
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VX_branch_ctl_if.slave branch_ctl_if [`NUM_ALU_BLOCKS],
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VX_decode_sched_if.slave decode_sched_if,
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VX_commit_sched_if.slave commit_sched_if,
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// outputs
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VX_schedule_if.master schedule_if,
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`ifdef GBAR_ENABLE
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VX_gbar_bus_if.master gbar_bus_if,
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`endif
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VX_sched_csr_if.master sched_csr_if,
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// status
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output wire busy
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);
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`UNUSED_PARAM (CORE_ID)
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reg [`NUM_WARPS-1:0] active_warps, active_warps_n; // updated when a warp is activated or disabled
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reg [`NUM_WARPS-1:0] stalled_warps, stalled_warps_n; // set when branch/gpgpu instructions are issued
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reg [`NUM_WARPS-1:0][`NUM_THREADS-1:0] thread_masks, thread_masks_n;
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reg [`NUM_WARPS-1:0][`XLEN-1:0] warp_pcs, warp_pcs_n;
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wire [`NW_WIDTH-1:0] schedule_wid;
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wire [`NUM_THREADS-1:0] schedule_tmask;
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wire [`XLEN-1:0] schedule_pc;
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wire schedule_valid;
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wire schedule_ready;
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// split/join
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wire join_valid;
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wire join_is_dvg;
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wire join_is_else;
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wire [`NW_WIDTH-1:0] join_wid;
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wire [`NUM_THREADS-1:0] join_tmask;
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wire [`XLEN-1:0] join_pc;
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reg [`PERF_CTR_BITS-1:0] cycles;
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reg [`NUM_WARPS-1:0][`UUID_WIDTH-1:0] issued_instrs;
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wire schedule_fire = schedule_valid && schedule_ready;
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wire schedule_if_fire = schedule_if.valid && schedule_if.ready;
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// branch
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wire [`NUM_ALU_BLOCKS-1:0] branch_valid;
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wire [`NUM_ALU_BLOCKS-1:0][`NW_WIDTH-1:0] branch_wid;
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wire [`NUM_ALU_BLOCKS-1:0] branch_taken;
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wire [`NUM_ALU_BLOCKS-1:0][`XLEN-1:0] branch_dest;
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for (genvar i = 0; i < `NUM_ALU_BLOCKS; ++i) begin
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assign branch_valid[i] = branch_ctl_if[i].valid;
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assign branch_wid[i] = branch_ctl_if[i].wid;
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assign branch_taken[i] = branch_ctl_if[i].taken;
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assign branch_dest[i] = branch_ctl_if[i].dest;
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end
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// barriers
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reg [`NUM_BARRIERS-1:0][`NUM_WARPS-1:0] barrier_masks, barrier_masks_n;
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reg [`NUM_WARPS-1:0] barrier_stalls, barrier_stalls_n;
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wire [`CLOG2(`NUM_WARPS+1)-1:0] active_barrier_count;
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wire [`NUM_WARPS-1:0] curr_barrier_mask;
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`ifdef GBAR_ENABLE
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reg [`NUM_WARPS-1:0] curr_barrier_mask_n;
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reg gbar_req_valid;
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reg [`NB_WIDTH-1:0] gbar_req_id;
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reg [`NC_WIDTH-1:0] gbar_req_size_m1;
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`endif
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assign curr_barrier_mask = barrier_masks[warp_ctl_if.barrier.id];
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`POP_COUNT(active_barrier_count, curr_barrier_mask);
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`UNUSED_VAR (active_barrier_count)
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always @(*) begin
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active_warps_n = active_warps;
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stalled_warps_n = stalled_warps;
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thread_masks_n = thread_masks;
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barrier_masks_n = barrier_masks;
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barrier_stalls_n= barrier_stalls;
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warp_pcs_n = warp_pcs;
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// wspawn handling
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if (warp_ctl_if.valid && warp_ctl_if.wspawn.valid) begin
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active_warps_n |= warp_ctl_if.wspawn.wmask;
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for (integer i = 0; i < `NUM_WARPS; ++i) begin
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if (warp_ctl_if.wspawn.wmask[i]) begin
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thread_masks_n[i][0] = 1;
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warp_pcs_n[i] = warp_ctl_if.wspawn.pc;
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end
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end
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stalled_warps_n[warp_ctl_if.wid] = 0; // unlock warp
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end
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// TMC handling
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if (warp_ctl_if.valid && warp_ctl_if.tmc.valid) begin
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active_warps_n[warp_ctl_if.wid] = (warp_ctl_if.tmc.tmask != 0);
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thread_masks_n[warp_ctl_if.wid] = warp_ctl_if.tmc.tmask;
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stalled_warps_n[warp_ctl_if.wid] = 0; // unlock warp
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end
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// split handling
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if (warp_ctl_if.valid && warp_ctl_if.split.valid) begin
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if (warp_ctl_if.split.is_dvg) begin
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thread_masks_n[warp_ctl_if.wid] = warp_ctl_if.split.then_tmask;
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end
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stalled_warps_n[warp_ctl_if.wid] = 0; // unlock warp
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end
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// join handling
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if (join_valid) begin
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if (join_is_dvg) begin
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if (join_is_else) begin
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warp_pcs_n[join_wid] = join_pc;
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end
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thread_masks_n[join_wid] = join_tmask;
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end
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stalled_warps_n[join_wid] = 0; // unlock warp
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end
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// barrier handling
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`ifdef GBAR_ENABLE
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curr_barrier_mask_n = curr_barrier_mask;
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curr_barrier_mask_n[warp_ctl_if.wid] = 1;
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`endif
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if (warp_ctl_if.valid && warp_ctl_if.barrier.valid) begin
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if (~warp_ctl_if.barrier.is_global
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&& (active_barrier_count[`NW_WIDTH-1:0] == warp_ctl_if.barrier.size_m1[`NW_WIDTH-1:0])) begin
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barrier_masks_n[warp_ctl_if.barrier.id] = '0;
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barrier_stalls_n &= ~barrier_masks[warp_ctl_if.barrier.id];
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end else begin
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barrier_masks_n[warp_ctl_if.barrier.id][warp_ctl_if.wid] = 1;
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barrier_stalls_n[warp_ctl_if.wid] = 1;
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end
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stalled_warps_n[warp_ctl_if.wid] = 0; // unlock warp
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end
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`ifdef GBAR_ENABLE
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if (gbar_bus_if.rsp_valid && (gbar_req_id == gbar_bus_if.rsp_id)) begin
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barrier_masks_n[gbar_bus_if.rsp_id] = '0;
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barrier_stalls_n = '0; // unlock all warps
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end
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`endif
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// Branch handling
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for (integer i = 0; i < `NUM_ALU_BLOCKS; ++i) begin
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if (branch_valid[i]) begin
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if (branch_taken[i]) begin
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warp_pcs_n[branch_wid[i]] = branch_dest[i];
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end
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stalled_warps_n[branch_wid[i]] = 0; // unlock warp
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end
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end
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// decode unlock
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if (decode_sched_if.valid && ~decode_sched_if.is_wstall) begin
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stalled_warps_n[decode_sched_if.wid] = 0;
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end
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// CSR unlock
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if (sched_csr_if.unlock_warp) begin
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stalled_warps_n[sched_csr_if.unlock_wid] = 0;
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end
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// stall the warp until decode stage
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if (schedule_fire) begin
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stalled_warps_n[schedule_wid] = 1;
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end
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// advance PC
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if (schedule_if_fire) begin
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warp_pcs_n[schedule_if.data.wid] = schedule_if.data.PC + 4;
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end
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end
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`UNUSED_VAR (base_dcrs)
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always @(posedge clk) begin
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if (reset) begin
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barrier_masks <= '0;
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`ifdef GBAR_ENABLE
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gbar_req_valid <= 0;
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`endif
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stalled_warps <= '0;
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warp_pcs <= '0;
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active_warps <= '0;
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thread_masks <= '0;
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barrier_stalls <= '0;
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issued_instrs <= '0;
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cycles <= '0;
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// activate first warp
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warp_pcs[0] <= base_dcrs.startup_addr;
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active_warps[0] <= 1;
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thread_masks[0][0] <= 1;
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end else begin
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active_warps <= active_warps_n;
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stalled_warps <= stalled_warps_n;
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thread_masks <= thread_masks_n;
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warp_pcs <= warp_pcs_n;
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barrier_masks <= barrier_masks_n;
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barrier_stalls <= barrier_stalls_n;
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// global barrier scheduling
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`ifdef GBAR_ENABLE
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if (warp_ctl_if.valid && warp_ctl_if.barrier.valid
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&& warp_ctl_if.barrier.is_global
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&& (curr_barrier_mask_n == active_warps)) begin
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gbar_req_valid <= 1;
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gbar_req_id <= warp_ctl_if.barrier.id;
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gbar_req_size_m1 <= warp_ctl_if.barrier.size_m1[`NC_WIDTH-1:0];
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end
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if (gbar_bus_if.req_valid && gbar_bus_if.req_ready) begin
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gbar_req_valid <= 0;
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end
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`endif
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if (schedule_if_fire) begin
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issued_instrs[schedule_if.data.wid] <= issued_instrs[schedule_if.data.wid] + `UUID_WIDTH'(1);
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end
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if (busy) begin
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cycles <= cycles + 1;
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end
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end
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end
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// barrier handling
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`ifdef GBAR_ENABLE
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assign gbar_bus_if.req_valid = gbar_req_valid;
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assign gbar_bus_if.req_id = gbar_req_id;
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assign gbar_bus_if.req_size_m1 = gbar_req_size_m1;
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assign gbar_bus_if.req_core_id = `NC_WIDTH'(CORE_ID % `NUM_CORES);
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`endif
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// split/join handling
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`RESET_RELAY (split_join_reset, reset);
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VX_split_join #(
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.CORE_ID (CORE_ID)
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) split_join (
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.clk (clk),
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.reset (split_join_reset),
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.valid (warp_ctl_if.valid),
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.wid (warp_ctl_if.wid),
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.split (warp_ctl_if.split),
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.sjoin (warp_ctl_if.sjoin),
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.join_valid (join_valid),
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.join_is_dvg (join_is_dvg),
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.join_is_else (join_is_else),
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.join_wid (join_wid),
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.join_tmask (join_tmask),
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.join_pc (join_pc)
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);
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// schedule the next ready warp
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wire [`NUM_WARPS-1:0] ready_warps = active_warps & ~(stalled_warps | barrier_stalls);
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VX_lzc #(
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.N (`NUM_WARPS),
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.REVERSE (1)
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) wid_select (
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.data_in (ready_warps),
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.data_out (schedule_wid),
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.valid_out (schedule_valid)
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);
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wire [`NUM_WARPS-1:0][(`NUM_THREADS + `XLEN)-1:0] schedule_data;
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for (genvar i = 0; i < `NUM_WARPS; ++i) begin
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assign schedule_data[i] = {thread_masks[i], warp_pcs[i]};
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end
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assign {schedule_tmask, schedule_pc} = {
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schedule_data[schedule_wid][(`NUM_THREADS + `XLEN)-1:(`NUM_THREADS + `XLEN)-4],
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schedule_data[schedule_wid][(`NUM_THREADS + `XLEN)-5:0]
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};
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`ifndef NDEBUG
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localparam GNW_WIDTH = `LOG2UP(`NUM_CLUSTERS * `NUM_CORES * `NUM_WARPS);
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reg [`UUID_WIDTH-1:0] instr_uuid;
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wire [GNW_WIDTH-1:0] g_wid = (GNW_WIDTH'(CORE_ID) << `NW_BITS) + GNW_WIDTH'(schedule_wid);
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always @(posedge clk) begin
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if (reset) begin
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instr_uuid <= `UUID_WIDTH'(dpi_uuid_gen(1, 0, 0));
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end else if (schedule_fire) begin
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instr_uuid <= `UUID_WIDTH'(dpi_uuid_gen(0, 32'(g_wid), 64'(schedule_pc)));
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end
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end
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`else
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wire [`UUID_WIDTH-1:0] instr_uuid = '0;
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`endif
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VX_elastic_buffer #(
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.DATAW (`NUM_THREADS + `XLEN + `NW_WIDTH)
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) out_buf (
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.clk (clk),
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.reset (reset),
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.valid_in (schedule_valid),
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.ready_in (schedule_ready),
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.data_in ({schedule_tmask, schedule_pc, schedule_wid}),
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.data_out ({schedule_if.data.tmask, schedule_if.data.PC, schedule_if.data.wid}),
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.valid_out (schedule_if.valid),
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.ready_out (schedule_if.ready)
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);
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assign schedule_if.data.uuid = instr_uuid;
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`RESET_RELAY (pending_instr_reset, reset);
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wire no_pending_instr;
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VX_pending_instr #(
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.CTR_WIDTH (12),
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.DECR_COUNT (`ISSUE_WIDTH),
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.ALM_EMPTY (1)
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) pending_instr(
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.clk (clk),
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.reset (pending_instr_reset),
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.incr (schedule_if_fire),
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.incr_wid (schedule_if.data.wid),
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.decr (commit_sched_if.committed),
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.decr_wid (commit_sched_if.committed_wid),
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.alm_empty_wid (sched_csr_if.alm_empty_wid),
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.alm_empty (sched_csr_if.alm_empty),
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.empty (no_pending_instr)
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);
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`BUFFER_BUSY (busy, (active_warps != 0 || ~no_pending_instr), 1);
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// export CSRs
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assign sched_csr_if.cycles = cycles;
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assign sched_csr_if.active_warps = active_warps;
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assign sched_csr_if.thread_masks = thread_masks;
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// timeout handling
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reg [31:0] timeout_ctr;
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reg timeout_enable;
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always @(posedge clk) begin
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if (reset) begin
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timeout_ctr <= '0;
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timeout_enable <= 0;
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end else begin
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if (decode_sched_if.valid && ~decode_sched_if.is_wstall) begin
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timeout_enable <= 1;
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end
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if (timeout_enable && active_warps !=0 && active_warps == stalled_warps) begin
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timeout_ctr <= timeout_ctr + 1;
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end else if (active_warps == 0 || active_warps != stalled_warps) begin
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timeout_ctr <= '0;
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end
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end
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end
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`RUNTIME_ASSERT(timeout_ctr < `STALL_TIMEOUT, ("%t: *** core%0d-scheduler-timeout: stalled_warps=%b", $time, CORE_ID, stalled_warps));
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endmodule
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