Vortex 2.0 changes:
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes
This commit is contained in:
Blaise Tine
@@ -1,829 +1,177 @@
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#!/usr/bin/env python3
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import os
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# Copyright © 2019-2023
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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import sys
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import argparse
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import xml.etree.ElementTree as ET
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import re
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import json
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import argparse
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import math
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vl_include_re = re.compile(r"^\s*`include\s+\"(.+)\"")
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vl_define_re = re.compile(r"^\s*`define\s+(\w+)(\([\w\s,]*\))?(.*)")
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vl_ifdef_re = re.compile(r"^\s*`(ifdef|ifndef|elsif)\s+(\w+)\s*$")
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vl_endif_re = re.compile(r"^\s*`(endif|else)\s*$")
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vl_expand_re = re.compile(r"`([0-9a-zA-Z_]+)")
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vl_int_re = re.compile(r"\d+'s*h([\da-fA-F]+)")
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exclude_files = []
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include_dirs = []
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macros = []
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br_stack = []
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def parse_vl_int(text):
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str_hex = re.sub(vl_int_re, r'\1', text)
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return int(str_hex, 16)
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def translate_ternary(text):
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def source_loc(xml_doc, xml_loc):
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loc = xml_loc.split(",")
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file_id = loc[0]
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start_line = loc[1]
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start_col = loc[2]
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end_line = loc[3]
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end_col = loc[4]
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file = xml_doc.find(".//file/[@id='" + file_id + "']").get("filename")
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return file + " (" + start_line + ":" + start_col + "-" + end_line + ":" + end_col + ")"
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def skip_space(text, i, ln, step):
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while (i >= 0) and (i < ln):
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c = text[i]
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if not c.isspace():
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break
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i += step
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return i
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def skip_expr(text, i, ln, step):
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paren = 0
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checkparen = True
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while (i >= 0) and (i < ln):
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c = text[i]
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if checkparen and (((step < 0) and (c == ')')) or ((step > 0) and (c == '('))):
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paren += 1
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elif checkparen and (((step < 0) and (c == '(')) or ((step > 0) and (c == ')'))):
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if (0 == paren):
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break
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paren -= 1
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if (0 == paren):
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i = skip_space(text, i + step, ln, step)
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checkparen = False
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continue
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elif (0 == paren) and not (c.isalnum() or (c == '_')):
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break
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i += step
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return (i - step)
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def parse_ternary(text):
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ternary = None
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ln = len(text)
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for i in range(1, ln):
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c = text[i]
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if not (c == '?'):
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continue
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# parse condition expression
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i0 = skip_space(text, i - 1, ln, -1)
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if (i < 0):
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raise Exception("invalid condition expression")
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i1 = skip_expr(text, i0, ln, -1)
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if (i1 > i0):
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raise Exception("invalid condition expression")
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# parse true expression
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i2 = skip_space(text, i + 1, ln, 1)
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if (i2 >= ln):
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raise Exception("invalid true expression")
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i3 = skip_expr(text, i2, ln, 1)
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if (i3 < i2):
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raise Exception("invalid true expression")
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# parse colon
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i4 = skip_space(text, i3 + 1, ln, 1)
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if (i4 >= ln):
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raise Exception("invalid colon")
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if not (text[i4] == ':'):
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raise Exception("missing colon")
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# parse false expression
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i5 = skip_space(text, i4 + 1, ln, 1)
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if (i5 >= ln):
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raise Exception("invalid false expression")
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i6 = skip_expr(text, i5, ln, 1)
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if (i6 < i5):
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raise Exception("invalid false expression")
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ternary = (i0, i1, i2, i3, i5, i6)
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break
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return ternary
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while True:
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pos = parse_ternary(text)
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if pos is None:
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break
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# convert to python ternary
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newText = text[:pos[1]] + text[pos[2]:pos[3]+1] + " if " + text[pos[1]:pos[0]+1] + " else " + text[pos[4]:pos[5]+1] + text[pos[5]+1:]
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text = newText
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return text
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def parse_func_args(text):
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args = []
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arg = ''
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l = len(text)
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if text[0] != '(':
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raise Exception("missing leading parenthesis: " + text)
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paren = 1
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for i in range(1, l):
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c = text[i]
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if c == '(':
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paren += 1
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elif c == ')':
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if paren == 0:
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raise Exception("mismatched parenthesis: (" + i + ") " + text)
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paren -= 1
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if paren == 0:
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l = i
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break
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if c == ',' and paren == 1:
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if arg.strip():
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args.append(arg)
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arg = ''
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else:
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arg += c
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if paren != 0:
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raise Exception("missing closing parenthesis: " + text)
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if arg.strip():
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args.append(arg)
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return (args, l)
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def load_include_path(dir):
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if not dir in include_dirs:
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print("*** include path: " + dir)
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include_dirs.append(dir)
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def resolve_include_path(filename, parent_dir):
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if os.path.basename(filename) in exclude_files:
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return None
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if os.path.isfile(filename):
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return os.path.abspath(filename)
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search_dirs = include_dirs
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if parent_dir:
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search_dirs.append(parent_dir)
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for dir in search_dirs:
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filepath = os.path.join(dir, filename)
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if os.path.isfile(filepath):
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return os.path.abspath(filepath)
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raise Exception("couldn't find include file: " + filename + " in " + parent_dir)
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def remove_comments(text):
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text = re.sub(re.compile("/\*.*?\*/",re.DOTALL ), "", text) # multiline
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text = re.sub(re.compile("//.*?\n" ), "\n", text) # singleline
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return text
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def add_macro(name, args, value):
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macro = (name, args, value)
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macros.append(macro)
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'''
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if not args is None:
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print("*** token: " + name + "(", end='')
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for i in range(len(args)):
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if i > 0:
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print(', ', end='')
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print(args[i], end='')
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print(")=" + value)
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def parse_dtype_width(xml_doc, dtype_id):
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xml_type = xml_doc.find(".//typetable/*[@id='" + dtype_id + "']")
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if xml_type.tag == "packarraydtype" or xml_type.tag == "unpackarraydtype":
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sub_dtype_id = xml_type.get("sub_dtype_id")
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base_width = parse_dtype_width(xml_doc, sub_dtype_id)
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const = xml_type.iter("const")
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left = parse_vl_int(next(const).get("name"))
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right = parse_vl_int(next(const).get("name"))
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return base_width * (left - right + 1)
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elif xml_type.tag == "structdtype":
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width = 0
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for member in xml_type.iter("memberdtype"):
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sub_dtype_id = member.get("sub_dtype_id")
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width = width + parse_dtype_width(xml_doc, sub_dtype_id)
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return width
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elif xml_type.tag == "uniondtype":
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width = 0
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for member in xml_type.iter("memberdtype"):
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sub_dtype_id = member.get("sub_dtype_id")
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width = max(width, parse_dtype_width(xml_doc, sub_dtype_id))
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return width
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else:
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print("*** token: " + name + "=" + value)
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'''
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def find_macro(name):
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for macro in macros:
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if macro[0] == name:
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return macro
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return None
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def expand_text(text, params):
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def re_pattern_args(args):
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p = "(?<![0-9a-zA-Z_])("
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i = 0
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for arg in args:
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if i > 0:
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p += "|"
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p += arg
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i += 1
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p += ")(?![0-9a-zA-Z_])"
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return p
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class DoReplParam(object):
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def __init__(self, params):
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self.params = params
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self.expanded = False
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def __call__(self, match):
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name = match.group(1)
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self.expanded = True
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return self.params[name]
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class DoReplMacro(object):
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def __init__(self):
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self.expanded = False
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self.has_func = False
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def __call__(self, match):
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name = match.group(1)
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macro = find_macro(name)
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if macro:
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if not macro[1] is None:
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self.has_func = True
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else:
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self.expanded = True
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return macro[2]
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return "`" + name
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def repl_func_macro(text):
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expanded = False
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match = re.search(vl_expand_re, text)
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if match:
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name = match.group(1)
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macro = find_macro(name)
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if macro:
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args = macro[1]
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value = macro[2]
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if not args is None:
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str_args = text[match.end():].strip()
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f_args = parse_func_args(str_args)
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if len(args) == 0:
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if len(f_args[0]) != 0:
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raise Exception("invalid argments for macro '" + name + "': value=" + text)
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else:
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if len(args) != len(f_args[0]):
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raise Exception("mismatch number of argments for macro '" + name + "': actual=" + len(f_args[0]) + ", expected=" + len(args))
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pattern = re_pattern_args(args)
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params = {}
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for i in range(len(args)):
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params[args[i]] = f_args[0][i]
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dorepl = DoReplParam(params)
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value = re.sub(pattern, dorepl, value)
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str_head = text[0:match.start()]
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str_tail = text[match.end() + f_args[1]+1:]
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text = str_head + value + str_tail
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expanded = True
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if expanded:
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return text
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return None
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changed = False
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iter = 0
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while True:
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if iter > 65536:
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raise Exception("Macro recursion!")
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has_func = False
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while True:
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params_updated = False
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if not params is None:
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do_repl = DoReplParam(params)
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pattern = re_pattern_args(params)
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new_text = re.sub(pattern, do_repl, text)
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if do_repl.expanded:
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text = new_text
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params_updated = True
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do_repl = DoReplMacro()
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new_text = re.sub(vl_expand_re, do_repl, text)
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has_func = do_repl.has_func
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if not (params_updated or do_repl.expanded):
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break
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text = new_text
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changed = True
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if not has_func:
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break
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expanded = repl_func_macro(text)
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if not expanded:
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break
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text = expanded
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changed = True
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iter += 1
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if changed:
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return text
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return None
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def parse_include(filename, nesting):
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print("*** parsing: " + filename + "...")
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if nesting > 99:
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raise Exception("include recursion!")
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#print("*** parsing '" + filename + "'...")
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content = None
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with open(filename, "r") as f:
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content = f.read()
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# remove comments
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content = remove_comments(content)
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# parse content
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prev_line = None
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for line in content.splitlines(False):
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# skip empty lines
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if re.match(re.compile(r'^\s*$'), line):
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continue
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# merge multi-line lines
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if line.endswith('\\'):
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if prev_line:
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prev_line += line[:len(line) - 1]
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else:
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prev_line = line[:len(line) - 1]
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continue
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if prev_line:
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line = prev_line + line
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prev_line = None
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# parse ifdef
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m = re.match(vl_ifdef_re, line)
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if m:
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key = m.group(1)
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cond = m.group(2)
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taken = find_macro(cond) is not None
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if key == 'ifndef':
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taken = not taken
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elif key == '"elsif':
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br_stack.pop()
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br_stack.append(taken)
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#print("*** " + key + "(" + cond + ") => " + str(taken))
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continue
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# parse endif
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m = re.match(vl_endif_re, line)
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if m:
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key = m.group(1)
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top = br_stack.pop()
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if key == 'else':
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br_stack.append(not top)
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#print("*** " + key)
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continue
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# skip disabled blocks
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if not all(br_stack):
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continue
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sub_dtype_id = xml_type.get("sub_dtype_id")
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if sub_dtype_id != None:
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return parse_dtype_width(xml_doc, sub_dtype_id)
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left = xml_type.get("left")
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right = xml_type.get("right")
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if left != None and right != None:
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return int(left) - int(right) + 1
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return 1
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|
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# parse include
|
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m = re.match(vl_include_re, line)
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if m:
|
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include = m.group(1)
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include = resolve_include_path(include, os.path.dirname(filename))
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if include:
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parse_include(include, nesting + 1)
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continue
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# parse define
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m = re.match(vl_define_re, line)
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if m:
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name = m.group(1)
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args = m.group(2)
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if args:
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args = args[1:len(args)-1].strip()
|
||||
if args != '':
|
||||
args = args.split(',')
|
||||
for i in range(len(args)):
|
||||
args[i] = args[i].strip()
|
||||
else:
|
||||
args = []
|
||||
value = m.group(3)
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||||
add_macro(name, args, value.strip())
|
||||
def parse_var_name(xml_doc, xml_node):
|
||||
if xml_node.tag == "varref":
|
||||
return xml_node.get("name")
|
||||
elif xml_node.tag == "varxref":
|
||||
name = xml_node.get("name")
|
||||
dotted = xml_node.get("dotted")
|
||||
return dotted + '.' + name
|
||||
else:
|
||||
raise ET.ParseError("invalid probe entry" + source_loc(xml_doc, xml_node.get("loc")))
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return name
|
||||
|
||||
def parse_sel_name(xml_doc, xml_node):
|
||||
name = parse_var_name(xml_doc, xml_node.find("*"))
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||||
const = xml_node.iter("const")
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||||
offset = parse_vl_int(next(const).get("name"))
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||||
#size = parse_vl_int(next(const).get("name"))
|
||||
return name + '_' + str(offset)
|
||||
|
||||
def parse_array_name(xml_doc, xml_node):
|
||||
if xml_node.tag == "arraysel":
|
||||
name = parse_array_name(xml_doc, xml_node.find("*"))
|
||||
xml_size = xml_node.find("const").get("name")
|
||||
array_size = parse_vl_int(xml_size)
|
||||
name = name + '_' + str(array_size)
|
||||
else:
|
||||
name = parse_var_name(xml_doc, xml_node)
|
||||
return name
|
||||
|
||||
def parse_vl_port(xml_doc, xml_node, signals):
|
||||
total_width = 0
|
||||
if xml_node.tag == "concat":
|
||||
for xml_child in xml_node.findall("*"):
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||||
total_width = total_width + parse_vl_port(xml_doc, xml_child, signals)
|
||||
elif xml_node.tag == "varref" or xml_node.tag == "varxref":
|
||||
name = parse_var_name(xml_doc, xml_node)
|
||||
dtype_id = xml_node.get("dtype_id")
|
||||
signal_width = parse_dtype_width(xml_doc, dtype_id)
|
||||
signals.append([name, signal_width])
|
||||
total_width = total_width + signal_width
|
||||
elif xml_node.tag == "sel":
|
||||
name = parse_sel_name(xml_doc, xml_node)
|
||||
dtype_id = xml_node.get("dtype_id")
|
||||
signal_width = parse_dtype_width(xml_doc, dtype_id)
|
||||
signals.append([name, signal_width])
|
||||
total_width = total_width + signal_width
|
||||
elif xml_node.tag == "arraysel":
|
||||
name = parse_array_name(xml_doc, xml_node)
|
||||
dtype_id = xml_node.get("dtype_id")
|
||||
signal_width = parse_dtype_width(xml_doc, dtype_id)
|
||||
signals.append([name, signal_width])
|
||||
total_width = total_width + signal_width
|
||||
else:
|
||||
raise ET.ParseError("invalid probe entry: " + source_loc(xml_doc, xml_node.get("loc")))
|
||||
return total_width
|
||||
|
||||
def parse_xml(filename, max_taps):
|
||||
xml_doc = ET.parse(filename)
|
||||
modules = {}
|
||||
xml_modules = xml_doc.findall(".//module/[@origName='VX_scope_tap']")
|
||||
for xml_module in xml_modules:
|
||||
scope_id = parse_vl_int(xml_module.find(".//var/[@name='SCOPE_ID']/const").get("name"))
|
||||
triggerw = parse_vl_int(xml_module.find(".//var/[@name='TRIGGERW']/const").get("name"))
|
||||
probew = parse_vl_int(xml_module.find(".//var/[@name='PROBEW']/const").get("name"))
|
||||
module_name = xml_module.get("name")
|
||||
modules[module_name] = [scope_id, triggerw, probew]
|
||||
|
||||
taps = []
|
||||
xml_instances = xml_doc.iter("instance")
|
||||
for xml_instance in xml_instances:
|
||||
if (max_taps != -1 and len(taps) >= max_taps):
|
||||
break
|
||||
defName = xml_instance.get("defName")
|
||||
module = modules.get(defName)
|
||||
if module is None:
|
||||
continue
|
||||
triggers = []
|
||||
probes = []
|
||||
w = parse_vl_port(xml_doc, xml_instance.find(".//port/[@name='triggers']/*"), triggers)
|
||||
if w != module[1]:
|
||||
raise ET.ParseError("invalid triggers width: actual=" + str(w) + ", expected=" + str(module[1]))
|
||||
w = parse_vl_port(xml_doc, xml_instance.find(".//port/[@name='probes']/*"), probes)
|
||||
if w != module[2]:
|
||||
raise ET.ParseError("invalid probes width: actual=" + str(w) + ", expected=" + str(module[2]))
|
||||
signals = probes
|
||||
for trigger in triggers:
|
||||
signals.append(trigger)
|
||||
loc = xml_instance.get("loc")
|
||||
hier = xml_doc.find(".//cell/[@loc='" + loc + "']").get("hier")
|
||||
path = hier.rsplit(".", 1)[0]
|
||||
taps.append({"id":module[0],
|
||||
"width":module[1] + module[2],
|
||||
"signals":signals,
|
||||
"path":path})
|
||||
|
||||
def parse_includes(includes):
|
||||
# change current directory to include directory
|
||||
old_dir = os.getcwd()
|
||||
script_dir = os.path.dirname(os.path.realpath(__file__))
|
||||
os.chdir(script_dir)
|
||||
|
||||
for include in includes:
|
||||
parse_include(include, 0)
|
||||
load_include_path(os.path.dirname(include))
|
||||
|
||||
# restore current directory
|
||||
os.chdir(old_dir)
|
||||
|
||||
def load_defines(defines):
|
||||
for define in defines:
|
||||
key_value = define.split('=', 2)
|
||||
name = key_value[0]
|
||||
value = ''
|
||||
if len(key_value) == 2:
|
||||
value = key_value[1]
|
||||
add_macro(name, None, value)
|
||||
|
||||
def load_config(filename):
|
||||
with open(filename, "r") as f:
|
||||
config = json.load(f)
|
||||
print("condfig=", config)
|
||||
return config
|
||||
|
||||
def eval_node(text, params):
|
||||
def clog2(x):
|
||||
l2 = math.log2(x)
|
||||
cl = math.ceil(l2)
|
||||
return int(cl)
|
||||
|
||||
if not type(text) == str:
|
||||
return text
|
||||
|
||||
expanded = expand_text(text, params)
|
||||
if expanded:
|
||||
text = expanded
|
||||
|
||||
try:
|
||||
__text = text.replace('$clog2', '__clog2')
|
||||
__text = translate_ternary(__text)
|
||||
__text = __text.replace('||', 'or')
|
||||
__text = __text.replace('&&', 'and')
|
||||
e = eval(__text, {'__clog2': clog2})
|
||||
return e
|
||||
except (NameError, SyntaxError):
|
||||
return text
|
||||
|
||||
def gen_vl_header(file, modules, taps):
|
||||
|
||||
header = '''
|
||||
`ifndef VX_SCOPE_DEFS
|
||||
`define VX_SCOPE_DEFS
|
||||
'''
|
||||
footer = '`endif'
|
||||
|
||||
def signal_size(size, mn):
|
||||
if type(size) == int:
|
||||
if (size != mn):
|
||||
return "[" + str(size-1) + ":0]"
|
||||
else:
|
||||
return ""
|
||||
else:
|
||||
return "[" + size + "-1:0]"
|
||||
|
||||
def create_signal(key, ports):
|
||||
if not key in ports:
|
||||
ports[key] = []
|
||||
return ports[key]
|
||||
|
||||
def dic_insert(gdic, ldic, key, value, enabled):
|
||||
if enabled:
|
||||
ldic[key] = value
|
||||
if key in gdic:
|
||||
return False
|
||||
if enabled:
|
||||
gdic[key] = None
|
||||
return True
|
||||
|
||||
def trigger_name(name, size):
|
||||
if type(size) == int:
|
||||
if size != 1:
|
||||
return "(| " + name + ")"
|
||||
else:
|
||||
return name
|
||||
else:
|
||||
return "(| " + name + ")"
|
||||
|
||||
def trigger_subscripts(asize):
|
||||
def Q(arr, ss, asize, idx, N):
|
||||
a = asize[idx]
|
||||
if (a != 0):
|
||||
for i in range(a):
|
||||
tmp = ss + '[' + str(i) + ']'
|
||||
if (idx + 1) < N:
|
||||
Q(arr, tmp, asize, idx + 1, N)
|
||||
else:
|
||||
arr.append(tmp)
|
||||
else:
|
||||
if (idx + 1) < N:
|
||||
Q(arr, ss, asize, idx + 1, N)
|
||||
else:
|
||||
arr.append(ss)
|
||||
|
||||
if asize is None:
|
||||
return [""]
|
||||
ln = len(asize)
|
||||
if (0 == ln):
|
||||
return [""]
|
||||
arr = []
|
||||
Q(arr, "", asize, 0, ln)
|
||||
return arr
|
||||
|
||||
|
||||
def visit_path(alltaps, ports, ntype, paths, modules, taps):
|
||||
curtaps = {}
|
||||
|
||||
if (len(paths) != 0):
|
||||
spath = paths.pop(0)
|
||||
snodes = modules[ntype]["submodules"]
|
||||
if not spath in snodes:
|
||||
raise Exception("invalid path: " + spath + " in " + ntype)
|
||||
|
||||
snode = snodes[spath]
|
||||
|
||||
stype = snode["type"]
|
||||
|
||||
enabled = True
|
||||
if "enabled" in snode:
|
||||
enabled = eval_node(snode["enabled"], None)
|
||||
|
||||
subtaps = visit_path(alltaps, ports, stype, paths, modules, taps)
|
||||
|
||||
scount = 0
|
||||
if "count" in snode:
|
||||
scount = eval_node(snode["count"], None)
|
||||
|
||||
params = None
|
||||
if "params" in snode:
|
||||
params = snode["params"]
|
||||
|
||||
new_staps = []
|
||||
|
||||
nn = "SCOPE_IO_" + ntype
|
||||
pp = create_signal(nn, ports)
|
||||
|
||||
for key in subtaps:
|
||||
subtap = subtaps[key]
|
||||
s = subtap[0]
|
||||
a = subtap[1]
|
||||
t = subtap[2]
|
||||
|
||||
aa = [scount]
|
||||
sa = signal_size(scount, 0)
|
||||
if a:
|
||||
for i in a:
|
||||
x = eval_node(i, params)
|
||||
aa.append(x)
|
||||
sa += signal_size(x, 0)
|
||||
|
||||
if dic_insert(alltaps, curtaps, spath + '/' + key, (s, aa, t), enabled):
|
||||
skey = key.replace('/', '_')
|
||||
if enabled:
|
||||
pp.append("\toutput wire" + sa + signal_size(s, 1) + " scope_" + spath + '_' + skey + ',')
|
||||
new_staps.append(skey)
|
||||
|
||||
ports[nn] = pp
|
||||
|
||||
if (0 == scount):
|
||||
nn = "SCOPE_BIND_" + ntype + '_' + spath
|
||||
pp = create_signal(nn, ports)
|
||||
|
||||
for st in new_staps:
|
||||
if enabled:
|
||||
pp.append("\t.scope_" + st + "(scope_" + spath + '_' + st + "),")
|
||||
else:
|
||||
pp.append("\t`UNUSED_PIN (scope_" + st + "),")
|
||||
|
||||
ports[nn] = pp
|
||||
else:
|
||||
nn = "SCOPE_BIND_" + ntype + '_' + spath + "(__i__)"
|
||||
pp = create_signal(nn, ports)
|
||||
|
||||
for st in new_staps:
|
||||
if enabled:
|
||||
pp.append("\t.scope_" + st + "(scope_" + spath + '_' + st + "[__i__]),")
|
||||
else:
|
||||
pp.append("\t`UNUSED_PIN (scope_" + st + "),")
|
||||
|
||||
ports[nn] = pp
|
||||
else:
|
||||
nn = "SCOPE_IO_" + ntype
|
||||
pp = create_signal(nn, ports)
|
||||
|
||||
for tk in taps:
|
||||
trigger = 0
|
||||
name = tk
|
||||
size = eval_node(taps[tk], None)
|
||||
if name[0] == '!':
|
||||
name = name[1:]
|
||||
trigger = 1
|
||||
elif name[0] == '?':
|
||||
name = name[1:]
|
||||
trigger = 2
|
||||
if dic_insert(alltaps, curtaps, name, (size, None, trigger), True):
|
||||
pp.append("\toutput wire" + signal_size(size, 1) + " scope_" + name + ',')
|
||||
|
||||
ports[nn] = pp
|
||||
|
||||
return curtaps
|
||||
|
||||
toptaps = {}
|
||||
|
||||
with open(file, 'w') as f:
|
||||
|
||||
ports = {}
|
||||
alltaps = {}
|
||||
|
||||
for key in taps:
|
||||
skey_list = key.split(',')
|
||||
_taps = taps[key]
|
||||
for skey in skey_list:
|
||||
#print('*** processing node: ' + skey + ' ...')
|
||||
paths = skey.strip().split('/')
|
||||
ntype = paths.pop(0)
|
||||
curtaps = visit_path(alltaps, ports, ntype, paths, modules, _taps)
|
||||
for tk in curtaps:
|
||||
toptaps[tk] = curtaps[tk]
|
||||
|
||||
print(header, file=f)
|
||||
|
||||
for key in ports:
|
||||
print("`define " + key + ' \\', file=f)
|
||||
for port in ports[key]:
|
||||
print(port + ' \\', file=f)
|
||||
print("", file=f)
|
||||
|
||||
print("`define SCOPE_DECL_SIGNALS \\", file=f)
|
||||
i = 0
|
||||
for key in toptaps:
|
||||
tap = toptaps[key]
|
||||
name = key.replace('/', '_')
|
||||
size = tap[0]
|
||||
asize = tap[1]
|
||||
sa = ""
|
||||
if asize:
|
||||
for a in asize:
|
||||
sa += signal_size(a, 0)
|
||||
if i > 0:
|
||||
print(" \\", file=f)
|
||||
print('\t wire' + sa + signal_size(size, 1) + " scope_" + name + ';', file=f, end='')
|
||||
i += 1
|
||||
print("", file=f)
|
||||
print("", file=f)
|
||||
|
||||
print("`define SCOPE_DATA_LIST \\", file=f)
|
||||
i = 0
|
||||
for key in toptaps:
|
||||
tap = toptaps[key]
|
||||
trigger = tap[2]
|
||||
if trigger != 0:
|
||||
continue
|
||||
name = key.replace('/', '_')
|
||||
if i > 0:
|
||||
print(", \\", file=f)
|
||||
print("\t scope_" + name, file=f, end='')
|
||||
i += 1
|
||||
print("", file=f)
|
||||
print("", file=f)
|
||||
|
||||
print("`define SCOPE_UPDATE_LIST \\", file=f)
|
||||
i = 0
|
||||
for key in toptaps:
|
||||
tap = toptaps[key]
|
||||
trigger = tap[2]
|
||||
if trigger == 0:
|
||||
continue
|
||||
name = key.replace('/', '_')
|
||||
if i > 0:
|
||||
print(", \\", file=f)
|
||||
print("\t scope_" + name, file=f, end='')
|
||||
i += 1
|
||||
print("", file=f)
|
||||
print("", file=f)
|
||||
|
||||
print("`define SCOPE_TRIGGER \\", file=f)
|
||||
i = 0
|
||||
for key in toptaps:
|
||||
tap = toptaps[key]
|
||||
if tap[2] != 2:
|
||||
continue
|
||||
size = tap[0]
|
||||
asize = tap[1]
|
||||
sus = trigger_subscripts(asize)
|
||||
for su in sus:
|
||||
if i > 0:
|
||||
print(" | \\", file=f)
|
||||
print("\t(", file=f, end='')
|
||||
name = trigger_name("scope_" + key.replace('/', '_') + su, size)
|
||||
print(name, file=f, end='')
|
||||
print(")", file=f, end='')
|
||||
i += 1
|
||||
print("", file=f)
|
||||
print("", file=f)
|
||||
|
||||
print(footer, file=f)
|
||||
|
||||
return toptaps
|
||||
|
||||
def gen_cc_header(file, taps):
|
||||
|
||||
header = '''
|
||||
#pragma once
|
||||
|
||||
struct scope_module_t {
|
||||
const char* name;
|
||||
int index;
|
||||
int parent;
|
||||
};
|
||||
|
||||
struct scope_tap_t {
|
||||
int width;
|
||||
const char* name;
|
||||
int module;
|
||||
};
|
||||
'''
|
||||
def flatten_path(paths, sizes):
|
||||
def Q(arr, ss, idx, N, paths, sizes):
|
||||
size = sizes[idx]
|
||||
if size != 0:
|
||||
for i in range(sizes[idx]):
|
||||
tmp = ss + ('/' if (ss != '') else '')
|
||||
tmp += paths[idx] + '_' + str(i)
|
||||
if (idx + 1) < N:
|
||||
Q(arr, tmp, idx + 1, N, paths, sizes)
|
||||
else:
|
||||
arr.append(tmp)
|
||||
else:
|
||||
tmp = ss + ('/' if (ss != '') else '')
|
||||
tmp += paths[idx]
|
||||
if (idx + 1) < N:
|
||||
Q(arr, tmp, idx + 1, N, paths, sizes)
|
||||
else:
|
||||
arr.append(tmp)
|
||||
|
||||
arr = []
|
||||
Q(arr, "", 0, len(asize), paths, asize)
|
||||
return arr
|
||||
|
||||
# flatten the taps
|
||||
fdic = {}
|
||||
for key in taps:
|
||||
tap = taps[key]
|
||||
size = str(tap[0])
|
||||
trigger = tap[2]
|
||||
if (trigger != 0):
|
||||
continue
|
||||
paths = key.split('/')
|
||||
if (len(paths) > 1):
|
||||
name = paths.pop(-1)
|
||||
asize = tap[1]
|
||||
for ss in flatten_path(paths, asize):
|
||||
fdic[ss + '/' + name ] = [size, 0]
|
||||
else:
|
||||
fdic[key] = [size, 0]
|
||||
for key in taps:
|
||||
tap = taps[key]
|
||||
size = str(tap[0])
|
||||
trigger = tap[2]
|
||||
if (trigger == 0):
|
||||
continue
|
||||
paths = key.split('/')
|
||||
if (len(paths) > 1):
|
||||
name = paths.pop(-1)
|
||||
asize = tap[1]
|
||||
for ss in flatten_path(paths, asize):
|
||||
fdic[ss + '/' + name ] = [size, 0]
|
||||
else:
|
||||
fdic[key] = [size, 0]
|
||||
|
||||
# generate module dic
|
||||
mdic = {}
|
||||
mdic["*"] = ("*", 0, -1)
|
||||
for key in fdic:
|
||||
paths = key.split('/')
|
||||
if len(paths) == 1:
|
||||
continue
|
||||
paths.pop(-1)
|
||||
parent = 0
|
||||
mk = ""
|
||||
for path in paths:
|
||||
mk += '/' + path
|
||||
if not mk in mdic:
|
||||
index = len(mdic)
|
||||
mdic[mk] = (path, index, parent)
|
||||
parent = index
|
||||
else:
|
||||
parent = mdic[mk][1]
|
||||
fdic[key][1] = parent
|
||||
|
||||
with open(file, 'w') as f:
|
||||
print(header, file=f)
|
||||
|
||||
print("static constexpr scope_module_t scope_modules[] = {", file=f)
|
||||
i = 0
|
||||
for key in mdic:
|
||||
m = mdic[key]
|
||||
if i > 0:
|
||||
print(',', file=f)
|
||||
print("\t{\"" + m[0] + "\", " + str(m[1]) + ", " + str(m[2]) + "}", file=f, end='')
|
||||
i += 1
|
||||
print("", file=f)
|
||||
print("};", file=f)
|
||||
|
||||
print("", file=f)
|
||||
print("static constexpr scope_tap_t scope_taps[] = {", file=f)
|
||||
i = 0
|
||||
for key in fdic:
|
||||
size = fdic[key][0]
|
||||
parent = fdic[key][1]
|
||||
paths = key.split('/')
|
||||
if len(paths) > 1:
|
||||
name = paths.pop(-1)
|
||||
else:
|
||||
name = key
|
||||
if i > 0:
|
||||
print(',', file=f)
|
||||
print("\t{" + size + ", \"" + name + "\", " + str(parent) + "}", file=f, end='')
|
||||
i += 1
|
||||
print("", file=f)
|
||||
print("};", file=f)
|
||||
return {"version":"0.1.0", "taps":taps}
|
||||
|
||||
def main():
|
||||
parser = argparse.ArgumentParser(description='Scope headers generator.')
|
||||
parser.add_argument('-vl', nargs='?', default='scope-defs.vh', metavar='file', help='Output Verilog header')
|
||||
parser.add_argument('-cc', nargs='?', default='scope-defs.h', metavar='file', help='Output C++ header')
|
||||
parser.add_argument('-D', nargs='?', action='append', metavar='macro[=value]', help='define macro')
|
||||
parser.add_argument('-I', nargs='?', action='append', metavar='<includedir>', help='include directory')
|
||||
parser.add_argument('config', help='Json config file')
|
||||
parser.add_argument('-o', nargs='?', default='scope.json', metavar='o', help='Output JSON manifest')
|
||||
parser.add_argument('-n', nargs='?', default=-1, metavar='n', type=int, help='Maximum number of taps to read')
|
||||
parser.add_argument('xml', help='Design XML descriptor file')
|
||||
args = parser.parse_args()
|
||||
print("args=", args)
|
||||
|
||||
global exclude_files
|
||||
global include_dirs
|
||||
global macros
|
||||
global br_stack
|
||||
|
||||
if args.I:
|
||||
for dir in args.I:
|
||||
load_include_path(dir)
|
||||
|
||||
if args.D:
|
||||
load_defines(args.D)
|
||||
|
||||
config = load_config(args.config)
|
||||
|
||||
exclude_files.append(os.path.basename(args.vl))
|
||||
|
||||
if "include_paths" in config:
|
||||
for path in config["include_paths"]:
|
||||
load_include_path(path)
|
||||
|
||||
if "includes" in config:
|
||||
parse_includes(config["includes"])
|
||||
|
||||
taps = gen_vl_header(args.vl, config["modules"], config["taps"])
|
||||
gen_cc_header(args.cc, taps)
|
||||
#print("args=", args)
|
||||
scope_taps = parse_xml(args.xml, args.n)
|
||||
with open(args.o, "w") as f:
|
||||
json.dump(scope_taps, f, ensure_ascii=False, indent=4)
|
||||
|
||||
if __name__ == '__main__':
|
||||
main()
|
||||
main()
|
||||
|
||||
Reference in New Issue
Block a user