Vortex 2.0 changes:
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes
This commit is contained in:
Blaise Tine
397
runtime/simx/vortex.cpp
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397
runtime/simx/vortex.cpp
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// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <assert.h>
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#include <iostream>
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#include <future>
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#include <chrono>
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#include <vortex.h>
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#include <utils.h>
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#include <malloc.h>
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#include <VX_config.h>
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#include <VX_types.h>
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#include <util.h>
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#include <processor.h>
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#include <arch.h>
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#include <mem.h>
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#include <constants.h>
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#ifndef NDEBUG
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#define DBGPRINT(format, ...) do { printf("[VXDRV] " format "", ##__VA_ARGS__); } while (0)
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#else
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#define DBGPRINT(format, ...) ((void)0)
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#endif
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using namespace vortex;
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///////////////////////////////////////////////////////////////////////////////
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class vx_device;
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class vx_buffer {
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public:
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vx_buffer(uint64_t size, vx_device* device)
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: size_(size)
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, device_(device) {
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uint64_t aligned_asize = aligned_size(size, CACHE_BLOCK_SIZE);
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data_ = aligned_malloc(aligned_asize, CACHE_BLOCK_SIZE);
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// set uninitialized data to "baadf00d"
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for (uint32_t i = 0; i < aligned_asize; ++i) {
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((uint8_t*)data_)[i] = (0xbaadf00d >> ((i & 0x3) * 8)) & 0xff;
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}
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}
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~vx_buffer() {
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if (data_) {
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aligned_free(data_);
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}
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}
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void* data() const {
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return data_;
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}
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uint64_t size() const {
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return size_;
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}
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vx_device* device() const {
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return device_;
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}
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private:
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uint64_t size_;
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vx_device* device_;
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void* data_;
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};
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///////////////////////////////////////////////////////////////////////////////
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class vx_device {
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public:
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vx_device()
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: arch_(NUM_THREADS, NUM_WARPS, NUM_CORES, NUM_CLUSTERS)
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, ram_(RAM_PAGE_SIZE)
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, processor_(arch_)
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, global_mem_(
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ALLOC_BASE_ADDR,
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ALLOC_MAX_ADDR - ALLOC_BASE_ADDR,
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RAM_PAGE_SIZE,
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CACHE_BLOCK_SIZE)
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, local_mem_(
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SMEM_BASE_ADDR,
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(1ull << SMEM_LOG_SIZE),
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RAM_PAGE_SIZE,
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1)
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{
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// attach memory module
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processor_.attach_ram(&ram_);
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}
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~vx_device() {
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if (future_.valid()) {
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future_.wait();
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}
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}
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int mem_alloc(uint64_t size, int type, uint64_t* dev_addr) {
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if (type == VX_MEM_TYPE_GLOBAL) {
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return global_mem_.allocate(size, dev_addr);
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} else if (type == VX_MEM_TYPE_LOCAL) {
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return local_mem_.allocate(size, dev_addr);
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}
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return -1;
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}
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int mem_free(uint64_t dev_addr) {
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if (dev_addr >= SMEM_BASE_ADDR) {
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return local_mem_.release(dev_addr);
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} else {
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return global_mem_.release(dev_addr);
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}
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}
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int mem_info(int type, uint64_t* mem_free, uint64_t* mem_used) const {
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if (type == VX_MEM_TYPE_GLOBAL) {
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if (mem_free)
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*mem_free = global_mem_.free();
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if (mem_used)
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*mem_used = global_mem_.allocated();
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} else if (type == VX_MEM_TYPE_LOCAL) {
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if (mem_free)
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*mem_free = local_mem_.free();
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if (mem_used)
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*mem_free = local_mem_.allocated();
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} else {
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return -1;
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}
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return 0;
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}
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int upload(uint64_t dest_addr, const void* src, uint64_t size) {
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uint64_t asize = aligned_size(size, CACHE_BLOCK_SIZE);
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if (dest_addr + asize > GLOBAL_MEM_SIZE)
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return -1;
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ram_.write((const uint8_t*)src, dest_addr, size);
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/*DBGPRINT("upload %ld bytes to 0x%lx\n", size, dest_addr);
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for (uint64_t i = 0; i < size && i < 1024; i += 4) {
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DBGPRINT(" 0x%lx <- 0x%x\n", dest_addr + i, *(uint32_t*)((uint8_t*)src + i));
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}*/
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return 0;
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}
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int download(void* dest, uint64_t src_addr, uint64_t size) {
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uint64_t asize = aligned_size(size, CACHE_BLOCK_SIZE);
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if (src_addr + asize > GLOBAL_MEM_SIZE)
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return -1;
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ram_.read((uint8_t*)dest, src_addr, size);
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/*DBGPRINT("download %ld bytes from 0x%lx\n", size, src_addr);
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for (uint64_t i = 0; i < size && i < 1024; i += 4) {
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DBGPRINT(" 0x%lx -> 0x%x\n", src_addr + i, *(uint32_t*)((uint8_t*)dest + i));
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}*/
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return 0;
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}
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int start() {
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// ensure prior run completed
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if (future_.valid()) {
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future_.wait();
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}
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// start new run
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future_ = std::async(std::launch::async, [&]{
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processor_.run(false);
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});
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return 0;
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}
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int wait(uint64_t timeout) {
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if (!future_.valid())
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return 0;
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uint64_t timeout_sec = timeout / 1000;
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std::chrono::seconds wait_time(1);
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for (;;) {
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// wait for 1 sec and check status
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auto status = future_.wait_for(wait_time);
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if (status == std::future_status::ready
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|| 0 == timeout_sec--)
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break;
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}
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return 0;
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}
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int write_dcr(uint32_t addr, uint32_t value) {
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if (future_.valid()) {
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future_.wait(); // ensure prior run completed
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}
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processor_.write_dcr(addr, value);
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dcrs_.write(addr, value);
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return 0;
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}
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uint64_t read_dcr(uint32_t addr) const {
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return dcrs_.read(addr);
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}
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private:
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Arch arch_;
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RAM ram_;
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Processor processor_;
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MemoryAllocator global_mem_;
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MemoryAllocator local_mem_;
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DeviceConfig dcrs_;
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std::future<void> future_;
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};
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///////////////////////////////////////////////////////////////////////////////
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extern int vx_dev_open(vx_device_h* hdevice) {
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if (nullptr == hdevice)
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return -1;
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auto device = new vx_device();
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if (device == nullptr)
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return -1;
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int err = dcr_initialize(device);
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if (err != 0) {
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delete device;
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return err;
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}
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#ifdef DUMP_PERF_STATS
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perf_add_device(device);
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#endif
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*hdevice = device;
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DBGPRINT("device creation complete!\n");
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return 0;
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}
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extern int vx_dev_close(vx_device_h hdevice) {
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if (nullptr == hdevice)
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return -1;
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vx_device *device = ((vx_device*)hdevice);
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#ifdef DUMP_PERF_STATS
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perf_remove_device(hdevice);
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#endif
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delete device;
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DBGPRINT("device destroyed!\n");
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return 0;
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}
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extern int vx_dev_caps(vx_device_h hdevice, uint32_t caps_id, uint64_t *value) {
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if (nullptr == hdevice)
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return -1;
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vx_device *device = ((vx_device*)hdevice);
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switch (caps_id) {
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case VX_CAPS_VERSION:
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*value = IMPLEMENTATION_ID;
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break;
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case VX_CAPS_NUM_THREADS:
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*value = NUM_THREADS;
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break;
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case VX_CAPS_NUM_WARPS:
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*value = NUM_WARPS;
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break;
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case VX_CAPS_NUM_CORES:
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*value = NUM_CORES * NUM_CLUSTERS;
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break;
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case VX_CAPS_CACHE_LINE_SIZE:
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*value = CACHE_BLOCK_SIZE;
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break;
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case VX_CAPS_GLOBAL_MEM_SIZE:
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*value = GLOBAL_MEM_SIZE;
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break;
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case VX_CAPS_KERNEL_BASE_ADDR:
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*value = (uint64_t(device->read_dcr(VX_DCR_BASE_STARTUP_ADDR1)) << 32)
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break;
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case VX_CAPS_ISA_FLAGS:
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*value = ((uint64_t(MISA_EXT))<<32) | ((log2floor(XLEN)-4) << 30) | MISA_STD;
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break;
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default:
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std::cout << "invalid caps id: " << caps_id << std::endl;
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std::abort();
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return -1;
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}
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return 0;
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}
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extern int vx_mem_alloc(vx_device_h hdevice, uint64_t size, int type, uint64_t* dev_addr) {
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if (nullptr == hdevice
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|| nullptr == dev_addr
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|| 0 == size)
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return -1;
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vx_device *device = ((vx_device*)hdevice);
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return device->mem_alloc(size, type, dev_addr);
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}
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extern int vx_mem_free(vx_device_h hdevice, uint64_t dev_addr) {
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if (nullptr == hdevice)
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return -1;
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if (0 == dev_addr)
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return 0;
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vx_device *device = ((vx_device*)hdevice);
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return device->mem_free(dev_addr);
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}
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extern int vx_mem_info(vx_device_h hdevice, int type, uint64_t* mem_free, uint64_t* mem_used) {
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if (nullptr == hdevice)
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return -1;
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auto device = ((vx_device*)hdevice);
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return device->mem_info(type, mem_free, mem_used);
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}
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extern int vx_copy_to_dev(vx_device_h hdevice, uint64_t dev_addr, const void* host_ptr, uint64_t size) {
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if (nullptr == hdevice)
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return -1;
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auto device = ((vx_device*)hdevice);
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DBGPRINT("COPY_TO_DEV: dev_addr=0x%lx, host_addr=0x%lx, size=%ld\n", dev_addr, host_ptr, size);
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return device->upload(dev_addr, host_ptr, size);
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}
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extern int vx_copy_from_dev(vx_device_h hdevice, void* host_ptr, uint64_t dev_addr, uint64_t size) {
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if (nullptr == hdevice)
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return -1;
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auto device = ((vx_device*)hdevice);
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DBGPRINT("COPY_FROM_DEV: dev_addr=0x%lx, host_addr=0x%lx, size=%ld\n", dev_addr, host_ptr, size);
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return device->download(host_ptr, dev_addr, size);
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}
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extern int vx_start(vx_device_h hdevice) {
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if (nullptr == hdevice)
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return -1;
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DBGPRINT("START\n");
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vx_device *device = ((vx_device*)hdevice);
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return device->start();
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}
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extern int vx_ready_wait(vx_device_h hdevice, uint64_t timeout) {
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if (nullptr == hdevice)
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return -1;
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vx_device *device = ((vx_device*)hdevice);
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return device->wait(timeout);
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}
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extern int vx_dcr_write(vx_device_h hdevice, uint32_t addr, uint64_t value) {
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if (nullptr == hdevice)
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return -1;
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vx_device *device = ((vx_device*)hdevice);
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// Ensure ready for new command
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if (vx_ready_wait(hdevice, -1) != 0)
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return -1;
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DBGPRINT("DCR_WRITE: addr=0x%x, value=0x%lx\n", addr, value);
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return device->write_dcr(addr, value);
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}
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