minor updates
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@@ -310,7 +310,7 @@ module VX_lsu_unit #(
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`ifndef SYNTHESIS
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reg [`LSUQ_SIZE-1:0][(`NW_BITS + 32 + `NR_BITS + `UUID_BITS + 64 + 1)-1:0] pending_reqs;
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wire [63:0] delay_timeout = 10000 * (1 ** (`L2_ENABLE + `L3_ENABLE));
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wire [63:0] delay_timeout = 40000 * (1 ** (`L2_ENABLE + `L3_ENABLE));
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always @(posedge clk) begin
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if (reset) begin
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