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minor updates

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This commit is contained in:
Blaise Tine
2022-02-01 06:53:31 -05:00
parent e3e2609f7e
commit d48f1c1c5f
9 changed files with 25 additions and 180 deletions
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12
sim/rtlsim/Makefile
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@@ -54,16 +54,14 @@ VL_FLAGS += $(CONFIGS)
CXXFLAGS += $(CONFIGS)
# Enable Verilator multithreaded simulation
#THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))')
THREADS ?= $(shell python -c 'import multiprocessing as mp; print(mp.cpu_count())')
VL_FLAGS += -j $(THREADS)
#VL_FLAGS += --threads $(THREADS)
# Enable VCD trace
VCD_TRACE = -DVCD_OUTPUT
# Debugigng
ifdef DEBUG
VL_FLAGS += $(VCD_TRACE) --trace --trace-structs $(DBG_FLAGS)
CXXFLAGS += -g -O0 $(VCD_TRACE) $(DBG_FLAGS)
VL_FLAGS += --trace --trace-structs -DVCD_OUTPUT $(DBG_FLAGS)
CXXFLAGS += -g -O0 -DVCD_OUTPUT $(DBG_FLAGS)
else
VL_FLAGS += -DNDEBUG
CXXFLAGS += -O2 -DNDEBUG
@@ -83,8 +81,6 @@ VL_FLAGS += -DIDIV_DPI
FPU_CORE ?= FPU_DPI
VL_FLAGS += -D$(FPU_CORE)
THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))')
PROJECT = rtlsim
all: $(PROJECT)

10
sim/vlsim/Makefile
View File

@@ -51,16 +51,14 @@ VL_FLAGS += $(CONFIGS)
CXXFLAGS += $(CONFIGS)
# Enable Verilator multithreaded simulation
#THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))')
THREADS ?= $(shell python -c 'import multiprocessing as mp; print(mp.cpu_count())')
VL_FLAGS += -j $(THREADS)
#VL_FLAGS += --threads $(THREADS)
# Enable VCD trace
#VCD_TRACE = -DVCD_OUTPUT
# Debugigng
ifdef DEBUG
VL_FLAGS += $(VCD_TRACE) --trace --trace-structs $(DBG_FLAGS)
CXXFLAGS += -g -O0 $(VCD_TRACE) $(DBG_FLAGS)
VL_FLAGS += --trace --trace-structs -DVCD_OUTPUT $(DBG_FLAGS)
#CXXFLAGS += -g -O0 -DVCD_OUTPUT $(DBG_FLAGS)
else
VL_FLAGS += -DNDEBUG
CXXFLAGS += -O2 -DNDEBUG