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cache req datapath optimizations

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This commit is contained in:
Blaise Tine
2020-12-08 02:58:08 -08:00
parent 268ad15098
commit d5fa82f5e4
17 changed files with 393 additions and 410 deletions
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4
hw/rtl/libs/VX_cam_buffer.v
View File

@@ -52,9 +52,7 @@ module VX_cam_buffer #(
write_addr_r <= ADDRW'(1'b0);
end else begin
if (release_slot) begin
assert(0 == free_slots[release_addr]) else begin
$display("%t: releasing invalid slot at port %d", $time, release_addr);
end
assert(0 == free_slots[release_addr]) else $error("%t: releasing invalid slot at port %d", $time, release_addr);
end
free_slots <= free_slots_n;
write_addr_r <= free_index;

119
hw/rtl/libs/VX_stream_arbiter.v
View File

@@ -1,10 +1,11 @@
`include "VX_platform.vh"
module VX_stream_arbiter #(
parameter NUM_REQS = 1,
parameter DATAW = 1,
parameter TYPE = "R",
parameter BUFFERED = 0
parameter NUM_REQS = 1,
parameter DATAW = 1,
parameter TYPE = "R",
parameter IN_BUFFER = 0,
parameter OUT_BUFFER = 0
) (
input wire clk,
input wire reset,
@@ -17,18 +18,30 @@ module VX_stream_arbiter #(
output wire [DATAW-1:0] data_out,
input wire ready_out
);
localparam LOG_NUM_REQS = $clog2(NUM_REQS);
if (NUM_REQS == 1) begin
if (NUM_REQS > 1) begin
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
assign valid_out = valid_in;
assign data_out = data_in;
assign ready_in = ready_out;
wire [NUM_REQS-1:0] valid_in_qual;
wire [NUM_REQS-1:0][DATAW-1:0] data_in_qual;
wire [NUM_REQS-1:0] ready_in_qual;
end else begin
for (genvar i = 0; i < NUM_REQS; ++i) begin
VX_skid_buffer #(
.DATAW (DATAW),
.PASSTHRU (!IN_BUFFER)
) req_buffer (
.clk (clk),
.reset (reset),
.valid_in (valid_in[i]),
.data_in (data_in[i]),
.ready_in (ready_in[i]),
.valid_out (valid_in_qual[i]),
.data_out (data_in_qual[i]),
.ready_out (ready_in_qual[i])
);
end
wire sel_enable;
wire sel_valid;
@@ -41,13 +54,13 @@ module VX_stream_arbiter #(
.NUM_REQS(NUM_REQS),
.LOCK_ENABLE(1)
) sel_arb (
.clk (clk),
.reset (reset),
.requests (valid_in),
.enable (sel_enable),
.grant_valid (sel_valid),
.grant_index (sel_idx),
.grant_onehot(sel_1hot)
.clk (clk),
.reset (reset),
.requests (valid_in_qual),
.enable (sel_enable),
.grant_valid (sel_valid),
.grant_index (sel_idx),
.grant_onehot (sel_1hot)
);
end else if (TYPE == "R") begin
@@ -56,13 +69,13 @@ module VX_stream_arbiter #(
.NUM_REQS(NUM_REQS),
.LOCK_ENABLE(1)
) sel_arb (
.clk (clk),
.reset (reset),
.requests (valid_in),
.enable (sel_enable),
.grant_valid (sel_valid),
.grant_index (sel_idx),
.grant_onehot(sel_1hot)
.clk (clk),
.reset (reset),
.requests (valid_in_qual),
.enable (sel_enable),
.grant_valid (sel_valid),
.grant_index (sel_idx),
.grant_onehot (sel_1hot)
);
end else if (TYPE == "F") begin
@@ -71,13 +84,13 @@ module VX_stream_arbiter #(
.NUM_REQS(NUM_REQS),
.LOCK_ENABLE(1)
) sel_arb (
.clk (clk),
.reset (reset),
.requests (valid_in),
.enable (sel_enable),
.grant_valid (sel_valid),
.grant_index (sel_idx),
.grant_onehot(sel_1hot)
.clk (clk),
.reset (reset),
.requests (valid_in_qual),
.enable (sel_enable),
.grant_valid (sel_valid),
.grant_index (sel_idx),
.grant_onehot (sel_1hot)
);
end else if (TYPE == "M") begin
@@ -86,18 +99,18 @@ module VX_stream_arbiter #(
.NUM_REQS(NUM_REQS),
.LOCK_ENABLE(1)
) sel_arb (
.clk (clk),
.reset (reset),
.requests (valid_in),
.enable (sel_enable),
.grant_valid (sel_valid),
.grant_index (sel_idx),
.grant_onehot(sel_1hot)
.clk (clk),
.reset (reset),
.requests (valid_in_qual),
.enable (sel_enable),
.grant_valid (sel_valid),
.grant_index (sel_idx),
.grant_onehot (sel_1hot)
);
end
if (BUFFERED) begin
if (OUT_BUFFER) begin
wire stall = ~ready_out && valid_out;
assign sel_enable = ~stall;
@@ -110,25 +123,35 @@ module VX_stream_arbiter #(
.reset (reset),
.stall (stall),
.flush (1'b0),
.data_in ({sel_valid, data_in[sel_idx]}),
.data_in ({sel_valid, data_in_qual[sel_idx]}),
.data_out ({valid_out, data_out})
);
for (genvar i = 0; i < NUM_REQS; i++) begin
assign ready_in[i] = sel_1hot[i] && ~stall;
assign ready_in_qual[i] = sel_1hot[i] && ~stall;
end
end else begin
assign sel_enable = ready_out;
assign valid_out = sel_valid;
assign data_out = data_in_qual[sel_idx];
assign valid_out = sel_valid;
assign data_out = data_in[sel_idx];
for (genvar i = 0; i < NUM_REQS; i++) begin
assign ready_in[i] = sel_1hot[i] && ready_out;
assign ready_in_qual[i] = sel_1hot[i] && ready_out;
end
end
end
end else begin
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
assign valid_out = valid_in;
assign data_out = data_in;
assign ready_in = ready_out;
end
endmodule