scope refactoring + snoop invalidate
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@@ -6,7 +6,6 @@ module VX_pipeline #(
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`SCOPE_SIGNALS_ICACHE_IO
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`SCOPE_SIGNALS_DCACHE_IO
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`SCOPE_SIGNALS_CORE_IO
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`SCOPE_SIGNALS_FE_IO
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`SCOPE_SIGNALS_BE_IO
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// Clock
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@@ -57,26 +56,6 @@ module VX_pipeline #(
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wire gpr_stage_delay;
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wire schedule_delay;
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`SCOPE_ASSIGN(scope_icache_req_valid, icache_req_valid);
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`SCOPE_ASSIGN(scope_icache_req_addr, {icache_req_addr, 2'b0});
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`SCOPE_ASSIGN(scope_icache_req_tag, icache_req_tag);
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`SCOPE_ASSIGN(scope_icache_req_ready, icache_req_ready);
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`SCOPE_ASSIGN(scope_icache_rsp_valid, icache_rsp_valid);
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`SCOPE_ASSIGN(scope_icache_rsp_data, icache_rsp_data);
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`SCOPE_ASSIGN(scope_icache_rsp_tag, icache_rsp_tag);
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`SCOPE_ASSIGN(scope_icache_rsp_ready, icache_rsp_ready);
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`SCOPE_ASSIGN(scope_dcache_req_valid, dcache_req_valid);
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`SCOPE_ASSIGN(scope_dcache_req_addr, {dcache_req_addr[0], 2'b0});
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`SCOPE_ASSIGN(scope_dcache_req_tag, dcache_req_tag);
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`SCOPE_ASSIGN(scope_dcache_req_ready, dcache_req_ready);
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`SCOPE_ASSIGN(scope_dcache_rsp_valid, dcache_rsp_valid);
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`SCOPE_ASSIGN(scope_dcache_rsp_data, dcache_rsp_data[0]);
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`SCOPE_ASSIGN(scope_dcache_rsp_tag, dcache_rsp_tag);
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`SCOPE_ASSIGN(scope_dcache_rsp_ready, dcache_rsp_ready);
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`SCOPE_ASSIGN(scope_schedule_delay, schedule_delay);
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// Dcache
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VX_cache_core_req_if #(
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.NUM_REQUESTS(`NUM_THREADS),
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@@ -121,7 +100,8 @@ module VX_pipeline #(
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VX_front_end #(
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.CORE_ID(CORE_ID)
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) front_end (
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`SCOPE_SIGNALS_FE_ATTACH
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`SCOPE_SIGNALS_ICACHE_ATTACH
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.clk (clk),
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.reset (reset),
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.warp_ctl_if (warp_ctl_if),
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@@ -149,7 +129,9 @@ module VX_pipeline #(
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VX_back_end #(
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.CORE_ID(CORE_ID)
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) back_end (
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`SCOPE_SIGNALS_DCACHE_ATTACH
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`SCOPE_SIGNALS_BE_ATTACH
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.clk (clk),
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.reset (reset),
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.schedule_delay (schedule_delay),
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@@ -192,4 +174,17 @@ module VX_pipeline #(
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assign core_icache_rsp_if.core_rsp_tag = icache_rsp_tag;
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assign icache_rsp_ready = core_icache_rsp_if.core_rsp_ready;
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`SCOPE_ASSIGN(scope_schedule_delay, schedule_delay);
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`SCOPE_ASSIGN(scope_memory_delay, memory_delay);
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`SCOPE_ASSIGN(scope_exec_delay, exec_delay);
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`SCOPE_ASSIGN(scope_gpr_stage_delay, gpr_stage_delay);
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`ifdef DBG_PRINT_WB
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always_ff @(posedge clk) begin
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if ((| writeback_if.valid) && (writeback_if.wb != 0)) begin
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$display("%t: Writeback: wid=%0d, rd=%0d, data=%0h", $time, writeback_if.warp_num, writeback_if.rd, writeback_if.data);
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end
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end
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`endif
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endmodule // Vortex
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