From d81e4085e2f6c298fe626f5f302c8eaebc89f590 Mon Sep 17 00:00:00 2001
From: Hansung Kim <hansung_kim@berkeley.edu>
Date: Fri, 17 Feb 2023 17:59:56 -0800
Subject: [PATCH] simx: add thread ID and vlen to load/store memory debug trace

---
 sim/simx/core.cpp      |  2 +-
 sim/simx/execute.cpp   | 10 +++++-----
 sim/simx/processor.cpp |  2 +-
 3 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/sim/simx/core.cpp b/sim/simx/core.cpp
index 8314a31d..ff1e90f8 100644
--- a/sim/simx/core.cpp
+++ b/sim/simx/core.cpp
@@ -683,4 +683,4 @@ bool Core::check_exit() const {
 bool Core::running() const {
   bool is_running = (committed_instrs_ != issued_instrs_);
   return is_running;
-}
\ No newline at end of file
+}
diff --git a/sim/simx/execute.cpp b/sim/simx/execute.cpp
index 7ad257e8..fee169ba 100644
--- a/sim/simx/execute.cpp
+++ b/sim/simx/execute.cpp
@@ -691,7 +691,7 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
         uint64_t mem_data = 0;
         core_->dcache_read(&mem_data, mem_addr, mem_bytes);
         trace->mem_addrs.at(t).push_back({mem_addr, mem_bytes});        
-        DP(4, "LOAD MEM: ADDRESS=0x" << std::hex << mem_addr << ", DATA=0x" << mem_data);
+        DP(4, "LOAD MEM: THREAD=" << t << ", ADDRESS=0x" << std::hex << mem_addr << ", DATA=0x" << mem_data << std::dec << ", BYTES=" << mem_bytes);
         switch (func3) {
         case 0:
           // RV32I: LB
@@ -731,7 +731,7 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
           core_->dcache_read(&mem_data, mem_addr, 4);
           Word *result_ptr = (Word *)(vd.data() + i);
           *result_ptr = mem_data;
-          DP(4, "LOAD MEM: ADDRESS=0x" << std::hex << mem_addr << ", DATA=0x" << mem_data);        
+          DP(4, "LOAD MEM: VLEN=" << vl_ << ", VID=" << i << ", ADDRESS=0x" << std::hex << mem_addr << ", DATA=0x" << mem_data << std::dec << ", BYTES=" << 4);        
         }
         break;
       } 
@@ -762,7 +762,7 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
           mem_data &= mask;
         }
         trace->mem_addrs.at(t).push_back({mem_addr, mem_bytes});        
-        DP(4, "STORE MEM: ADDRESS=0x" << std::hex << mem_addr << ", DATA=0x" << mem_data);
+        DP(4, "STORE MEM: THREAD=" << t << ", ADDRESS=0x" << std::hex << mem_addr << ", DATA=0x" << mem_data << std::dec << ", BYTES=" << mem_bytes);
         switch (func3) {
         case 0:
         case 1:
@@ -782,7 +782,7 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
           // store word and unit strided (not checking for unit stride)          
           uint32_t mem_data = *(uint32_t *)(vreg_file_.at(instr.getVs3()).data() + i);
           core_->dcache_write(&mem_data, mem_addr, 4);
-          DP(4, "STORE MEM: ADDRESS=0x" << std::hex << mem_addr << ", DATA=0x" << mem_data);
+          DP(4, "STORE MEM: VLEN=" << vl_ << ", VID=" << i << ", ADDRESS=0x" << std::hex << mem_addr << ", DATA=0x" << mem_data << std::dec << ", BYTES=" << 4);
           break;
         } 
         default:
@@ -2349,4 +2349,4 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
     DP(3, "*** Next PC: " << std::hex << nextPC << std::dec);
     PC_ = nextPC;
   }
-}
\ No newline at end of file
+}
diff --git a/sim/simx/processor.cpp b/sim/simx/processor.cpp
index a7314687..9dac7cc3 100644
--- a/sim/simx/processor.cpp
+++ b/sim/simx/processor.cpp
@@ -175,4 +175,4 @@ void Processor::attach_ram(RAM* mem) {
 
 int Processor::run() {
   return impl_->run();
-}
\ No newline at end of file
+}