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This commit is contained in:
Blaise Tine
2020-04-21 03:19:47 -04:00
parent 43a8bf4326
commit d85c0af5d6
75 changed files with 4388 additions and 4382 deletions
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24
hw/rtl/libs/VX_countones.v
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@@ -1,18 +1,18 @@
module VX_countones #(
parameter N = 10
parameter N = 10
) (
input wire[N-1:0] valids,
output reg[$clog2(N):0] count
input wire[N-1:0] valids,
output reg[$clog2(N):0] count
);
integer i;
always @(*) begin
count = 0;
for (i = N-1; i >= 0; i = i - 1) begin
if (valids[i]) begin
count = count + 1;
end
end
end
integer i;
always @(*) begin
count = 0;
for (i = N-1; i >= 0; i = i - 1) begin
if (valids[i]) begin
count = count + 1;
end
end
end
endmodule

34
hw/rtl/libs/VX_generic_priority_encoder.v
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@@ -1,26 +1,26 @@
`include "VX_define.vh"
module VX_generic_priority_encoder #(
parameter N = 1
parameter N = 1
) (
input wire[N-1:0] valids,
input wire[N-1:0] valids,
//output reg[$clog2(N)-1:0] index,
output reg[(`LOG2UP(N))-1:0] index,
output reg[(`LOG2UP(N))-1:0] index,
//output reg[`LOG2UP(N):0] index, // eh
output reg found
output reg found
);
integer i;
always @(*) begin
index = 0;
found = 0;
for (i = N-1; i >= 0; i = i - 1) begin
if (valids[i]) begin
//index = i[$clog2(N)-1:0];
index = i[(`LOG2UP(N))-1:0];
found = 1;
end
end
end
integer i;
always @(*) begin
index = 0;
found = 0;
for (i = N-1; i >= 0; i = i - 1) begin
if (valids[i]) begin
//index = i[$clog2(N)-1:0];
index = i[(`LOG2UP(N))-1:0];
found = 1;
end
end
end
endmodule

14
hw/rtl/libs/VX_generic_queue.v
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@@ -5,15 +5,15 @@ module VX_generic_queue #(
parameter SIZE = 16
) (
`IGNORE_WARNINGS_BEGIN
input wire clk,
input wire reset,
input wire push,
input wire clk,
input wire reset,
input wire push,
input wire pop,
output wire empty,
output wire full,
`IGNORE_WARNINGS_END
output wire empty,
output wire full,
`IGNORE_WARNINGS_END
input wire [DATAW-1:0] data_in,
output wire [DATAW-1:0] data_out
output wire [DATAW-1:0] data_out
);
if (SIZE == 0) begin

46
hw/rtl/libs/VX_generic_register.v
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@@ -1,36 +1,36 @@
`include "VX_define.vh"
module VX_generic_register #(
parameter N,
parameter PassThru = 0
parameter N,
parameter PassThru = 0
) (
`IGNORE_WARNINGS_BEGIN
input wire clk,
input wire reset,
input wire stall,
input wire flush,
input wire clk,
input wire reset,
input wire stall,
input wire flush,
`IGNORE_WARNINGS_END
input wire[N-1:0] in,
output wire[N-1:0] out
input wire[N-1:0] in,
output wire[N-1:0] out
);
if (PassThru) begin
assign out = in;
end else begin
if (PassThru) begin
assign out = in;
end else begin
reg [(N-1):0] value;
reg [(N-1):0] value;
always @(posedge clk) begin
if (reset) begin
value <= 0;
end else if (flush) begin
value <= 0;
end else if (~stall) begin
value <= in;
end
end
always @(posedge clk) begin
if (reset) begin
value <= 0;
end else if (flush) begin
value <= 0;
end else if (~stall) begin
value <= in;
end
end
assign out = value;
end
assign out = value;
end
endmodule

52
hw/rtl/libs/VX_generic_stack.v
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@@ -1,34 +1,34 @@
module VX_generic_stack #(
parameter WIDTH = 40,
parameter DEPTH = 2
module VX_generic_stack #(
parameter WIDTH = 40,
parameter DEPTH = 2
) (
input wire clk,
input wire reset,
input wire push,
input wire pop,
input reg [WIDTH - 1:0] q1,
input reg [WIDTH - 1:0] q2,
output wire[WIDTH - 1:0] d
input wire clk,
input wire reset,
input wire push,
input wire pop,
input reg [WIDTH - 1:0] q1,
input reg [WIDTH - 1:0] q2,
output wire[WIDTH - 1:0] d
);
reg [DEPTH - 1:0] ptr;
reg [WIDTH - 1:0] stack [0:(1 << DEPTH) - 1];
reg [DEPTH - 1:0] ptr;
reg [WIDTH - 1:0] stack [0:(1 << DEPTH) - 1];
integer i;
always @(posedge clk) begin
if (reset) begin
ptr <= 0;
for (i = 0; i < (1 << DEPTH); i=i+1) stack[i] <= 0;
end else if (push) begin
stack[ptr] <= q1;
stack[ptr+1] <= q2;
ptr <= ptr + 2;
end else if (pop) begin
ptr <= ptr - 1;
end
end
integer i;
always @(posedge clk) begin
if (reset) begin
ptr <= 0;
for (i = 0; i < (1 << DEPTH); i=i+1) stack[i] <= 0;
end else if (push) begin
stack[ptr] <= q1;
stack[ptr+1] <= q2;
ptr <= ptr + 2;
end else if (pop) begin
ptr <= ptr - 1;
end
end
assign d = stack[ptr - 1];
assign d = stack[ptr - 1];
endmodule

8
hw/rtl/libs/VX_mult.v
View File

@@ -9,10 +9,12 @@ module VX_mult #(
parameter PIPELINE=0,
parameter FORCE_LE="NO"
) (
input clock, aclr, clken,
input clock;
input aclr;
input clken;
input [WIDTHA-1:0] dataa,
input [WIDTHB-1:0] datab,
input [WIDTHA-1:0] dataa,
input [WIDTHB-1:0] datab,
output reg [WIDTHP-1:0] result
);

40
hw/rtl/libs/VX_priority_encoder.v
View File

@@ -1,28 +1,28 @@
`include "VX_define.vh"
module VX_priority_encoder #(
parameter N
parameter N
) (
input wire [N-1:0] valids,
output wire [`LOG2UP(N)-1:0] index,
output wire found
input wire [N-1:0] valids,
output wire [`LOG2UP(N)-1:0] index,
output wire found
);
reg [`LOG2UP(N)-1:0] index_r;
reg found_r;
reg [`LOG2UP(N)-1:0] index_r;
reg found_r;
integer i;
always @(*) begin
index_r = 0;
found_r = 0;
for (i = `NUM_WARPS-1; i >= 0; i = i - 1) begin
if (valids[i]) begin
index_r = i[`NW_BITS-1:0];
found_r = 1;
end
end
end
integer i;
always @(*) begin
index_r = 0;
found_r = 0;
for (i = `NUM_WARPS-1; i >= 0; i = i - 1) begin
if (valids[i]) begin
index_r = i[`NW_BITS-1:0];
found_r = 1;
end
end
end
assign index = index_r;
assign found = found_r;
assign index = index_r;
assign found = found_r;
endmodule

44
hw/rtl/libs/VX_priority_encoder_w_mask.v
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@@ -1,32 +1,32 @@
`include "VX_define.vh"
module VX_priority_encoder_w_mask #(
parameter N = 10
parameter N = 10
) (
input wire[N-1:0] valids,
output reg [N-1:0] mask,
input wire[N-1:0] valids,
output reg [N-1:0] mask,
//output reg[$clog2(N)-1:0] index,
output reg[(`LOG2UP(N))-1:0] index,
output reg[(`LOG2UP(N))-1:0] index,
//output reg[`LOG2UP(N):0] index, // eh
output reg found
output reg found
);
integer i;
always @(valids) begin
index = 0;
found = 0;
// mask = 0;
for (i = 0; i < N; i=i+1) begin
if (valids[i]) begin
//index = i[$clog2(N)-1:0];
index = i[(`LOG2UP(N))-1:0];
found = 1;
// mask[index] = (1 << i);
// $display("%h",(1 << i));
end
end
end
integer i;
always @(valids) begin
index = 0;
found = 0;
// mask = 0;
for (i = 0; i < N; i=i+1) begin
if (valids[i]) begin
//index = i[$clog2(N)-1:0];
index = i[(`LOG2UP(N))-1:0];
found = 1;
// mask[index] = (1 << i);
// $display("%h",(1 << i));
end
end
end
assign mask = found ? (1 << index) : 0;
assign mask = found ? (1 << index) : 0;
endmodule