From db11bf699040dcc2ba878fa2f1db1fc8a619ae63 Mon Sep 17 00:00:00 2001 From: felsabbagh3 Date: Sat, 7 Mar 2020 00:49:40 -0800 Subject: [PATCH] Made the cache module configurable for multi-instantiation --- rtl/VX_back_end.v | 8 +- rtl/VX_cache/VX_bank.v | 200 ++++++++++++--- rtl/VX_cache/VX_cache.v | 227 ++++++++++++++---- rtl/VX_cache/VX_cache_config.v | 58 +---- rtl/VX_cache/VX_cache_core_req_bank_sel.v | 56 ++++- rtl/VX_cache/VX_cache_dfq_queue.v | 67 +++++- rtl/VX_cache/VX_cache_dram_req_arb.v | 68 +++++- rtl/VX_cache/VX_cache_miss_resrv.v | 164 ++++++++----- rtl/VX_cache/VX_cache_req_queue.v | 82 +++++-- rtl/VX_cache/VX_cache_wb_sel_merge.v | 78 ++++-- rtl/VX_cache/VX_dcache_llv_resp_bank_sel.v | 66 ++++- rtl/VX_cache/VX_fill_invalidator.v | 106 +++++--- rtl/VX_cache/VX_tag_data_access.v | 99 ++++++-- rtl/VX_cache/VX_tag_data_structure.v | 46 +++- rtl/VX_define.v | 115 ++++----- rtl/VX_dmem_controller.v | 33 ++- rtl/VX_generic_queue_ll.v | 168 +++++++------ rtl/Vortex.v | 23 +- rtl/interfaces/VX_gpu_dcache_dram_req_inter.v | 8 +- rtl/interfaces/VX_gpu_dcache_dram_res_inter.v | 8 +- rtl/interfaces/VX_gpu_dcache_req_inter.v | 12 +- rtl/interfaces/VX_gpu_dcache_res_inter.v | 10 +- 22 files changed, 1209 insertions(+), 493 deletions(-) diff --git a/rtl/VX_back_end.v b/rtl/VX_back_end.v index 9b51e9ed..fdbcfd5f 100644 --- a/rtl/VX_back_end.v +++ b/rtl/VX_back_end.v @@ -5,6 +5,9 @@ module VX_back_end ( input wire reset, input wire schedule_delay, + VX_gpu_dcache_res_inter VX_dcache_rsp, + VX_gpu_dcache_req_inter VX_dcache_req, + output wire out_mem_delay, output wire out_exec_delay, output wire gpr_stage_delay, @@ -14,10 +17,7 @@ module VX_back_end ( VX_frE_to_bckE_req_inter VX_bckE_req, VX_wb_inter VX_writeback_inter, - VX_warp_ctl_inter VX_warp_ctl, - - VX_gpu_dcache_res_inter VX_dcache_rsp, - VX_gpu_dcache_req_inter VX_dcache_req + VX_warp_ctl_inter VX_warp_ctl ); diff --git a/rtl/VX_cache/VX_bank.v b/rtl/VX_cache/VX_bank.v index f1d3a354..6e1468f6 100644 --- a/rtl/VX_cache/VX_bank.v +++ b/rtl/VX_cache/VX_bank.v @@ -1,14 +1,58 @@ `include "VX_cache_config.v" -module VX_bank ( +module VX_bank + #( + // Size of cache in bytes + parameter CACHE_SIZE_BYTES = 1024, + // Size of line inside a bank in bytes + parameter BANK_LINE_SIZE_BYTES = 16, + // Number of banks {1, 2, 4, 8,...} + parameter NUMBER_BANKS = 8, + // Size of a word in bytes + parameter WORD_SIZE_BYTES = 4, + // Number of Word requests per cycle {1, 2, 4, 8, ...} + parameter NUMBER_REQUESTS = 2, + // Number of cycles to complete stage 1 (read from memory) + parameter STAGE_1_CYCLES = 2, + +// Queues feeding into banks Knobs {1, 2, 4, 8, ...} + + // Core Request Queue Size + parameter REQQ_SIZE = 8, + // Miss Reserv Queue Knob + parameter MRVQ_SIZE = 8, + // Dram Fill Rsp Queue Size + parameter DFPQ_SIZE = 2, + // Snoop Req Queue + parameter SNRQ_SIZE = 8, + +// Queues for writebacks Knobs {1, 2, 4, 8, ...} + // Core Writeback Queue Size + parameter CWBQ_SIZE = 8, + // Dram Writeback Queue Size + parameter DWBQ_SIZE = 4, + // Dram Fill Req Queue Size + parameter DFQQ_SIZE = 8, + // Lower Level Cache Hit Queue Size + parameter LLVQ_SIZE = 16, + + // Fill Invalidator Size {Fill invalidator must be active} + parameter FILL_INVALIDAOR_SIZE = 16, + +// Dram knobs + parameter SIMULATED_DRAM_LATENCY_CYCLES = 10 + + + ) + ( input wire clk, input wire reset, // Input Core Request input wire delay_req, - input wire [`NUMBER_REQUESTS-1:0] bank_valids, - input wire [`NUMBER_REQUESTS-1:0][31:0] bank_addr, - input wire [`NUMBER_REQUESTS-1:0][31:0] bank_writedata, + input wire [NUMBER_REQUESTS-1:0] bank_valids, + input wire [NUMBER_REQUESTS-1:0][31:0] bank_addr, + input wire [NUMBER_REQUESTS-1:0][31:0] bank_writedata, input wire [4:0] bank_rd, input wire [1:0] bank_wb, input wire [`NW_M1:0] bank_warp_num, @@ -19,7 +63,7 @@ module VX_bank ( // Output Core WB input wire bank_wb_pop, output wire bank_wb_valid, - output wire [`vx_clog2(`NUMBER_REQUESTS)-1:0] bank_wb_tid, + output wire [`vx_clog2(NUMBER_REQUESTS)-1:0] bank_wb_tid, output wire [4:0] bank_wb_rd, output wire [1:0] bank_wb_wb, output wire [`NW_M1:0] bank_wb_warp_num, @@ -53,7 +97,7 @@ module VX_bank ( output wire llvq_valid, output wire[31:0] llvq_res_addr, output wire[`BANK_LINE_SIZE_RNG][31:0] llvq_res_data, - output wire[`vx_clog2(`NUMBER_REQUESTS)-1:0] llvq_res_tid + output wire[`vx_clog2(NUMBER_REQUESTS)-1:0] llvq_res_tid ); @@ -69,7 +113,7 @@ module VX_bank ( reg snrq_hazard_st0; assign snrq_valid_st0 = !snrq_empty; - VX_generic_queue_ll #(.DATAW(32), .SIZE(`SNRQ_SIZE)) snr_queue( + VX_generic_queue_ll #(.DATAW(32), .SIZE(SNRQ_SIZE)) snr_queue( .clk (clk), .reset (reset), .push (snp_req), @@ -89,7 +133,7 @@ module VX_bank ( assign dram_fill_accept = !dfpq_full; - VX_generic_queue_ll #(.DATAW(32+(`BANK_LINE_SIZE_WORDS*32)), .SIZE(`DFPQ_SIZE)) dfp_queue( + VX_generic_queue_ll #(.DATAW(32+(`BANK_LINE_SIZE_WORDS*32)), .SIZE(DFPQ_SIZE)) dfp_queue( .clk (clk), .reset (reset), .push (dram_fill_rsp), @@ -105,7 +149,7 @@ module VX_bank ( wire reqq_push; wire reqq_empty; wire reqq_req_st0; - wire[`vx_clog2(`NUMBER_REQUESTS)-1:0] reqq_req_tid_st0; + wire[`vx_clog2(NUMBER_REQUESTS)-1:0] reqq_req_tid_st0; wire [31:0] reqq_req_addr_st0; wire [31:0] reqq_req_writeword_st0; wire [4:0] reqq_req_rd_st0; @@ -117,7 +161,26 @@ module VX_bank ( assign reqq_push = !delay_req && (|bank_valids); - VX_cache_req_queue req_queue( + VX_cache_req_queue #( + .CACHE_SIZE_BYTES (CACHE_SIZE_BYTES), + .BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES), + .NUMBER_BANKS (NUMBER_BANKS), + .WORD_SIZE_BYTES (WORD_SIZE_BYTES), + .NUMBER_REQUESTS (NUMBER_REQUESTS), + .STAGE_1_CYCLES (STAGE_1_CYCLES), + .REQQ_SIZE (REQQ_SIZE), + .MRVQ_SIZE (MRVQ_SIZE), + .DFPQ_SIZE (DFPQ_SIZE), + .SNRQ_SIZE (SNRQ_SIZE), + .CWBQ_SIZE (CWBQ_SIZE), + .DWBQ_SIZE (DWBQ_SIZE), + .DFQQ_SIZE (DFQQ_SIZE), + .LLVQ_SIZE (LLVQ_SIZE), + .FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE), + .SIMULATED_DRAM_LATENCY_CYCLES(SIMULATED_DRAM_LATENCY_CYCLES) + ) + req_queue + ( .clk (clk), .reset (reset), // Enqueue @@ -149,7 +212,7 @@ module VX_bank ( wire mrvq_pop; wire mrvq_full; wire mrvq_valid_st0; - wire[`vx_clog2(`NUMBER_REQUESTS)-1:0] mrvq_tid_st0; + wire[`vx_clog2(NUMBER_REQUESTS)-1:0] mrvq_tid_st0; wire [31:0] mrvq_addr_st0; wire [31:0] mrvq_writeword_st0; wire [4:0] mrvq_rd_st0; @@ -162,14 +225,33 @@ module VX_bank ( wire miss_add; wire[31:0] miss_add_addr; wire[31:0] miss_add_data; - wire[`vx_clog2(`NUMBER_REQUESTS)-1:0] miss_add_tid; + wire[`vx_clog2(NUMBER_REQUESTS)-1:0] miss_add_tid; wire[4:0] miss_add_rd; wire[1:0] miss_add_wb; wire[`NW_M1:0] miss_add_warp_num; wire[2:0] miss_add_mem_read; wire[2:0] miss_add_mem_write; - VX_cache_miss_resrv mrvq_queue( + VX_cache_miss_resrv #( + .CACHE_SIZE_BYTES (CACHE_SIZE_BYTES), + .BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES), + .NUMBER_BANKS (NUMBER_BANKS), + .WORD_SIZE_BYTES (WORD_SIZE_BYTES), + .NUMBER_REQUESTS (NUMBER_REQUESTS), + .STAGE_1_CYCLES (STAGE_1_CYCLES), + .REQQ_SIZE (REQQ_SIZE), + .MRVQ_SIZE (MRVQ_SIZE), + .DFPQ_SIZE (DFPQ_SIZE), + .SNRQ_SIZE (SNRQ_SIZE), + .CWBQ_SIZE (CWBQ_SIZE), + .DWBQ_SIZE (DWBQ_SIZE), + .DFQQ_SIZE (DFQQ_SIZE), + .LLVQ_SIZE (LLVQ_SIZE), + .FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE), + .SIMULATED_DRAM_LATENCY_CYCLES(SIMULATED_DRAM_LATENCY_CYCLES) + ) + mrvq_queue + ( .clk (clk), .reset (reset), // Enqueue @@ -217,7 +299,7 @@ module VX_bank ( mrvq_hazard_st0 = 0; reqq_hazard_st0 = 0; snrq_hazard_st0 = 0; - for (st1_cycle = 0; st1_cycle < `STAGE_1_CYCLES; st1_cycle = st1_cycle + 1) begin + for (st1_cycle = 0; st1_cycle < STAGE_1_CYCLES; st1_cycle = st1_cycle + 1) begin if (valid_st1[st1_cycle] && going_to_write_st1[st1_cycle]) begin if (dfpq_addr_st0 [31:`LINE_SELECT_ADDR_START] == addr_st1[st1_cycle][31:`LINE_SELECT_ADDR_START]) dfpq_hazard_st0 = 1; if (mrvq_addr_st0 [31:`LINE_SELECT_ADDR_START] == addr_st1[st1_cycle][31:`LINE_SELECT_ADDR_START]) mrvq_hazard_st0 = 1; @@ -239,14 +321,14 @@ module VX_bank ( wire qual_going_to_write_st0; wire qual_is_snp; - wire valid_st1 [`STAGE_1_CYCLES-1:0]; - wire going_to_write_st1[`STAGE_1_CYCLES-1:0]; - wire [31:0] addr_st1 [`STAGE_1_CYCLES-1:0]; - wire [31:0] writeword_st1 [`STAGE_1_CYCLES-1:0]; - wire [`REQ_INST_META_SIZE-1:0] inst_meta_st1 [`STAGE_1_CYCLES-1:0]; - wire is_fill_st1 [`STAGE_1_CYCLES-1:0]; - wire [`BANK_LINE_SIZE_RNG][31:0] writedata_st1 [`STAGE_1_CYCLES-1:0]; - wire is_snp_st1 [`STAGE_1_CYCLES-1:0]; + wire valid_st1 [STAGE_1_CYCLES-1:0]; + wire going_to_write_st1[STAGE_1_CYCLES-1:0]; + wire [31:0] addr_st1 [STAGE_1_CYCLES-1:0]; + wire [31:0] writeword_st1 [STAGE_1_CYCLES-1:0]; + wire [`REQ_INST_META_SIZE-1:0] inst_meta_st1 [STAGE_1_CYCLES-1:0]; + wire is_fill_st1 [STAGE_1_CYCLES-1:0]; + wire [`BANK_LINE_SIZE_RNG][31:0] writedata_st1 [STAGE_1_CYCLES-1:0]; + wire is_snp_st1 [STAGE_1_CYCLES-1:0]; assign qual_is_fill_st0 = dfpq_pop; assign qual_valid_st0 = dfpq_pop || mrvq_pop || reqq_pop || snrq_pop; @@ -286,7 +368,7 @@ module VX_bank ( genvar curr_stage; generate - for (curr_stage = 1; curr_stage < `STAGE_1_CYCLES; curr_stage = curr_stage + 1) begin + for (curr_stage = 1; curr_stage < STAGE_1_CYCLES; curr_stage = curr_stage + 1) begin VX_generic_register #(.N( 1 + 1 + 1 + 32 + 32 + `REQ_INST_META_SIZE + (`BANK_LINE_SIZE_WORDS*32) + 1)) s0_1_cc ( .clk (clk), .reset(reset), @@ -311,16 +393,35 @@ module VX_bank ( wire [`NW_M1:0] warp_num_st1e; wire [2:0] mem_read_st1e; wire [2:0] mem_write_st1e; - wire [`vx_clog2(`NUMBER_REQUESTS)-1:0] tid_st1e; + wire [`vx_clog2(NUMBER_REQUESTS)-1:0] tid_st1e; wire fill_saw_dirty_st1e; wire is_snp_st1e; - assign is_snp_st1e = is_snp_st1[`STAGE_1_CYCLES-1]; + assign is_snp_st1e = is_snp_st1[STAGE_1_CYCLES-1]; - assign {rd_st1e, wb_st1e, warp_num_st1e, mem_read_st1e, mem_write_st1e, tid_st1e} = inst_meta_st1[`STAGE_1_CYCLES-1]; + assign {rd_st1e, wb_st1e, warp_num_st1e, mem_read_st1e, mem_write_st1e, tid_st1e} = inst_meta_st1[STAGE_1_CYCLES-1]; - VX_tag_data_access VX_tag_data_access( + VX_tag_data_access #( + .CACHE_SIZE_BYTES (CACHE_SIZE_BYTES), + .BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES), + .NUMBER_BANKS (NUMBER_BANKS), + .WORD_SIZE_BYTES (WORD_SIZE_BYTES), + .NUMBER_REQUESTS (NUMBER_REQUESTS), + .STAGE_1_CYCLES (STAGE_1_CYCLES), + .REQQ_SIZE (REQQ_SIZE), + .MRVQ_SIZE (MRVQ_SIZE), + .DFPQ_SIZE (DFPQ_SIZE), + .SNRQ_SIZE (SNRQ_SIZE), + .CWBQ_SIZE (CWBQ_SIZE), + .DWBQ_SIZE (DWBQ_SIZE), + .DFQQ_SIZE (DFQQ_SIZE), + .LLVQ_SIZE (LLVQ_SIZE), + .FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE), + .SIMULATED_DRAM_LATENCY_CYCLES(SIMULATED_DRAM_LATENCY_CYCLES) + ) + VX_tag_data_access + ( .clk (clk), .reset (reset), .stall (stall_bank_pipe), @@ -329,11 +430,11 @@ module VX_bank ( .readaddr_st10 (addr_st1[0]), // Actual Read/Write - .valid_req_st1e(valid_st1[`STAGE_1_CYCLES-1]), - .writefill_st1e(is_fill_st1[`STAGE_1_CYCLES-1]), - .writeaddr_st1e(addr_st1[`STAGE_1_CYCLES-1]), - .writeword_st1e(writeword_st1[`STAGE_1_CYCLES-1]), - .writedata_st1e(writedata_st1[`STAGE_1_CYCLES-1]), + .valid_req_st1e(valid_st1[STAGE_1_CYCLES-1]), + .writefill_st1e(is_fill_st1[STAGE_1_CYCLES-1]), + .writeaddr_st1e(addr_st1[STAGE_1_CYCLES-1]), + .writeword_st1e(writeword_st1[STAGE_1_CYCLES-1]), + .writedata_st1e(writedata_st1[STAGE_1_CYCLES-1]), .mem_write_st1e(mem_write_st1e), .mem_read_st1e (mem_read_st1e), @@ -349,7 +450,7 @@ module VX_bank ( .fill_saw_dirty_st1e(fill_saw_dirty_st1e) ); - wire qual_valid_st1e_2 = valid_st1[`STAGE_1_CYCLES-1] && !is_fill_st1[`STAGE_1_CYCLES-1]; + wire qual_valid_st1e_2 = valid_st1[STAGE_1_CYCLES-1] && !is_fill_st1[STAGE_1_CYCLES-1]; wire valid_st2; wire[31:0] addr_st2; @@ -369,7 +470,7 @@ module VX_bank ( .reset(reset), .stall(stall_bank_pipe), .flush(0), - .in ({is_snp_st1e, fill_saw_dirty_st1e, is_fill_st1[`STAGE_1_CYCLES-1], qual_valid_st1e_2, addr_st1[`STAGE_1_CYCLES-1], writeword_st1[`STAGE_1_CYCLES-1], readword_st1e, readdata_st1e, readtag_st1e, miss_st1e, dirty_st1e, inst_meta_st1[`STAGE_1_CYCLES-1]}), + .in ({is_snp_st1e, fill_saw_dirty_st1e, is_fill_st1[STAGE_1_CYCLES-1], qual_valid_st1e_2, addr_st1[STAGE_1_CYCLES-1], writeword_st1[STAGE_1_CYCLES-1], readword_st1e, readdata_st1e, readtag_st1e, miss_st1e, dirty_st1e, inst_meta_st1[STAGE_1_CYCLES-1]}), .out ({is_snp_st2 , fill_saw_dirty_st2 , is_fill_st2 , valid_st2 , addr_st2 , writeword_st2 , readword_st2 , readdata_st2 , readtag_st2 , miss_st2 , dirty_st2 , inst_meta_st2 }) ); @@ -384,7 +485,7 @@ module VX_bank ( // Enqueue to CWB Queue wire cwbq_push = (valid_st2 && !miss_st2); wire [31:0] cwbq_data = readword_st2; - wire [`vx_clog2(`NUMBER_REQUESTS)-1:0] cwbq_tid = miss_add_tid; + wire [`vx_clog2(NUMBER_REQUESTS)-1:0] cwbq_tid = miss_add_tid; wire [4:0] cwbq_rd = miss_add_rd; wire [1:0] cwbq_wb = miss_add_wb; wire [`NW_M1:0] cwbq_warp_num = miss_add_warp_num; @@ -392,7 +493,7 @@ module VX_bank ( wire cwbq_full; wire cwbq_empty; assign bank_wb_valid = !cwbq_empty; - VX_generic_queue_ll #(.DATAW( `vx_clog2(`NUMBER_REQUESTS) + 5 + 2 + (`NW_M1+1) + 32), .SIZE(`CWBQ_SIZE)) cwb_queue( + VX_generic_queue_ll #(.DATAW( `vx_clog2(NUMBER_REQUESTS) + 5 + 2 + (`NW_M1+1) + 32), .SIZE(CWBQ_SIZE)) cwb_queue( .clk (clk), .reset (reset), @@ -415,7 +516,26 @@ module VX_bank ( wire invalidate_fill; wire possible_fill = valid_st2 && miss_st2; - VX_fill_invalidator VX_fill_invalidator( + VX_fill_invalidator #( + .CACHE_SIZE_BYTES (CACHE_SIZE_BYTES), + .BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES), + .NUMBER_BANKS (NUMBER_BANKS), + .WORD_SIZE_BYTES (WORD_SIZE_BYTES), + .NUMBER_REQUESTS (NUMBER_REQUESTS), + .STAGE_1_CYCLES (STAGE_1_CYCLES), + .REQQ_SIZE (REQQ_SIZE), + .MRVQ_SIZE (MRVQ_SIZE), + .DFPQ_SIZE (DFPQ_SIZE), + .SNRQ_SIZE (SNRQ_SIZE), + .CWBQ_SIZE (CWBQ_SIZE), + .DWBQ_SIZE (DWBQ_SIZE), + .DFQQ_SIZE (DFQQ_SIZE), + .LLVQ_SIZE (LLVQ_SIZE), + .FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE), + .SIMULATED_DRAM_LATENCY_CYCLES(SIMULATED_DRAM_LATENCY_CYCLES) + ) + VX_fill_invalidator + ( .clk (clk), .reset (reset), .possible_fill (possible_fill), @@ -432,7 +552,7 @@ module VX_bank ( assign dram_fill_req_addr = addr_st2; assign dram_wb_req = !dwbq_empty; - VX_generic_queue_ll #(.DATAW( 1 + 32 + (`BANK_LINE_SIZE_WORDS * 32) + 1 + 1), .SIZE(`DWBQ_SIZE)) dwb_queue( + VX_generic_queue_ll #(.DATAW( 1 + 32 + (`BANK_LINE_SIZE_WORDS * 32) + 1 + 1), .SIZE(DWBQ_SIZE)) dwb_queue( .clk (clk), .reset (reset), @@ -452,11 +572,11 @@ module VX_bank ( wire llvq_push = valid_st2 && !miss_st2; wire[`BANK_LINE_SIZE_RNG][31:0] llvq_push_data = readdata_st2; wire llvq_addr = addr_st2; - wire[`vx_clog2(`NUMBER_REQUESTS)-1:0] llvq_tid = miss_add_tid; + wire[`vx_clog2(NUMBER_REQUESTS)-1:0] llvq_tid = miss_add_tid; assign llvq_valid = !llvq_empty; - VX_generic_queue_ll #(.DATAW(`vx_clog2(`NUMBER_REQUESTS) + 32 + (`BANK_LINE_SIZE_WORDS * 32)), .SIZE(`LLVQ_SIZE)) llv_queue( + VX_generic_queue_ll #(.DATAW(`vx_clog2(NUMBER_REQUESTS) + 32 + (`BANK_LINE_SIZE_WORDS * 32)), .SIZE(LLVQ_SIZE)) llv_queue( .clk (clk), .reset (reset), .push (llvq_push), diff --git a/rtl/VX_cache/VX_cache.v b/rtl/VX_cache/VX_cache.v index 67ec6737..e00680ef 100644 --- a/rtl/VX_cache/VX_cache.v +++ b/rtl/VX_cache/VX_cache.v @@ -1,13 +1,57 @@ `include "VX_cache_config.v" -module VX_cache ( +module VX_cache + #( + // Size of cache in bytes + parameter CACHE_SIZE_BYTES = 1024, + // Size of line inside a bank in bytes + parameter BANK_LINE_SIZE_BYTES = 16, + // Number of banks {1, 2, 4, 8,...} + parameter NUMBER_BANKS = 8, + // Size of a word in bytes + parameter WORD_SIZE_BYTES = 4, + // Number of Word requests per cycle {1, 2, 4, 8, ...} + parameter NUMBER_REQUESTS = 2, + // Number of cycles to complete stage 1 (read from memory) + parameter STAGE_1_CYCLES = 2, + +// Queues feeding into banks Knobs {1, 2, 4, 8, ...} + + // Core Request Queue Size + parameter REQQ_SIZE = 8, + // Miss Reserv Queue Knob + parameter MRVQ_SIZE = 8, + // Dram Fill Rsp Queue Size + parameter DFPQ_SIZE = 2, + // Snoop Req Queue + parameter SNRQ_SIZE = 8, + +// Queues for writebacks Knobs {1, 2, 4, 8, ...} + // Core Writeback Queue Size + parameter CWBQ_SIZE = 8, + // Dram Writeback Queue Size + parameter DWBQ_SIZE = 4, + // Dram Fill Req Queue Size + parameter DFQQ_SIZE = 8, + // Lower Level Cache Hit Queue Size + parameter LLVQ_SIZE = 16, + + // Fill Invalidator Size {Fill invalidator must be active} + parameter FILL_INVALIDAOR_SIZE = 16, + +// Dram knobs + parameter SIMULATED_DRAM_LATENCY_CYCLES = 10 + + + ) + ( input wire clk, input wire reset, // Req Info - input wire [`NUMBER_REQUESTS-1:0] core_req_valid, - input wire [`NUMBER_REQUESTS-1:0][31:0] core_req_addr, - input wire [`NUMBER_REQUESTS-1:0][31:0] core_req_writedata, + input wire [NUMBER_REQUESTS-1:0] core_req_valid, + input wire [NUMBER_REQUESTS-1:0][31:0] core_req_addr, + input wire [NUMBER_REQUESTS-1:0][31:0] core_req_writedata, input wire[2:0] core_req_mem_read, input wire[2:0] core_req_mem_write, @@ -19,11 +63,11 @@ module VX_cache ( // Core Writeback input wire core_no_wb_slot, - output wire [`NUMBER_REQUESTS-1:0] core_wb_valid, + output wire [NUMBER_REQUESTS-1:0] core_wb_valid, output wire [4:0] core_wb_req_rd, output wire [1:0] core_wb_req_wb, output wire [`NW_M1:0] core_wb_warp_num, - output wire [`NUMBER_REQUESTS-1:0][31:0] core_wb_readdata, + output wire [NUMBER_REQUESTS-1:0][31:0] core_wb_readdata, // Dram Fill Response @@ -49,50 +93,69 @@ module VX_cache ( // Lower Level Cache input wire llvq_pop, - output wire[`NUMBER_REQUESTS-1:0] llvq_valid, - output wire[`NUMBER_REQUESTS-1:0][31:0] llvq_res_addr, - output wire[`NUMBER_REQUESTS-1:0][`BANK_LINE_SIZE_RNG][31:0] llvq_res_data + output wire[NUMBER_REQUESTS-1:0] llvq_valid, + output wire[NUMBER_REQUESTS-1:0][31:0] llvq_res_addr, + output wire[NUMBER_REQUESTS-1:0][`BANK_LINE_SIZE_RNG][31:0] llvq_res_data ); - wire [`NUMBER_BANKS-1:0][`NUMBER_REQUESTS-1:0] per_bank_valids; - wire [`NUMBER_BANKS-1:0] per_bank_wb_pop; - wire [`NUMBER_BANKS-1:0] per_bank_wb_valid; - wire [`NUMBER_BANKS-1:0][`vx_clog2(`NUMBER_REQUESTS)-1:0] per_bank_wb_tid; - wire [`NUMBER_BANKS-1:0][4:0] per_bank_wb_rd; - wire [`NUMBER_BANKS-1:0][1:0] per_bank_wb_wb; - wire [`NUMBER_BANKS-1:0][`NW_M1:0] per_bank_wb_warp_num; - wire [`NUMBER_BANKS-1:0][31:0] per_bank_wb_data; + wire [NUMBER_BANKS-1:0][NUMBER_REQUESTS-1:0] per_bank_valids; + wire [NUMBER_BANKS-1:0] per_bank_wb_pop; + wire [NUMBER_BANKS-1:0] per_bank_wb_valid; + wire [NUMBER_BANKS-1:0][`vx_clog2(NUMBER_REQUESTS)-1:0] per_bank_wb_tid; + wire [NUMBER_BANKS-1:0][4:0] per_bank_wb_rd; + wire [NUMBER_BANKS-1:0][1:0] per_bank_wb_wb; + wire [NUMBER_BANKS-1:0][`NW_M1:0] per_bank_wb_warp_num; + wire [NUMBER_BANKS-1:0][31:0] per_bank_wb_data; wire dfqq_full; - wire[`NUMBER_BANKS-1:0] per_bank_dram_fill_req; - wire[`NUMBER_BANKS-1:0][31:0] per_bank_dram_fill_req_addr; - wire[`NUMBER_BANKS-1:0] per_bank_dram_fill_accept; + wire[NUMBER_BANKS-1:0] per_bank_dram_fill_req; + wire[NUMBER_BANKS-1:0][31:0] per_bank_dram_fill_req_addr; + wire[NUMBER_BANKS-1:0] per_bank_dram_fill_accept; - wire[`NUMBER_BANKS-1:0] per_bank_dram_wb_queue_pop; - wire[`NUMBER_BANKS-1:0] per_bank_dram_wb_req; - wire[`NUMBER_BANKS-1:0] per_bank_dram_because_of_snp; - wire[`NUMBER_BANKS-1:0][31:0] per_bank_dram_wb_req_addr; - wire[`NUMBER_BANKS-1:0][`BANK_LINE_SIZE_RNG][31:0] per_bank_dram_wb_req_data; + wire[NUMBER_BANKS-1:0] per_bank_dram_wb_queue_pop; + wire[NUMBER_BANKS-1:0] per_bank_dram_wb_req; + wire[NUMBER_BANKS-1:0] per_bank_dram_because_of_snp; + wire[NUMBER_BANKS-1:0][31:0] per_bank_dram_wb_req_addr; + wire[NUMBER_BANKS-1:0][`BANK_LINE_SIZE_RNG][31:0] per_bank_dram_wb_req_data; - wire[`NUMBER_BANKS-1:0] per_bank_reqq_full; + wire[NUMBER_BANKS-1:0] per_bank_reqq_full; - wire[`NUMBER_BANKS-1:0] per_bank_llvq_pop; - wire[`NUMBER_BANKS-1:0] per_bank_llvq_valid; - wire[`NUMBER_BANKS-1:0][31:0] per_bank_llvq_res_addr; - wire[`NUMBER_BANKS-1:0][`BANK_LINE_SIZE_RNG][31:0] per_bank_llvq_res_data; - wire [`NUMBER_BANKS-1:0][`vx_clog2(`NUMBER_REQUESTS)-1:0] per_bank_llvq_res_tid; + wire[NUMBER_BANKS-1:0] per_bank_llvq_pop; + wire[NUMBER_BANKS-1:0] per_bank_llvq_valid; + wire[NUMBER_BANKS-1:0][31:0] per_bank_llvq_res_addr; + wire[NUMBER_BANKS-1:0][`BANK_LINE_SIZE_RNG][31:0] per_bank_llvq_res_data; + wire [NUMBER_BANKS-1:0][`vx_clog2(NUMBER_REQUESTS)-1:0] per_bank_llvq_res_tid; assign delay_req = (|per_bank_reqq_full); - assign dram_fill_accept = (`NUMBER_BANKS == 1) ? per_bank_dram_fill_accept[0] : per_bank_dram_fill_accept[dram_fill_rsp_addr[`BANK_SELECT_ADDR_RNG]]; + assign dram_fill_accept = (NUMBER_BANKS == 1) ? per_bank_dram_fill_accept[0] : per_bank_dram_fill_accept[dram_fill_rsp_addr[`BANK_SELECT_ADDR_RNG]]; - VX_dcache_llv_resp_bank_sel VX_dcache_llv_resp_bank_sel( + VX_dcache_llv_resp_bank_sel #( + .CACHE_SIZE_BYTES (CACHE_SIZE_BYTES), + .BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES), + .NUMBER_BANKS (NUMBER_BANKS), + .WORD_SIZE_BYTES (WORD_SIZE_BYTES), + .NUMBER_REQUESTS (NUMBER_REQUESTS), + .STAGE_1_CYCLES (STAGE_1_CYCLES), + .REQQ_SIZE (REQQ_SIZE), + .MRVQ_SIZE (MRVQ_SIZE), + .DFPQ_SIZE (DFPQ_SIZE), + .SNRQ_SIZE (SNRQ_SIZE), + .CWBQ_SIZE (CWBQ_SIZE), + .DWBQ_SIZE (DWBQ_SIZE), + .DFQQ_SIZE (DFQQ_SIZE), + .LLVQ_SIZE (LLVQ_SIZE), + .FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE), + .SIMULATED_DRAM_LATENCY_CYCLES(SIMULATED_DRAM_LATENCY_CYCLES) + ) + VX_dcache_llv_resp_bank_sel + ( .per_bank_llvq_pop (per_bank_llvq_pop), .per_bank_llvq_valid (per_bank_llvq_valid), .per_bank_llvq_res_addr(per_bank_llvq_res_addr), @@ -104,7 +167,26 @@ module VX_cache ( .llvq_res_data (llvq_res_data) ); - VX_cache_dram_req_arb VX_cache_dram_req_arb( + VX_cache_dram_req_arb #( + .CACHE_SIZE_BYTES (CACHE_SIZE_BYTES), + .BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES), + .NUMBER_BANKS (NUMBER_BANKS), + .WORD_SIZE_BYTES (WORD_SIZE_BYTES), + .NUMBER_REQUESTS (NUMBER_REQUESTS), + .STAGE_1_CYCLES (STAGE_1_CYCLES), + .REQQ_SIZE (REQQ_SIZE), + .MRVQ_SIZE (MRVQ_SIZE), + .DFPQ_SIZE (DFPQ_SIZE), + .SNRQ_SIZE (SNRQ_SIZE), + .CWBQ_SIZE (CWBQ_SIZE), + .DWBQ_SIZE (DWBQ_SIZE), + .DFQQ_SIZE (DFQQ_SIZE), + .LLVQ_SIZE (LLVQ_SIZE), + .FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE), + .SIMULATED_DRAM_LATENCY_CYCLES(SIMULATED_DRAM_LATENCY_CYCLES) + ) + VX_cache_dram_req_arb + ( .clk (clk), .reset (reset), .dfqq_full (dfqq_full), @@ -125,14 +207,52 @@ module VX_cache ( ); - VX_cache_core_req_bank_sel VX_cache_core_req_bank_sell( + VX_cache_core_req_bank_sel #( + .CACHE_SIZE_BYTES (CACHE_SIZE_BYTES), + .BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES), + .NUMBER_BANKS (NUMBER_BANKS), + .WORD_SIZE_BYTES (WORD_SIZE_BYTES), + .NUMBER_REQUESTS (NUMBER_REQUESTS), + .STAGE_1_CYCLES (STAGE_1_CYCLES), + .REQQ_SIZE (REQQ_SIZE), + .MRVQ_SIZE (MRVQ_SIZE), + .DFPQ_SIZE (DFPQ_SIZE), + .SNRQ_SIZE (SNRQ_SIZE), + .CWBQ_SIZE (CWBQ_SIZE), + .DWBQ_SIZE (DWBQ_SIZE), + .DFQQ_SIZE (DFQQ_SIZE), + .LLVQ_SIZE (LLVQ_SIZE), + .FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE), + .SIMULATED_DRAM_LATENCY_CYCLES(SIMULATED_DRAM_LATENCY_CYCLES) + ) + VX_cache_core_req_bank_sell + ( .core_req_valid (core_req_valid), .core_req_addr (core_req_addr), .per_bank_valids(per_bank_valids) ); - VX_cache_wb_sel_merge VX_cache_core_req_bank_sel( + VX_cache_wb_sel_merge #( + .CACHE_SIZE_BYTES (CACHE_SIZE_BYTES), + .BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES), + .NUMBER_BANKS (NUMBER_BANKS), + .WORD_SIZE_BYTES (WORD_SIZE_BYTES), + .NUMBER_REQUESTS (NUMBER_REQUESTS), + .STAGE_1_CYCLES (STAGE_1_CYCLES), + .REQQ_SIZE (REQQ_SIZE), + .MRVQ_SIZE (MRVQ_SIZE), + .DFPQ_SIZE (DFPQ_SIZE), + .SNRQ_SIZE (SNRQ_SIZE), + .CWBQ_SIZE (CWBQ_SIZE), + .DWBQ_SIZE (DWBQ_SIZE), + .DFQQ_SIZE (DFQQ_SIZE), + .LLVQ_SIZE (LLVQ_SIZE), + .FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE), + .SIMULATED_DRAM_LATENCY_CYCLES(SIMULATED_DRAM_LATENCY_CYCLES) + ) + VX_cache_core_req_bank_sel + ( .per_bank_wb_valid (per_bank_wb_valid), .per_bank_wb_tid (per_bank_wb_tid), .per_bank_wb_rd (per_bank_wb_rd), @@ -151,10 +271,10 @@ module VX_cache ( genvar curr_bank; generate - for (curr_bank = 0; curr_bank < `NUMBER_BANKS; curr_bank=curr_bank+1) begin - wire [`NUMBER_REQUESTS-1:0] curr_bank_valids; - wire [`NUMBER_REQUESTS-1:0][31:0] curr_bank_addr; - wire [`NUMBER_REQUESTS-1:0][31:0] curr_bank_writedata; + for (curr_bank = 0; curr_bank < NUMBER_BANKS; curr_bank=curr_bank+1) begin + wire [NUMBER_REQUESTS-1:0] curr_bank_valids; + wire [NUMBER_REQUESTS-1:0][31:0] curr_bank_addr; + wire [NUMBER_REQUESTS-1:0][31:0] curr_bank_writedata; wire [4:0] curr_bank_rd; wire [1:0] curr_bank_wb; wire [`NW_M1:0] curr_bank_warp_num; @@ -163,7 +283,7 @@ module VX_cache ( wire curr_bank_wb_pop; wire curr_bank_wb_valid; - wire [`vx_clog2(`NUMBER_REQUESTS)-1:0] curr_bank_wb_tid; + wire [`vx_clog2(NUMBER_REQUESTS)-1:0] curr_bank_wb_tid; wire [4:0] curr_bank_wb_rd; wire [1:0] curr_bank_wb_wb; wire [`NW_M1:0] curr_bank_wb_warp_num; @@ -195,7 +315,7 @@ module VX_cache ( wire curr_bank_llvq_valid; wire[31:0] curr_bank_llvq_res_addr; wire[`BANK_LINE_SIZE_RNG][31:0] curr_bank_llvq_res_data; - wire[`vx_clog2(`NUMBER_REQUESTS)-1:0] curr_bank_llvq_res_tid; + wire[`vx_clog2(NUMBER_REQUESTS)-1:0] curr_bank_llvq_res_tid; // Core Req @@ -224,7 +344,7 @@ module VX_cache ( assign per_bank_dram_fill_req_addr[curr_bank] = curr_bank_dram_fill_req_addr; // Dram fill response - assign curr_bank_dram_fill_rsp = (`NUMBER_BANKS == 1) || (dram_fill_rsp && (curr_bank_dram_fill_rsp_addr[`BANK_SELECT_ADDR_RNG] == curr_bank)); + assign curr_bank_dram_fill_rsp = (NUMBER_BANKS == 1) || (dram_fill_rsp && (curr_bank_dram_fill_rsp_addr[`BANK_SELECT_ADDR_RNG] == curr_bank)); assign curr_bank_dram_fill_rsp_addr = dram_fill_rsp_addr; assign curr_bank_dram_fill_rsp_data = dram_fill_rsp_data; assign per_bank_dram_fill_accept[curr_bank] = curr_bank_dram_fill_accept; @@ -248,7 +368,26 @@ module VX_cache ( assign per_bank_llvq_res_addr[curr_bank] = curr_bank_llvq_res_addr; assign per_bank_llvq_res_tid[curr_bank] = curr_bank_llvq_res_tid; - VX_bank bank ( + VX_bank #( + .CACHE_SIZE_BYTES (CACHE_SIZE_BYTES), + .BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES), + .NUMBER_BANKS (NUMBER_BANKS), + .WORD_SIZE_BYTES (WORD_SIZE_BYTES), + .NUMBER_REQUESTS (NUMBER_REQUESTS), + .STAGE_1_CYCLES (STAGE_1_CYCLES), + .REQQ_SIZE (REQQ_SIZE), + .MRVQ_SIZE (MRVQ_SIZE), + .DFPQ_SIZE (DFPQ_SIZE), + .SNRQ_SIZE (SNRQ_SIZE), + .CWBQ_SIZE (CWBQ_SIZE), + .DWBQ_SIZE (DWBQ_SIZE), + .DFQQ_SIZE (DFQQ_SIZE), + .LLVQ_SIZE (LLVQ_SIZE), + .FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE), + .SIMULATED_DRAM_LATENCY_CYCLES(SIMULATED_DRAM_LATENCY_CYCLES) + ) + bank + ( .clk (clk), .reset (reset), // Core req diff --git a/rtl/VX_cache/VX_cache_config.v b/rtl/VX_cache/VX_cache_config.v index 648c2137..0757d15a 100644 --- a/rtl/VX_cache/VX_cache_config.v +++ b/rtl/VX_cache/VX_cache_config.v @@ -3,57 +3,11 @@ `include "../VX_define.v" -// ========================================= Configurable Knobs ========================================= - -// General Cache Knobs - // Size of cache in bytes - `define CACHE_SIZE_BYTES 1024 - // Size of line inside a bank in bytes - `define BANK_LINE_SIZE_BYTES 16 - // Number of banks {1, 2, 4, 8,...} - `define NUMBER_BANKS 8 - // Size of a word in bytes - `define WORD_SIZE_BYTES 4 - // Number of Word requests per cycle {1, 2, 4, 8, ...} - `define NUMBER_REQUESTS `NT - // Number of cycles to complete stage 1 (read from memory) - `define STAGE_1_CYCLES 2 - -// Queues feeding into banks Knobs {1, 2, 4, 8, ...} - - // Core Request Queue Size - `define REQQ_SIZE `NT*`NW - // Miss Reserv Queue Knob - `define MRVQ_SIZE `REQQ_SIZE - // Dram Fill Rsp Queue Size - `define DFPQ_SIZE 2 - // Snoop Req Queue - `define SNRQ_SIZE 8 - -// Queues for writebacks Knobs {1, 2, 4, 8, ...} - // Core Writeback Queue Size - `define CWBQ_SIZE `REQQ_SIZE - // Dram Writeback Queue Size - `define DWBQ_SIZE 4 - // Dram Fill Req Queue Size - `define DFQQ_SIZE `REQQ_SIZE - // Lower Level Cache Hit Queue Size - `define LLVQ_SIZE 16 - - // Fill Invalidator Active {Comment out define statement to invalidate} - `define FILL_INVALIDATOR_ACTIVE 1 - // Fill Invalidator Size {Fill invalidator must be active} - `define FILL_INVALIDAOR_SIZE 16 - -// Dram knobs - `define SIMULATED_DRAM_LATENCY_CYCLES 10 - -// ========================================= Configurable Knobs ========================================= // data tid rd wb warp_num read write -`define MRVQ_METADATA_SIZE (32 + $clog2(`NUMBER_REQUESTS) + 5 + 2 + (`NW_M1 + 1) + 3 + 3) +`define MRVQ_METADATA_SIZE (32 + $clog2(NUMBER_REQUESTS) + 5 + 2 + (`NW_M1 + 1) + 3 + 3) -`define REQ_INST_META_SIZE (5 + 2 + (`NW_M1+1) + 3 + 3 + $clog2(`NUMBER_REQUESTS)) +`define REQ_INST_META_SIZE (5 + 2 + (`NW_M1+1) + 3 + 3 + $clog2(NUMBER_REQUESTS)) `define vx_clog2(value) $clog2(value) // `define vx_clog2_h(value, x) (value == (1 << x)) ? (x) @@ -93,11 +47,11 @@ // 0 -`define BANK_SIZE_BYTES `CACHE_SIZE_BYTES/`NUMBER_BANKS +`define BANK_SIZE_BYTES CACHE_SIZE_BYTES/NUMBER_BANKS -`define BANK_LINE_COUNT (`BANK_SIZE_BYTES/`BANK_LINE_SIZE_BYTES) -`define BANK_LINE_SIZE_WORDS (`BANK_LINE_SIZE_BYTES / `WORD_SIZE_BYTES) +`define BANK_LINE_COUNT (`BANK_SIZE_BYTES/BANK_LINE_SIZE_BYTES) +`define BANK_LINE_SIZE_WORDS (BANK_LINE_SIZE_BYTES / NUMBER_BANKS) `define BANK_LINE_SIZE_RNG `BANK_LINE_SIZE_WORDS-1:0 // Offset is fixed @@ -115,7 +69,7 @@ `define WORD_SELECT_ADDR_RNG `WORD_SELECT_ADDR_END:`WORD_SELECT_ADDR_START `define WORD_SELECT_SIZE_RNG `WORD_SELECT_SIZE_END-1:0 -`define BANK_SELECT_NUM_BITS $clog2(`NUMBER_BANKS) +`define BANK_SELECT_NUM_BITS $clog2(NUMBER_BANKS) `define BANK_SELECT_SIZE_END `BANK_SELECT_NUM_BITS `define BANK_SELECT_ADDR_START 1+`WORD_SELECT_ADDR_END `define BANK_SELECT_ADDR_END `BANK_SELECT_SIZE_END+`BANK_SELECT_ADDR_START diff --git a/rtl/VX_cache/VX_cache_core_req_bank_sel.v b/rtl/VX_cache/VX_cache_core_req_bank_sel.v index fb968fcf..cf47d063 100644 --- a/rtl/VX_cache/VX_cache_core_req_bank_sel.v +++ b/rtl/VX_cache/VX_cache_core_req_bank_sel.v @@ -1,11 +1,55 @@ `include "VX_cache_config.v" -module VX_cache_core_req_bank_sel ( - input wire [`NUMBER_REQUESTS-1:0] core_req_valid, - input wire [`NUMBER_REQUESTS-1:0][31:0] core_req_addr, +module VX_cache_core_req_bank_sel + #( + // Size of cache in bytes + parameter CACHE_SIZE_BYTES = 1024, + // Size of line inside a bank in bytes + parameter BANK_LINE_SIZE_BYTES = 16, + // Number of banks {1, 2, 4, 8,...} + parameter NUMBER_BANKS = 8, + // Size of a word in bytes + parameter WORD_SIZE_BYTES = 4, + // Number of Word requests per cycle {1, 2, 4, 8, ...} + parameter NUMBER_REQUESTS = 2, + // Number of cycles to complete stage 1 (read from memory) + parameter STAGE_1_CYCLES = 2, + +// Queues feeding into banks Knobs {1, 2, 4, 8, ...} + + // Core Request Queue Size + parameter REQQ_SIZE = 8, + // Miss Reserv Queue Knob + parameter MRVQ_SIZE = 8, + // Dram Fill Rsp Queue Size + parameter DFPQ_SIZE = 2, + // Snoop Req Queue + parameter SNRQ_SIZE = 8, + +// Queues for writebacks Knobs {1, 2, 4, 8, ...} + // Core Writeback Queue Size + parameter CWBQ_SIZE = 8, + // Dram Writeback Queue Size + parameter DWBQ_SIZE = 4, + // Dram Fill Req Queue Size + parameter DFQQ_SIZE = 8, + // Lower Level Cache Hit Queue Size + parameter LLVQ_SIZE = 16, + + // Fill Invalidator Size {Fill invalidator must be active} + parameter FILL_INVALIDAOR_SIZE = 16, + +// Dram knobs + parameter SIMULATED_DRAM_LATENCY_CYCLES = 10 + + + ) + ( + input wire [NUMBER_REQUESTS-1:0] core_req_valid, + input wire [NUMBER_REQUESTS-1:0][31:0] core_req_addr, - output reg [`NUMBER_BANKS-1:0][`NUMBER_REQUESTS-1:0] per_bank_valids + output reg [NUMBER_BANKS-1:0][NUMBER_REQUESTS-1:0] per_bank_valids ); wire[31:0] req_address; @@ -14,8 +58,8 @@ module VX_cache_core_req_bank_sel ( integer curr_req; always @(*) begin per_bank_valids = 0; - for (curr_req = 0; curr_req < `NUMBER_REQUESTS; curr_req = curr_req + 1) begin - if (`NUMBER_BANKS == 1) begin + for (curr_req = 0; curr_req < NUMBER_REQUESTS; curr_req = curr_req + 1) begin + if (NUMBER_BANKS == 1) begin // If there is only one bank, then only map requests to that bank per_bank_valids[0][curr_req] = core_req_valid[curr_req]; end else begin diff --git a/rtl/VX_cache/VX_cache_dfq_queue.v b/rtl/VX_cache/VX_cache_dfq_queue.v index 214d183f..b2d4743a 100644 --- a/rtl/VX_cache/VX_cache_dfq_queue.v +++ b/rtl/VX_cache/VX_cache_dfq_queue.v @@ -1,12 +1,55 @@ `include "VX_cache_config.v" module VX_cache_dfq_queue + #( + // Size of cache in bytes + parameter CACHE_SIZE_BYTES = 1024, + // Size of line inside a bank in bytes + parameter BANK_LINE_SIZE_BYTES = 16, + // Number of banks {1, 2, 4, 8,...} + parameter NUMBER_BANKS = 8, + // Size of a word in bytes + parameter WORD_SIZE_BYTES = 4, + // Number of Word requests per cycle {1, 2, 4, 8, ...} + parameter NUMBER_REQUESTS = 2, + // Number of cycles to complete stage 1 (read from memory) + parameter STAGE_1_CYCLES = 2, + +// Queues feeding into banks Knobs {1, 2, 4, 8, ...} + + // Core Request Queue Size + parameter REQQ_SIZE = 8, + // Miss Reserv Queue Knob + parameter MRVQ_SIZE = 8, + // Dram Fill Rsp Queue Size + parameter DFPQ_SIZE = 2, + // Snoop Req Queue + parameter SNRQ_SIZE = 8, + +// Queues for writebacks Knobs {1, 2, 4, 8, ...} + // Core Writeback Queue Size + parameter CWBQ_SIZE = 8, + // Dram Writeback Queue Size + parameter DWBQ_SIZE = 4, + // Dram Fill Req Queue Size + parameter DFQQ_SIZE = 8, + // Lower Level Cache Hit Queue Size + parameter LLVQ_SIZE = 16, + + // Fill Invalidator Size {Fill invalidator must be active} + parameter FILL_INVALIDAOR_SIZE = 16, + +// Dram knobs + parameter SIMULATED_DRAM_LATENCY_CYCLES = 10 + + + ) ( input wire clk, input wire reset, input wire dfqq_push, - input wire[`NUMBER_BANKS-1:0] per_bank_dram_fill_req, - input wire[`NUMBER_BANKS-1:0][31:0] per_bank_dram_fill_req_addr, + input wire[NUMBER_BANKS-1:0] per_bank_dram_fill_req, + input wire[NUMBER_BANKS-1:0][31:0] per_bank_dram_fill_req_addr, input wire dfqq_pop, output wire dfqq_req, @@ -15,18 +58,18 @@ module VX_cache_dfq_queue output wire dfqq_full ); - wire[`NUMBER_BANKS-1:0] out_per_bank_dram_fill_req; - wire[`NUMBER_BANKS-1:0][31:0] out_per_bank_dram_fill_req_addr; + wire[NUMBER_BANKS-1:0] out_per_bank_dram_fill_req; + wire[NUMBER_BANKS-1:0][31:0] out_per_bank_dram_fill_req_addr; - reg [`NUMBER_BANKS-1:0] use_per_bank_dram_fill_req; - reg [`NUMBER_BANKS-1:0][31:0] use_per_bank_dram_fill_req_addr; + reg [NUMBER_BANKS-1:0] use_per_bank_dram_fill_req; + reg [NUMBER_BANKS-1:0][31:0] use_per_bank_dram_fill_req_addr; - wire[`NUMBER_BANKS-1:0] qual_bank_dram_fill_req; - wire[`NUMBER_BANKS-1:0][31:0] qual_bank_dram_fill_req_addr; + wire[NUMBER_BANKS-1:0] qual_bank_dram_fill_req; + wire[NUMBER_BANKS-1:0][31:0] qual_bank_dram_fill_req_addr; - wire[`NUMBER_BANKS-1:0] updated_bank_dram_fill_req; + wire[NUMBER_BANKS-1:0] updated_bank_dram_fill_req; wire o_empty; @@ -36,7 +79,7 @@ module VX_cache_dfq_queue wire push_qual = dfqq_push && !dfqq_full; wire pop_qual = dfqq_pop && use_empty && !out_empty; - VX_generic_queue_ll #(.DATAW(`NUMBER_BANKS * (1+32)), .SIZE(`DFQQ_SIZE)) dfqq_queue( + VX_generic_queue_ll #(.DATAW(NUMBER_BANKS * (1+32)), .SIZE(DFQQ_SIZE)) dfqq_queue( .clk (clk), .reset (reset), .push (push_qual), @@ -51,9 +94,9 @@ module VX_cache_dfq_queue assign qual_bank_dram_fill_req = use_empty ? out_per_bank_dram_fill_req : use_per_bank_dram_fill_req; assign qual_bank_dram_fill_req_addr = use_empty ? out_per_bank_dram_fill_req_addr : use_per_bank_dram_fill_req_addr; - wire[`vx_clog2(`NUMBER_BANKS)-1:0] qual_request_index; + wire[`vx_clog2(NUMBER_BANKS)-1:0] qual_request_index; wire qual_has_request; - VX_generic_priority_encoder #(.N(`NUMBER_BANKS)) VX_sel_bank( + VX_generic_priority_encoder #(.N(NUMBER_BANKS)) VX_sel_bank( .valids(qual_bank_dram_fill_req), .index (qual_request_index), .found (qual_has_request) diff --git a/rtl/VX_cache/VX_cache_dram_req_arb.v b/rtl/VX_cache/VX_cache_dram_req_arb.v index af5f9ba6..01e699ed 100644 --- a/rtl/VX_cache/VX_cache_dram_req_arb.v +++ b/rtl/VX_cache/VX_cache_dram_req_arb.v @@ -1,21 +1,65 @@ `include "VX_cache_config.v" -module VX_cache_dram_req_arb ( +module VX_cache_dram_req_arb + #( + // Size of cache in bytes + parameter CACHE_SIZE_BYTES = 1024, + // Size of line inside a bank in bytes + parameter BANK_LINE_SIZE_BYTES = 16, + // Number of banks {1, 2, 4, 8,...} + parameter NUMBER_BANKS = 8, + // Size of a word in bytes + parameter WORD_SIZE_BYTES = 4, + // Number of Word requests per cycle {1, 2, 4, 8, ...} + parameter NUMBER_REQUESTS = 2, + // Number of cycles to complete stage 1 (read from memory) + parameter STAGE_1_CYCLES = 2, + +// Queues feeding into banks Knobs {1, 2, 4, 8, ...} + + // Core Request Queue Size + parameter REQQ_SIZE = 8, + // Miss Reserv Queue Knob + parameter MRVQ_SIZE = 8, + // Dram Fill Rsp Queue Size + parameter DFPQ_SIZE = 2, + // Snoop Req Queue + parameter SNRQ_SIZE = 8, + +// Queues for writebacks Knobs {1, 2, 4, 8, ...} + // Core Writeback Queue Size + parameter CWBQ_SIZE = 8, + // Dram Writeback Queue Size + parameter DWBQ_SIZE = 4, + // Dram Fill Req Queue Size + parameter DFQQ_SIZE = 8, + // Lower Level Cache Hit Queue Size + parameter LLVQ_SIZE = 16, + + // Fill Invalidator Size {Fill invalidator must be active} + parameter FILL_INVALIDAOR_SIZE = 16, + +// Dram knobs + parameter SIMULATED_DRAM_LATENCY_CYCLES = 10 + + + ) + ( input wire clk, input wire reset, // Fill Request output wire dfqq_full, - input wire[`NUMBER_BANKS-1:0] per_bank_dram_fill_req, - input wire[`NUMBER_BANKS-1:0][31:0] per_bank_dram_fill_req_addr, + input wire[NUMBER_BANKS-1:0] per_bank_dram_fill_req, + input wire[NUMBER_BANKS-1:0][31:0] per_bank_dram_fill_req_addr, // DFQ Request - output wire[`NUMBER_BANKS-1:0] per_bank_dram_wb_queue_pop, - input wire[`NUMBER_BANKS-1:0] per_bank_dram_wb_req, - input wire[`NUMBER_BANKS-1:0][31:0] per_bank_dram_wb_req_addr, - input wire[`NUMBER_BANKS-1:0][`BANK_LINE_SIZE_RNG][31:0] per_bank_dram_wb_req_data, - input wire[`NUMBER_BANKS-1:0] per_bank_dram_because_of_snp, + output wire[NUMBER_BANKS-1:0] per_bank_dram_wb_queue_pop, + input wire[NUMBER_BANKS-1:0] per_bank_dram_wb_req, + input wire[NUMBER_BANKS-1:0][31:0] per_bank_dram_wb_req_addr, + input wire[NUMBER_BANKS-1:0][`BANK_LINE_SIZE_RNG][31:0] per_bank_dram_wb_req_data, + input wire[NUMBER_BANKS-1:0] per_bank_dram_because_of_snp, // real Dram request output wire dram_req, @@ -48,9 +92,9 @@ module VX_cache_dram_req_arb ( .dfqq_full (dfqq_full) ); - wire[`vx_clog2(`NUMBER_BANKS)-1:0] dwb_bank; - wire[`NUMBER_BANKS-1:0] use_wb_valid = per_bank_dram_wb_req | per_bank_dram_because_of_snp; - VX_generic_priority_encoder #(.N(`NUMBER_BANKS)) VX_sel_dwb( + wire[`vx_clog2(NUMBER_BANKS)-1:0] dwb_bank; + wire[NUMBER_BANKS-1:0] use_wb_valid = per_bank_dram_wb_req | per_bank_dram_because_of_snp; + VX_generic_priority_encoder #(.N(NUMBER_BANKS)) VX_sel_dwb( .valids(use_wb_valid), .index (dwb_bank), .found (dwb_valid) @@ -64,7 +108,7 @@ module VX_cache_dram_req_arb ( assign dram_req_write = dwb_valid; assign dram_req_read = dfqq_req && !dwb_valid; assign dram_req_addr = (dwb_valid ? per_bank_dram_wb_req_addr[dwb_bank] : dfqq_req_addr) & `BASE_ADDR_MASK; - assign dram_req_size = `BANK_LINE_SIZE_BYTES; + assign dram_req_size = BANK_LINE_SIZE_BYTES; assign dram_req_data = dwb_valid ? per_bank_dram_wb_req_data[dwb_bank] : 0; assign dram_req_because_of_wb = dwb_valid ? per_bank_dram_because_of_snp[dwb_bank] : 0; diff --git a/rtl/VX_cache/VX_cache_miss_resrv.v b/rtl/VX_cache/VX_cache_miss_resrv.v index 9724e761..9c2be799 100644 --- a/rtl/VX_cache/VX_cache_miss_resrv.v +++ b/rtl/VX_cache/VX_cache_miss_resrv.v @@ -1,7 +1,51 @@ `include "VX_cache_config.v" -module VX_cache_miss_resrv ( +module VX_cache_miss_resrv + #( + // Size of cache in bytes + parameter CACHE_SIZE_BYTES = 1024, + // Size of line inside a bank in bytes + parameter BANK_LINE_SIZE_BYTES = 16, + // Number of banks {1, 2, 4, 8,...} + parameter NUMBER_BANKS = 8, + // Size of a word in bytes + parameter WORD_SIZE_BYTES = 4, + // Number of Word requests per cycle {1, 2, 4, 8, ...} + parameter NUMBER_REQUESTS = 2, + // Number of cycles to complete stage 1 (read from memory) + parameter STAGE_1_CYCLES = 2, + +// Queues feeding into banks Knobs {1, 2, 4, 8, ...} + + // Core Request Queue Size + parameter REQQ_SIZE = 8, + // Miss Reserv Queue Knob + parameter MRVQ_SIZE = 8, + // Dram Fill Rsp Queue Size + parameter DFPQ_SIZE = 2, + // Snoop Req Queue + parameter SNRQ_SIZE = 8, + +// Queues for writebacks Knobs {1, 2, 4, 8, ...} + // Core Writeback Queue Size + parameter CWBQ_SIZE = 8, + // Dram Writeback Queue Size + parameter DWBQ_SIZE = 4, + // Dram Fill Req Queue Size + parameter DFQQ_SIZE = 8, + // Lower Level Cache Hit Queue Size + parameter LLVQ_SIZE = 16, + + // Fill Invalidator Size {Fill invalidator must be active} + parameter FILL_INVALIDAOR_SIZE = 16, + +// Dram knobs + parameter SIMULATED_DRAM_LATENCY_CYCLES = 10 + + + ) + ( input wire clk, input wire reset, @@ -9,7 +53,7 @@ module VX_cache_miss_resrv ( input wire miss_add, input wire[31:0] miss_add_addr, input wire[31:0] miss_add_data, - input wire[`vx_clog2(`NUMBER_REQUESTS)-1:0] miss_add_tid, + input wire[`vx_clog2(NUMBER_REQUESTS)-1:0] miss_add_tid, input wire[4:0] miss_add_rd, input wire[1:0] miss_add_wb, input wire[`NW_M1:0] miss_add_warp_num, @@ -26,7 +70,7 @@ module VX_cache_miss_resrv ( output wire miss_resrv_valid_st0, output wire[31:0] miss_resrv_addr_st0, output wire[31:0] miss_resrv_data_st0, - output wire[`vx_clog2(`NUMBER_REQUESTS)-1:0] miss_resrv_tid_st0, + output wire[`vx_clog2(NUMBER_REQUESTS)-1:0] miss_resrv_tid_st0, output wire[4:0] miss_resrv_rd_st0, output wire[1:0] miss_resrv_wb_st0, output wire[`NW_M1:0] miss_resrv_warp_num_st0, @@ -35,69 +79,71 @@ module VX_cache_miss_resrv ( ); - // Size of metadata = 32 + `vx_clog2(`NUMBER_REQUESTS) + 5 + 2 + (`NW_M1 + 1) - reg[`MRVQ_METADATA_SIZE-1:0] metadata_table[`MRVQ_SIZE-1:0]; - reg[`MRVQ_SIZE-1:0][31:0] addr_table; - reg[`MRVQ_SIZE-1:0] valid_table; - reg[`MRVQ_SIZE-1:0] ready_table; - reg[`vx_clog2(`MRVQ_SIZE)-1:0] head_ptr; - reg[`vx_clog2(`MRVQ_SIZE)-1:0] tail_ptr; + // Size of metadata = 32 + `vx_clog2(NUMBER_REQUESTS) + 5 + 2 + (`NW_M1 + 1) + reg[`MRVQ_METADATA_SIZE-1:0] metadata_table[MRVQ_SIZE-1:0]; + reg[MRVQ_SIZE-1:0][31:0] addr_table; + reg[MRVQ_SIZE-1:0] valid_table; + reg[MRVQ_SIZE-1:0] ready_table; + reg[`vx_clog2(MRVQ_SIZE)-1:0] head_ptr; + reg[`vx_clog2(MRVQ_SIZE)-1:0] tail_ptr; - assign miss_resrv_full = (tail_ptr+1) == head_ptr; + assign miss_resrv_full = (MRVQ_SIZE != 2) && (tail_ptr+1) == head_ptr; - wire enqueue_possible = !miss_resrv_full; - wire[`vx_clog2(`MRVQ_SIZE)-1:0] enqueue_index = tail_ptr; + wire enqueue_possible = !miss_resrv_full; + wire[`vx_clog2(MRVQ_SIZE)-1:0] enqueue_index = tail_ptr; - reg[`MRVQ_SIZE-1:0] make_ready; - genvar curr_e; - generate - for (curr_e = 0; curr_e < `MRVQ_SIZE; curr_e=curr_e+1) begin - assign make_ready[curr_e] = is_fill_st1 && valid_table[curr_e] - && addr_table[curr_e][31:`LINE_SELECT_ADDR_START] == fill_addr_st1[31:`LINE_SELECT_ADDR_START]; + reg[MRVQ_SIZE-1:0] make_ready; + genvar curr_e; + generate + for (curr_e = 0; curr_e < MRVQ_SIZE; curr_e=curr_e+1) begin + assign make_ready[curr_e] = is_fill_st1 && valid_table[curr_e] + && addr_table[curr_e][31:`LINE_SELECT_ADDR_START] == fill_addr_st1[31:`LINE_SELECT_ADDR_START]; + end + endgenerate + + + wire dequeue_possible = valid_table[head_ptr] && ready_table[head_ptr]; + wire[`vx_clog2(MRVQ_SIZE)-1:0] dequeue_index = head_ptr; + + assign miss_resrv_valid_st0 = (MRVQ_SIZE != 2) && dequeue_possible; + + assign miss_resrv_addr_st0 = addr_table[dequeue_index]; + assign {miss_resrv_data_st0, miss_resrv_tid_st0, miss_resrv_rd_st0, miss_resrv_wb_st0, miss_resrv_warp_num_st0, miss_resrv_mem_read_st0, miss_resrv_mem_write_st0} = metadata_table[dequeue_index]; + + wire update_ready = (|make_ready); + integer i; + always @(posedge clk) begin + if (reset) begin + for (i = 0; i < MRVQ_SIZE; i=i+1) metadata_table[i] <= 0; + valid_table <= 0; + ready_table <= 0; + addr_table <= 0; + end else begin + if (miss_add && enqueue_possible && (MRVQ_SIZE != 2)) begin + valid_table[enqueue_index] <= 1; + ready_table[enqueue_index] <= 0; + addr_table[enqueue_index] <= miss_add_addr; + metadata_table[enqueue_index] <= {miss_add_data, miss_add_tid, miss_add_rd, miss_add_wb, miss_add_warp_num, miss_add_mem_read, miss_add_mem_write}; + tail_ptr <= tail_ptr + 1; + end + + if (update_ready) begin + ready_table <= ready_table | make_ready; + end + + if (miss_resrv_pop && dequeue_possible) begin + valid_table[dequeue_index] <= 0; + ready_table[dequeue_index] <= 0; + addr_table[dequeue_index] <= 0; + metadata_table[dequeue_index] <= 0; + head_ptr <= head_ptr + 1; + end + + end end - endgenerate - wire dequeue_possible = valid_table[head_ptr] && ready_table[head_ptr]; - wire[`vx_clog2(`MRVQ_SIZE)-1:0] dequeue_index = head_ptr; - - assign miss_resrv_valid_st0 = dequeue_possible; - assign miss_resrv_addr_st0 = addr_table[dequeue_index]; - assign {miss_resrv_data_st0, miss_resrv_tid_st0, miss_resrv_rd_st0, miss_resrv_wb_st0, miss_resrv_warp_num_st0, miss_resrv_mem_read_st0, miss_resrv_mem_write_st0} = metadata_table[dequeue_index]; - - wire update_ready = (|make_ready); - integer i; - always @(posedge clk) begin - if (reset) begin - for (i = 0; i < `MRVQ_SIZE; i=i+1) metadata_table[i] <= 0; - valid_table <= 0; - ready_table <= 0; - addr_table <= 0; - end else begin - if (miss_add && enqueue_possible) begin - valid_table[enqueue_index] <= 1; - ready_table[enqueue_index] <= 0; - addr_table[enqueue_index] <= miss_add_addr; - metadata_table[enqueue_index] <= {miss_add_data, miss_add_tid, miss_add_rd, miss_add_wb, miss_add_warp_num, miss_add_mem_read, miss_add_mem_write}; - tail_ptr <= tail_ptr + 1; - end - - if (update_ready) begin - ready_table <= ready_table | make_ready; - end - - if (miss_resrv_pop && dequeue_possible) begin - valid_table[dequeue_index] <= 0; - ready_table[dequeue_index] <= 0; - addr_table[dequeue_index] <= 0; - metadata_table[dequeue_index] <= 0; - head_ptr <= head_ptr + 1; - end - - end - end - endmodule \ No newline at end of file diff --git a/rtl/VX_cache/VX_cache_req_queue.v b/rtl/VX_cache/VX_cache_req_queue.v index 2b1e4d98..cbc4ce67 100644 --- a/rtl/VX_cache/VX_cache_req_queue.v +++ b/rtl/VX_cache/VX_cache_req_queue.v @@ -1,14 +1,58 @@ `include "VX_cache_config.v" -module VX_cache_req_queue ( +module VX_cache_req_queue + #( + // Size of cache in bytes + parameter CACHE_SIZE_BYTES = 1024, + // Size of line inside a bank in bytes + parameter BANK_LINE_SIZE_BYTES = 16, + // Number of banks {1, 2, 4, 8,...} + parameter NUMBER_BANKS = 8, + // Size of a word in bytes + parameter WORD_SIZE_BYTES = 4, + // Number of Word requests per cycle {1, 2, 4, 8, ...} + parameter NUMBER_REQUESTS = 2, + // Number of cycles to complete stage 1 (read from memory) + parameter STAGE_1_CYCLES = 2, + +// Queues feeding into banks Knobs {1, 2, 4, 8, ...} + + // Core Request Queue Size + parameter REQQ_SIZE = 8, + // Miss Reserv Queue Knob + parameter MRVQ_SIZE = 8, + // Dram Fill Rsp Queue Size + parameter DFPQ_SIZE = 2, + // Snoop Req Queue + parameter SNRQ_SIZE = 8, + +// Queues for writebacks Knobs {1, 2, 4, 8, ...} + // Core Writeback Queue Size + parameter CWBQ_SIZE = 8, + // Dram Writeback Queue Size + parameter DWBQ_SIZE = 4, + // Dram Fill Req Queue Size + parameter DFQQ_SIZE = 8, + // Lower Level Cache Hit Queue Size + parameter LLVQ_SIZE = 16, + + // Fill Invalidator Size {Fill invalidator must be active} + parameter FILL_INVALIDAOR_SIZE = 16, + +// Dram knobs + parameter SIMULATED_DRAM_LATENCY_CYCLES = 10 + + + ) + ( input wire clk, input wire reset, // Enqueue Data input wire reqq_push, - input wire [`NUMBER_REQUESTS-1:0] bank_valids, - input wire [`NUMBER_REQUESTS-1:0][31:0] bank_addr, - input wire [`NUMBER_REQUESTS-1:0][31:0] bank_writedata, + input wire [NUMBER_REQUESTS-1:0] bank_valids, + input wire [NUMBER_REQUESTS-1:0][31:0] bank_addr, + input wire [NUMBER_REQUESTS-1:0][31:0] bank_writedata, input wire [4:0] bank_rd, input wire [1:0] bank_wb, input wire [`NW_M1:0] bank_warp_num, @@ -18,7 +62,7 @@ module VX_cache_req_queue ( // Dequeue Data input wire reqq_pop, output wire reqq_req_st0, - output wire [`vx_clog2(`NUMBER_REQUESTS)-1:0] reqq_req_tid_st0, + output wire [`vx_clog2(NUMBER_REQUESTS)-1:0] reqq_req_tid_st0, output wire [31:0] reqq_req_addr_st0, output wire [31:0] reqq_req_writedata_st0, output wire [4:0] reqq_req_rd_st0, @@ -32,9 +76,9 @@ module VX_cache_req_queue ( output wire reqq_full ); - wire [`NUMBER_REQUESTS-1:0] out_per_valids; - wire [`NUMBER_REQUESTS-1:0][31:0] out_per_addr; - wire [`NUMBER_REQUESTS-1:0][31:0] out_per_writedata; + wire [NUMBER_REQUESTS-1:0] out_per_valids; + wire [NUMBER_REQUESTS-1:0][31:0] out_per_addr; + wire [NUMBER_REQUESTS-1:0][31:0] out_per_writedata; wire [4:0] out_per_rd; wire [1:0] out_per_wb; wire [`NW_M1:0] out_per_warp_num; @@ -42,9 +86,9 @@ module VX_cache_req_queue ( wire [2:0] out_per_mem_write; - reg [`NUMBER_REQUESTS-1:0] use_per_valids; - reg [`NUMBER_REQUESTS-1:0][31:0] use_per_addr; - reg [`NUMBER_REQUESTS-1:0][31:0] use_per_writedata; + reg [NUMBER_REQUESTS-1:0] use_per_valids; + reg [NUMBER_REQUESTS-1:0][31:0] use_per_addr; + reg [NUMBER_REQUESTS-1:0][31:0] use_per_writedata; reg [4:0] use_per_rd; reg [1:0] use_per_wb; reg [`NW_M1:0] use_per_warp_num; @@ -52,16 +96,16 @@ module VX_cache_req_queue ( reg [2:0] use_per_mem_write; - wire [`NUMBER_REQUESTS-1:0] qual_valids; - wire [`NUMBER_REQUESTS-1:0][31:0] qual_addr; - wire [`NUMBER_REQUESTS-1:0][31:0] qual_writedata; + wire [NUMBER_REQUESTS-1:0] qual_valids; + wire [NUMBER_REQUESTS-1:0][31:0] qual_addr; + wire [NUMBER_REQUESTS-1:0][31:0] qual_writedata; wire [4:0] qual_rd; wire [1:0] qual_wb; wire [`NW_M1:0] qual_warp_num; wire [2:0] qual_mem_read; wire [2:0] qual_mem_write; - wire[`NUMBER_REQUESTS-1:0] updated_valids; + wire[NUMBER_REQUESTS-1:0] updated_valids; wire o_empty; @@ -71,7 +115,7 @@ module VX_cache_req_queue ( wire push_qual = reqq_push && !reqq_full; wire pop_qual = reqq_pop && use_empty && !out_empty; - VX_generic_queue_ll #(.DATAW( (`NUMBER_REQUESTS * (1+32+32)) + 5 + 2 + (`NW_M1+1) + 3 + 3 ), .SIZE(`REQQ_SIZE)) reqq_queue( + VX_generic_queue_ll #(.DATAW( (NUMBER_REQUESTS * (1+32+32)) + 5 + 2 + (`NW_M1+1) + 3 + 3 ), .SIZE(REQQ_SIZE)) reqq_queue( .clk (clk), .reset (reset), .push (push_qual), @@ -83,7 +127,7 @@ module VX_cache_req_queue ( ); - wire[`NUMBER_REQUESTS-1:0] real_out_per_valids = out_per_valids & {`NUMBER_REQUESTS{~out_empty}}; + wire[NUMBER_REQUESTS-1:0] real_out_per_valids = out_per_valids & {NUMBER_REQUESTS{~out_empty}}; assign qual_valids = use_empty ? real_out_per_valids : out_empty ? 0 : use_per_valids; assign qual_addr = use_empty ? out_per_addr : use_per_addr; @@ -94,9 +138,9 @@ module VX_cache_req_queue ( assign qual_mem_read = use_empty ? out_per_mem_read : use_per_mem_read; assign qual_mem_write = use_empty ? out_per_mem_write : use_per_mem_write; - wire[`vx_clog2(`NUMBER_REQUESTS)-1:0] qual_request_index; + wire[`vx_clog2(NUMBER_REQUESTS)-1:0] qual_request_index; wire qual_has_request; - VX_generic_priority_encoder #(.N(`NUMBER_REQUESTS)) VX_sel_bank( + VX_generic_priority_encoder #(.N(NUMBER_REQUESTS)) VX_sel_bank( .valids(qual_valids), .index (qual_request_index), .found (qual_has_request) diff --git a/rtl/VX_cache/VX_cache_wb_sel_merge.v b/rtl/VX_cache/VX_cache_wb_sel_merge.v index 0898d66e..99048f0a 100644 --- a/rtl/VX_cache/VX_cache_wb_sel_merge.v +++ b/rtl/VX_cache/VX_cache_wb_sel_merge.v @@ -1,43 +1,87 @@ `include "VX_cache_config.v" -module VX_cache_wb_sel_merge ( +module VX_cache_wb_sel_merge + #( + // Size of cache in bytes + parameter CACHE_SIZE_BYTES = 1024, + // Size of line inside a bank in bytes + parameter BANK_LINE_SIZE_BYTES = 16, + // Number of banks {1, 2, 4, 8,...} + parameter NUMBER_BANKS = 8, + // Size of a word in bytes + parameter WORD_SIZE_BYTES = 4, + // Number of Word requests per cycle {1, 2, 4, 8, ...} + parameter NUMBER_REQUESTS = 2, + // Number of cycles to complete stage 1 (read from memory) + parameter STAGE_1_CYCLES = 2, + +// Queues feeding into banks Knobs {1, 2, 4, 8, ...} + + // Core Request Queue Size + parameter REQQ_SIZE = 8, + // Miss Reserv Queue Knob + parameter MRVQ_SIZE = 8, + // Dram Fill Rsp Queue Size + parameter DFPQ_SIZE = 2, + // Snoop Req Queue + parameter SNRQ_SIZE = 8, + +// Queues for writebacks Knobs {1, 2, 4, 8, ...} + // Core Writeback Queue Size + parameter CWBQ_SIZE = 8, + // Dram Writeback Queue Size + parameter DWBQ_SIZE = 4, + // Dram Fill Req Queue Size + parameter DFQQ_SIZE = 8, + // Lower Level Cache Hit Queue Size + parameter LLVQ_SIZE = 16, + + // Fill Invalidator Size {Fill invalidator must be active} + parameter FILL_INVALIDAOR_SIZE = 16, + +// Dram knobs + parameter SIMULATED_DRAM_LATENCY_CYCLES = 10 + + + ) + ( // Per Bank WB - input wire [`NUMBER_BANKS-1:0] per_bank_wb_valid, - input wire [`NUMBER_BANKS-1:0][`vx_clog2(`NUMBER_REQUESTS)-1:0] per_bank_wb_tid, - input wire [`NUMBER_BANKS-1:0][4:0] per_bank_wb_rd, - input wire [`NUMBER_BANKS-1:0][1:0] per_bank_wb_wb, - input wire [`NUMBER_BANKS-1:0][`NW_M1:0] per_bank_wb_warp_num, - input wire [`NUMBER_BANKS-1:0][31:0] per_bank_wb_data, - output wire [`NUMBER_BANKS-1:0] per_bank_wb_pop, + input wire [NUMBER_BANKS-1:0] per_bank_wb_valid, + input wire [NUMBER_BANKS-1:0][`vx_clog2(NUMBER_REQUESTS)-1:0] per_bank_wb_tid, + input wire [NUMBER_BANKS-1:0][4:0] per_bank_wb_rd, + input wire [NUMBER_BANKS-1:0][1:0] per_bank_wb_wb, + input wire [NUMBER_BANKS-1:0][`NW_M1:0] per_bank_wb_warp_num, + input wire [NUMBER_BANKS-1:0][31:0] per_bank_wb_data, + output wire [NUMBER_BANKS-1:0] per_bank_wb_pop, // Core Writeback input wire core_no_wb_slot, - output reg [`NUMBER_REQUESTS-1:0] core_wb_valid, - output reg [`NUMBER_REQUESTS-1:0][31:0] core_wb_readdata, + output reg [NUMBER_REQUESTS-1:0] core_wb_valid, + output reg [NUMBER_REQUESTS-1:0][31:0] core_wb_readdata, output wire [4:0] core_wb_req_rd, output wire [1:0] core_wb_req_wb, output wire [`NW_M1:0] core_wb_warp_num ); - reg [`NUMBER_BANKS-1:0] per_bank_wb_pop_unqual; - assign per_bank_wb_pop = per_bank_wb_pop_unqual & {`NUMBER_BANKS{~core_no_wb_slot}}; + reg [NUMBER_BANKS-1:0] per_bank_wb_pop_unqual; + assign per_bank_wb_pop = per_bank_wb_pop_unqual & {NUMBER_BANKS{~core_no_wb_slot}}; - wire[`NUMBER_BANKS-1:0] bank_wants_wb; + wire[NUMBER_BANKS-1:0] bank_wants_wb; genvar curr_bank; generate - for (curr_bank = 0; curr_bank < `NUMBER_BANKS; curr_bank=curr_bank+1) begin + for (curr_bank = 0; curr_bank < NUMBER_BANKS; curr_bank=curr_bank+1) begin assign bank_wants_wb[curr_bank] = (|per_bank_wb_valid[curr_bank]); end endgenerate - wire [(`vx_clog2(`NUMBER_BANKS))-1:0] main_bank_index; + wire [(`vx_clog2(NUMBER_BANKS))-1:0] main_bank_index; wire found_bank; - VX_generic_priority_encoder #(.N(`NUMBER_BANKS)) VX_sel_bank( + VX_generic_priority_encoder #(.N(NUMBER_BANKS)) VX_sel_bank( .valids(bank_wants_wb), .index (main_bank_index), .found (found_bank) @@ -52,7 +96,7 @@ module VX_cache_wb_sel_merge ( always @(*) begin core_wb_valid = 0; core_wb_readdata = 0; - for (this_bank = 0; this_bank < `NUMBER_BANKS; this_bank = this_bank + 1) begin + for (this_bank = 0; this_bank < NUMBER_BANKS; this_bank = this_bank + 1) begin if (found_bank && (per_bank_wb_valid[this_bank]) && (per_bank_wb_rd[this_bank] == per_bank_wb_rd[main_bank_index]) && (per_bank_wb_warp_num[this_bank] == per_bank_wb_warp_num[main_bank_index])) begin core_wb_valid[per_bank_wb_tid[this_bank]] = 1; core_wb_readdata[per_bank_wb_tid[this_bank]] = per_bank_wb_data[this_bank]; diff --git a/rtl/VX_cache/VX_dcache_llv_resp_bank_sel.v b/rtl/VX_cache/VX_dcache_llv_resp_bank_sel.v index 97dc22d2..61dec330 100644 --- a/rtl/VX_cache/VX_dcache_llv_resp_bank_sel.v +++ b/rtl/VX_cache/VX_dcache_llv_resp_bank_sel.v @@ -1,24 +1,68 @@ `include "VX_cache_config.v" -module VX_dcache_llv_resp_bank_sel ( - output reg [`NUMBER_BANKS-1:0] per_bank_llvq_pop, - input wire[`NUMBER_BANKS-1:0] per_bank_llvq_valid, - input wire[`NUMBER_BANKS-1:0][31:0] per_bank_llvq_res_addr, - input wire[`NUMBER_BANKS-1:0][`BANK_LINE_SIZE_RNG][31:0] per_bank_llvq_res_data, - input wire[`NUMBER_BANKS-1:0][`vx_clog2(`NUMBER_REQUESTS)-1:0] per_bank_llvq_res_tid, +module VX_dcache_llv_resp_bank_sel + #( + // Size of cache in bytes + parameter CACHE_SIZE_BYTES = 1024, + // Size of line inside a bank in bytes + parameter BANK_LINE_SIZE_BYTES = 16, + // Number of banks {1, 2, 4, 8,...} + parameter NUMBER_BANKS = 8, + // Size of a word in bytes + parameter WORD_SIZE_BYTES = 4, + // Number of Word requests per cycle {1, 2, 4, 8, ...} + parameter NUMBER_REQUESTS = 2, + // Number of cycles to complete stage 1 (read from memory) + parameter STAGE_1_CYCLES = 2, + +// Queues feeding into banks Knobs {1, 2, 4, 8, ...} + + // Core Request Queue Size + parameter REQQ_SIZE = 8, + // Miss Reserv Queue Knob + parameter MRVQ_SIZE = 8, + // Dram Fill Rsp Queue Size + parameter DFPQ_SIZE = 2, + // Snoop Req Queue + parameter SNRQ_SIZE = 8, + +// Queues for writebacks Knobs {1, 2, 4, 8, ...} + // Core Writeback Queue Size + parameter CWBQ_SIZE = 8, + // Dram Writeback Queue Size + parameter DWBQ_SIZE = 4, + // Dram Fill Req Queue Size + parameter DFQQ_SIZE = 8, + // Lower Level Cache Hit Queue Size + parameter LLVQ_SIZE = 16, + + // Fill Invalidator Size {Fill invalidator must be active} + parameter FILL_INVALIDAOR_SIZE = 16, + +// Dram knobs + parameter SIMULATED_DRAM_LATENCY_CYCLES = 10 + + + ) + ( + output reg [NUMBER_BANKS-1:0] per_bank_llvq_pop, + input wire[NUMBER_BANKS-1:0] per_bank_llvq_valid, + input wire[NUMBER_BANKS-1:0][31:0] per_bank_llvq_res_addr, + input wire[NUMBER_BANKS-1:0][`BANK_LINE_SIZE_RNG][31:0] per_bank_llvq_res_data, + input wire[NUMBER_BANKS-1:0][`vx_clog2(NUMBER_REQUESTS)-1:0] per_bank_llvq_res_tid, input wire llvq_pop, - output reg[`NUMBER_REQUESTS-1:0] llvq_valid, - output reg[`NUMBER_REQUESTS-1:0][31:0] llvq_res_addr, - output reg[`NUMBER_REQUESTS-1:0][`BANK_LINE_SIZE_RNG][31:0] llvq_res_data + output reg[NUMBER_REQUESTS-1:0] llvq_valid, + output reg[NUMBER_REQUESTS-1:0][31:0] llvq_res_addr, + output reg[NUMBER_REQUESTS-1:0][`BANK_LINE_SIZE_RNG][31:0] llvq_res_data ); - wire [(`vx_clog2(`NUMBER_BANKS))-1:0] main_bank_index; + wire [(`vx_clog2(NUMBER_BANKS))-1:0] main_bank_index; wire found_bank; - VX_generic_priority_encoder #(.N(`NUMBER_BANKS)) VX_sel_bank( + VX_generic_priority_encoder #(.N(NUMBER_BANKS)) VX_sel_bank( .valids(per_bank_llvq_valid), .index (main_bank_index), .found (found_bank) diff --git a/rtl/VX_cache/VX_fill_invalidator.v b/rtl/VX_cache/VX_fill_invalidator.v index 4cf0d79f..decdfb15 100644 --- a/rtl/VX_cache/VX_fill_invalidator.v +++ b/rtl/VX_cache/VX_fill_invalidator.v @@ -1,6 +1,50 @@ `include "VX_cache_config.v" -module VX_fill_invalidator ( +module VX_fill_invalidator + #( + // Size of cache in bytes + parameter CACHE_SIZE_BYTES = 1024, + // Size of line inside a bank in bytes + parameter BANK_LINE_SIZE_BYTES = 16, + // Number of banks {1, 2, 4, 8,...} + parameter NUMBER_BANKS = 8, + // Size of a word in bytes + parameter WORD_SIZE_BYTES = 4, + // Number of Word requests per cycle {1, 2, 4, 8, ...} + parameter NUMBER_REQUESTS = 2, + // Number of cycles to complete stage 1 (read from memory) + parameter STAGE_1_CYCLES = 2, + +// Queues feeding into banks Knobs {1, 2, 4, 8, ...} + + // Core Request Queue Size + parameter REQQ_SIZE = 8, + // Miss Reserv Queue Knob + parameter MRVQ_SIZE = 8, + // Dram Fill Rsp Queue Size + parameter DFPQ_SIZE = 2, + // Snoop Req Queue + parameter SNRQ_SIZE = 8, + +// Queues for writebacks Knobs {1, 2, 4, 8, ...} + // Core Writeback Queue Size + parameter CWBQ_SIZE = 8, + // Dram Writeback Queue Size + parameter DWBQ_SIZE = 4, + // Dram Fill Req Queue Size + parameter DFQQ_SIZE = 8, + // Lower Level Cache Hit Queue Size + parameter LLVQ_SIZE = 16, + + // Fill Invalidator Size {Fill invalidator must be active} + parameter FILL_INVALIDAOR_SIZE = 16, + +// Dram knobs + parameter SIMULATED_DRAM_LATENCY_CYCLES = 10 + + + ) + ( input wire clk, input wire reset, @@ -14,25 +58,25 @@ module VX_fill_invalidator ( ); - `ifndef FILL_INVALIDATOR_ACTIVE + if (FILL_INVALIDAOR_SIZE == 0) begin assign invalidate_fill = 0; - `else + end else begin - reg[`FILL_INVALIDAOR_SIZE-1:0] fills_active; - reg[`FILL_INVALIDAOR_SIZE-1:0][31:0] fills_address; + reg[FILL_INVALIDAOR_SIZE-1:0] fills_active; + reg[FILL_INVALIDAOR_SIZE-1:0][31:0] fills_address; reg success_found; - reg[(`vx_clog2(`FILL_INVALIDAOR_SIZE))-1:0] success_index; + reg[(`vx_clog2(FILL_INVALIDAOR_SIZE))-1:0] success_index; integer curr_fill; always @(*) begin invalidate_fill = 0; success_found = 0; success_index = 0; - for (curr_fill = 0; curr_fill < `FILL_INVALIDAOR_SIZE; curr_fill=curr_fill+1) begin + for (curr_fill = 0; curr_fill < FILL_INVALIDAOR_SIZE; curr_fill=curr_fill+1) begin if (fill_addr[31:`LINE_SELECT_ADDR_START] == fills_address[curr_fill][31:`LINE_SELECT_ADDR_START]) begin if (possible_fill && fills_active[curr_fill]) begin @@ -50,39 +94,39 @@ module VX_fill_invalidator ( - wire [(`vx_clog2(`FILL_INVALIDAOR_SIZE))-1:0] enqueue_index; - wire enqueue_found; + wire [(`vx_clog2(FILL_INVALIDAOR_SIZE))-1:0] enqueue_index; + wire enqueue_found; - VX_generic_priority_encoder #(.N(`FILL_INVALIDAOR_SIZE)) VX_sel_bank( - .valids(fills_active), - .index (enqueue_index), - .found (enqueue_found) - ); + VX_generic_priority_encoder #(.N(FILL_INVALIDAOR_SIZE)) VX_sel_bank( + .valids(fills_active), + .index (enqueue_index), + .found (enqueue_found) + ); - reg[`FILL_INVALIDAOR_SIZE-1:0] new_valids; + reg[FILL_INVALIDAOR_SIZE-1:0] new_valids; - always @(posedge clk) begin - if (reset) begin - fills_active <= 0; - fills_address <= 0; - end else begin - if (enqueue_found && !invalidate_fill) begin - fills_active[enqueue_index] <= 1; - fills_address[enqueue_index] <= fill_addr; + always @(posedge clk) begin + if (reset) begin + fills_active <= 0; + fills_address <= 0; + end else begin + if (enqueue_found && !invalidate_fill) begin + fills_active[enqueue_index] <= 1; + fills_address[enqueue_index] <= fill_addr; + end + + if (success_found) begin + fills_active[success_index] <= 0; + end + end - - if (success_found) begin - fills_active[success_index] <= 0; - end - end + + end - `endif - - endmodule \ No newline at end of file diff --git a/rtl/VX_cache/VX_tag_data_access.v b/rtl/VX_cache/VX_tag_data_access.v index e96d4eea..2ff175cd 100644 --- a/rtl/VX_cache/VX_tag_data_access.v +++ b/rtl/VX_cache/VX_tag_data_access.v @@ -1,6 +1,50 @@ `include "VX_cache_config.v" -module VX_tag_data_access ( +module VX_tag_data_access + #( + // Size of cache in bytes + parameter CACHE_SIZE_BYTES = 1024, + // Size of line inside a bank in bytes + parameter BANK_LINE_SIZE_BYTES = 16, + // Number of banks {1, 2, 4, 8,...} + parameter NUMBER_BANKS = 8, + // Size of a word in bytes + parameter WORD_SIZE_BYTES = 4, + // Number of Word requests per cycle {1, 2, 4, 8, ...} + parameter NUMBER_REQUESTS = 2, + // Number of cycles to complete stage 1 (read from memory) + parameter STAGE_1_CYCLES = 2, + +// Queues feeding into banks Knobs {1, 2, 4, 8, ...} + + // Core Request Queue Size + parameter REQQ_SIZE = 8, + // Miss Reserv Queue Knob + parameter MRVQ_SIZE = 8, + // Dram Fill Rsp Queue Size + parameter DFPQ_SIZE = 2, + // Snoop Req Queue + parameter SNRQ_SIZE = 8, + +// Queues for writebacks Knobs {1, 2, 4, 8, ...} + // Core Writeback Queue Size + parameter CWBQ_SIZE = 8, + // Dram Writeback Queue Size + parameter DWBQ_SIZE = 4, + // Dram Fill Req Queue Size + parameter DFQQ_SIZE = 8, + // Lower Level Cache Hit Queue Size + parameter LLVQ_SIZE = 16, + + // Fill Invalidator Size {Fill invalidator must be active} + parameter FILL_INVALIDAOR_SIZE = 16, + +// Dram knobs + parameter SIMULATED_DRAM_LATENCY_CYCLES = 10 + + + ) + ( input wire clk, input wire reset, input wire stall, @@ -27,12 +71,12 @@ module VX_tag_data_access ( ); - reg[`BANK_LINE_SIZE_RNG][31:0] readdata_st[`STAGE_1_CYCLES-1:0]; + reg[`BANK_LINE_SIZE_RNG][31:0] readdata_st[STAGE_1_CYCLES-1:0]; - reg read_valid_st1c[`STAGE_1_CYCLES-1:0]; - reg read_dirty_st1c[`STAGE_1_CYCLES-1:0]; - reg[`TAG_SELECT_SIZE_RNG] read_tag_st1c [`STAGE_1_CYCLES-1:0]; - reg[`BANK_LINE_SIZE_RNG][31:0] read_data_st1c [`STAGE_1_CYCLES-1:0]; + reg read_valid_st1c[STAGE_1_CYCLES-1:0]; + reg read_dirty_st1c[STAGE_1_CYCLES-1:0]; + reg[`TAG_SELECT_SIZE_RNG] read_tag_st1c [STAGE_1_CYCLES-1:0]; + reg[`BANK_LINE_SIZE_RNG][31:0] read_data_st1c [STAGE_1_CYCLES-1:0]; wire qual_read_valid_st1; @@ -50,7 +94,26 @@ module VX_tag_data_access ( wire fill_sent; wire invalidate_line; - VX_tag_data_structure VX_tag_data_structure( + VX_tag_data_structure #( + .CACHE_SIZE_BYTES (CACHE_SIZE_BYTES), + .BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES), + .NUMBER_BANKS (NUMBER_BANKS), + .WORD_SIZE_BYTES (WORD_SIZE_BYTES), + .NUMBER_REQUESTS (NUMBER_REQUESTS), + .STAGE_1_CYCLES (STAGE_1_CYCLES), + .REQQ_SIZE (REQQ_SIZE), + .MRVQ_SIZE (MRVQ_SIZE), + .DFPQ_SIZE (DFPQ_SIZE), + .SNRQ_SIZE (SNRQ_SIZE), + .CWBQ_SIZE (CWBQ_SIZE), + .DWBQ_SIZE (DWBQ_SIZE), + .DFQQ_SIZE (DFQQ_SIZE), + .LLVQ_SIZE (LLVQ_SIZE), + .FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE), + .SIMULATED_DRAM_LATENCY_CYCLES(SIMULATED_DRAM_LATENCY_CYCLES) + ) + VX_tag_data_structure + ( .clk (clk), .reset (reset), @@ -79,7 +142,7 @@ module VX_tag_data_access ( genvar curr_stage; generate - for (curr_stage = 1; curr_stage < `STAGE_1_CYCLES; curr_stage = curr_stage + 1) begin + for (curr_stage = 1; curr_stage < STAGE_1_CYCLES; curr_stage = curr_stage + 1) begin VX_generic_register #(.N( 1 + 1 + `TAG_SELECT_NUM_BITS + (`BANK_LINE_SIZE_WORDS*32) )) s0_1_cc ( .clk (clk), .reset(reset), @@ -92,13 +155,13 @@ module VX_tag_data_access ( endgenerate - assign use_read_valid_st1e = read_valid_st1c[`STAGE_1_CYCLES-1]; - assign use_read_dirty_st1e = read_dirty_st1c[`STAGE_1_CYCLES-1]; - assign use_read_tag_st1e = read_tag_st1c [`STAGE_1_CYCLES-1]; + assign use_read_valid_st1e = read_valid_st1c[STAGE_1_CYCLES-1]; + assign use_read_dirty_st1e = read_dirty_st1c[STAGE_1_CYCLES-1]; + assign use_read_tag_st1e = read_tag_st1c [STAGE_1_CYCLES-1]; genvar curr_w; - for (curr_w = 0; curr_w < `BANK_LINE_SIZE_WORDS; curr_w = curr_w+1) assign use_read_data_st1e[curr_w][31:0] = read_data_st1c[`STAGE_1_CYCLES-1][curr_w][31:0]; - // assign use_read_data_st1e = read_data_st1c [`STAGE_1_CYCLES-1]; + for (curr_w = 0; curr_w < `BANK_LINE_SIZE_WORDS; curr_w = curr_w+1) assign use_read_data_st1e[curr_w][31:0] = read_data_st1c[STAGE_1_CYCLES-1][curr_w][31:0]; + // assign use_read_data_st1e = read_data_st1c [STAGE_1_CYCLES-1]; /////////////////////// LOAD LOGIC /////////////////// @@ -116,12 +179,12 @@ module VX_tag_data_access ( wire b2 = (byte_select == 2); wire b3 = (byte_select == 3); - wire[31:0] w0 = read_data_st1c[`STAGE_1_CYCLES-1][0][31:0]; - wire[31:0] w1 = read_data_st1c[`STAGE_1_CYCLES-1][1][31:0]; - wire[31:0] w2 = read_data_st1c[`STAGE_1_CYCLES-1][2][31:0]; - wire[31:0] w3 = read_data_st1c[`STAGE_1_CYCLES-1][3][31:0]; + wire[31:0] w0 = read_data_st1c[STAGE_1_CYCLES-1][0][31:0]; + wire[31:0] w1 = read_data_st1c[STAGE_1_CYCLES-1][1][31:0]; + wire[31:0] w2 = read_data_st1c[STAGE_1_CYCLES-1][2][31:0]; + wire[31:0] w3 = read_data_st1c[STAGE_1_CYCLES-1][3][31:0]; - wire[31:0] data_unmod = read_data_st1c[`STAGE_1_CYCLES-1][block_offset][31:0]; + wire[31:0] data_unmod = read_data_st1c[STAGE_1_CYCLES-1][block_offset][31:0]; wire[31:0] data_unQual = (b0 || lw) ? (data_unmod) : b1 ? (data_unmod >> 8) : diff --git a/rtl/VX_cache/VX_tag_data_structure.v b/rtl/VX_cache/VX_tag_data_structure.v index 3a5f822b..c817698d 100644 --- a/rtl/VX_cache/VX_tag_data_structure.v +++ b/rtl/VX_cache/VX_tag_data_structure.v @@ -1,6 +1,50 @@ `include "VX_cache_config.v" -module VX_tag_data_structure ( +module VX_tag_data_structure + #( + // Size of cache in bytes + parameter CACHE_SIZE_BYTES = 1024, + // Size of line inside a bank in bytes + parameter BANK_LINE_SIZE_BYTES = 16, + // Number of banks {1, 2, 4, 8,...} + parameter NUMBER_BANKS = 8, + // Size of a word in bytes + parameter WORD_SIZE_BYTES = 4, + // Number of Word requests per cycle {1, 2, 4, 8, ...} + parameter NUMBER_REQUESTS = 2, + // Number of cycles to complete stage 1 (read from memory) + parameter STAGE_1_CYCLES = 2, + +// Queues feeding into banks Knobs {1, 2, 4, 8, ...} + + // Core Request Queue Size + parameter REQQ_SIZE = 8, + // Miss Reserv Queue Knob + parameter MRVQ_SIZE = 8, + // Dram Fill Rsp Queue Size + parameter DFPQ_SIZE = 2, + // Snoop Req Queue + parameter SNRQ_SIZE = 8, + +// Queues for writebacks Knobs {1, 2, 4, 8, ...} + // Core Writeback Queue Size + parameter CWBQ_SIZE = 8, + // Dram Writeback Queue Size + parameter DWBQ_SIZE = 4, + // Dram Fill Req Queue Size + parameter DFQQ_SIZE = 8, + // Lower Level Cache Hit Queue Size + parameter LLVQ_SIZE = 16, + + // Fill Invalidator Size {Fill invalidator must be active} + parameter FILL_INVALIDAOR_SIZE = 16, + +// Dram knobs + parameter SIMULATED_DRAM_LATENCY_CYCLES = 10 + + + ) + ( input wire clk, input wire reset, diff --git a/rtl/VX_define.v b/rtl/VX_define.v index 45efae34..b2938dcf 100644 --- a/rtl/VX_define.v +++ b/rtl/VX_define.v @@ -181,62 +181,6 @@ `define ICACHE_TAG_SIZE_END (32-(`ICACHE_IND_ED+1)-1) `define ICACHE_ADDR_TAG_START (`ICACHE_IND_ED+1) `define ICACHE_ADDR_TAG_END 31 - -//Cache configurations -//Bytes -`define DCACHE_SIZE 4096 -`define DCACHE_WAYS 2 - -//Bytes -`define DCACHE_BLOCK 64 -`define DCACHE_BANKS 4 -`define DCACHE_LOG_NUM_BANKS $clog2(`DCACHE_BANKS) -`define DCACHE_NUM_WORDS_PER_BLOCK (`DCACHE_BLOCK / (`DCACHE_BANKS * 4)) -`define DCACHE_NUM_REQ `NT -`define DCACHE_LOG_NUM_REQ $clog2(`DCACHE_NUM_REQ) - -//set this to 1 if CACHE_WAYS is 1 -`define DCACHE_WAY_INDEX $clog2(`DCACHE_WAYS) -//`define DCACHE_WAY_INDEX 1 -`define DCACHE_BLOCK_PER_BANK (`DCACHE_BLOCK / `DCACHE_BANKS) - -// Offset -`define DCACHE_OFFSET_NB ($clog2(`DCACHE_NUM_WORDS_PER_BLOCK)) - -`define DCACHE_ADDR_OFFSET_ST (2+$clog2(`DCACHE_BANKS)) -`define DCACHE_ADDR_OFFSET_ED (`DCACHE_ADDR_OFFSET_ST+(`DCACHE_OFFSET_NB)-1) - - -`define DCACHE_ADDR_OFFSET_RNG `DCACHE_ADDR_OFFSET_ED:`DCACHE_ADDR_OFFSET_ST -`define DCACHE_OFFSET_SIZE_RNG ($clog2(`DCACHE_NUM_WORDS_PER_BLOCK)-1):0 -`define DCACHE_OFFSET_ST 0 -`define DCACHE_OFFSET_ED ($clog2(`DCACHE_NUM_WORDS_PER_BLOCK)-1) - -// Index -// `define DCACHE_NUM_IND (`DCACHE_SIZE / (`DCACHE_WAYS * `DCACHE_BLOCK_PER_BANK)) -`define DCACHE_NUM_IND (`DCACHE_SIZE / (`DCACHE_WAYS * `DCACHE_BLOCK)) -`define DCACHE_IND_NB ($clog2(`DCACHE_NUM_IND)) - -`define DCACHE_IND_ST (`DCACHE_ADDR_OFFSET_ED+1) -`define DCACHE_IND_ED (`DCACHE_IND_ST+`DCACHE_IND_NB-1) - -`define DCACHE_ADDR_IND_RNG `DCACHE_IND_ED:`DCACHE_IND_ST -`define DCACHE_IND_SIZE_RNG `DCACHE_IND_NB-1:0 - -`define DCACHE_IND_SIZE_START 0 -`define DCACHE_IND_SIZE_END `DCACHE_IND_NB-1 - - -// Tag -`define DCACHE_ADDR_TAG_RNG 31:(`DCACHE_IND_ED+1) -`define DCACHE_TAG_SIZE_RNG (32-(`DCACHE_IND_ED+1)-1):0 -`define DCACHE_TAG_SIZE_START 0 -`define DCACHE_TAG_SIZE_END (32-(`DCACHE_IND_ED+1)-1) -`define DCACHE_ADDR_TAG_START (`DCACHE_IND_ED+1) -`define DCACHE_ADDR_TAG_END 31 - -// Mask -`define DCACHE_MEM_REQ_ADDR_MASK (32'hffffffff - (`DCACHE_BLOCK-1)) `define ICACHE_MEM_REQ_ADDR_MASK (32'hffffffff - (`ICACHE_BLOCK-1)) /////// @@ -264,4 +208,63 @@ `define SHARED_MEMORY_INDEX_OFFSET_ST (`SHARED_MEMORY_BLOCK_OFFSET_ED + 1) `define SHARED_MEMORY_INDEX_OFFSET_ED (`SHARED_MEMORY_INDEX_OFFSET_ST + $clog2(`SHARED_MEMORY_HEIGHT)-1) + + + + + +// ========================================= Dcache Configurable Knobs ========================================= + +// General Cache Knobs + // Size of cache in bytes + `define DCACHE_SIZE_BYTES 1024 + // Size of line inside a bank in bytes + `define DBANK_LINE_SIZE_BYTES 16 + // Number of banks {1, 2, 4, 8,...} + `define DNUMBER_BANKS 8 + // Size of a word in bytes + `define DWORD_SIZE_BYTES 4 + // Number of Word requests per cycle {1, 2, 4, 8, ...} + `define DNUMBER_REQUESTS `NT + // Number of cycles to complete stage 1 (read from memory) + `define DSTAGE_1_CYCLES 2 + + // Bank Number of words in a line + `define DBANK_LINE_SIZE_WORDS (`DBANK_LINE_SIZE_BYTES / `DNUMBER_BANKS) + `define DBANK_LINE_SIZE_RNG `DBANK_LINE_SIZE_WORDS-1:0 +// Queues feeding into banks Knobs {1, 2, 4, 8, ...} + + // Core Request Queue Size + `define DREQQ_SIZE `NT*`NW + // Miss Reserv Queue Knob + `define DMRVQ_SIZE `DREQQ_SIZE + // Dram Fill Rsp Queue Size + `define DDFPQ_SIZE 2 + // Snoop Req Queue + `define DSNRQ_SIZE 8 + +// Queues for writebacks Knobs {1, 2, 4, 8, ...} + // Core Writeback Queue Size + `define DCWBQ_SIZE `DREQQ_SIZE + // Dram Writeback Queue Size + `define DDWBQ_SIZE 4 + // Dram Fill Req Queue Size + `define DDFQQ_SIZE `DREQQ_SIZE + // Lower Level Cache Hit Queue Size + `define DLLVQ_SIZE 0 + + // Fill Invalidator Size {Fill invalidator must be active} + `define DFILL_INVALIDAOR_SIZE 16 + +// Dram knobs + `define DSIMULATED_DRAM_LATENCY_CYCLES 10 + +// ========================================= Dcache Configurable Knobs ========================================= + + + + + + + `endif diff --git a/rtl/VX_dmem_controller.v b/rtl/VX_dmem_controller.v index 18226a3b..0a3cecd4 100644 --- a/rtl/VX_dmem_controller.v +++ b/rtl/VX_dmem_controller.v @@ -3,16 +3,18 @@ module VX_dmem_controller ( input wire clk, input wire reset, - // MEM-RAM + // Dcache VX_gpu_dcache_dram_req_inter VX_gpu_dcache_dram_req, VX_gpu_dcache_dram_res_inter VX_gpu_dcache_dram_res, + VX_gpu_dcache_res_inter VX_dcache_rsp, + VX_gpu_dcache_req_inter VX_dcache_req, + + VX_dram_req_rsp_inter VX_dram_req_rsp_icache, // MEM-Processor VX_icache_request_inter VX_icache_req, - VX_icache_response_inter VX_icache_rsp, - VX_gpu_dcache_req_inter VX_dcache_req, - VX_gpu_dcache_res_inter VX_dcache_rsp + VX_icache_response_inter VX_icache_rsp ); wire to_shm = VX_dcache_req.core_req_addr[0][31:24] == 8'hFF; @@ -42,7 +44,7 @@ module VX_dmem_controller ( VX_shared_memory #( .SM_SIZE (`SHARED_MEMORY_SIZE), - .SM_BANKS (`SHARED_MEMORY_BANKS), + .SM_BANKS (`SHARED_MEMORY_BANKS), .SM_BYTES_PER_READ (`SHARED_MEMORY_BYTES_PER_READ), .SM_WORDS_PER_READ (`SHARED_MEMORY_WORDS_PER_READ), .SM_LOG_WORDS_PER_READ (`SHARED_MEMORY_LOG_WORDS_PER_READ), @@ -71,7 +73,26 @@ module VX_dmem_controller ( ); - VX_cache gpu_dcache( + VX_cache #( + .CACHE_SIZE_BYTES (`DCACHE_SIZE_BYTES), + .BANK_LINE_SIZE_BYTES (`DBANK_LINE_SIZE_BYTES), + .NUMBER_BANKS (`DNUMBER_BANKS), + .WORD_SIZE_BYTES (`DWORD_SIZE_BYTES), + .NUMBER_REQUESTS (`DNUMBER_REQUESTS), + .STAGE_1_CYCLES (`DSTAGE_1_CYCLES), + .REQQ_SIZE (`DREQQ_SIZE), + .MRVQ_SIZE (`DMRVQ_SIZE), + .DFPQ_SIZE (`DDFPQ_SIZE), + .SNRQ_SIZE (`DSNRQ_SIZE), + .CWBQ_SIZE (`DCWBQ_SIZE), + .DWBQ_SIZE (`DDWBQ_SIZE), + .DFQQ_SIZE (`DDFQQ_SIZE), + .LLVQ_SIZE (`DLLVQ_SIZE), + .FILL_INVALIDAOR_SIZE (`DFILL_INVALIDAOR_SIZE), + .SIMULATED_DRAM_LATENCY_CYCLES(`DSIMULATED_DRAM_LATENCY_CYCLES) + ) + gpu_dcache + ( .clk (clk), .reset (reset), diff --git a/rtl/VX_generic_queue_ll.v b/rtl/VX_generic_queue_ll.v index d92ff164..a54a2403 100644 --- a/rtl/VX_generic_queue_ll.v +++ b/rtl/VX_generic_queue_ll.v @@ -16,93 +16,103 @@ module VX_generic_queue_ll output wire full ); - reg[DATAW-1:0] data[SIZE-1:0], curr_r, head_r; - reg[$clog2(SIZE+1)-1:0] size_r; - reg[$clog2(SIZE)-1:0] wr_ctr_r; - reg[$clog2(SIZE)-1:0] rd_ptr_r, rd_next_ptr_r; - reg empty_r, full_r, bypass_r; - wire reading, writing; - - assign reading = pop && !empty; - assign writing = push && !full; - - if (SIZE == 1) begin - always @(posedge clk) begin - if (reset) begin - size_r <= 0; - end else begin - if (writing && !reading) begin - size_r <= 1; - end else if (reading && !writing) begin - size_r <= 0; - end - - if (writing) begin - head_r <= in_data; - end - end - end - - assign out_data = head_r; - assign empty = (size_r == 0); - assign full = (size_r != 0) && !pop; + if (SIZE == 0) begin + assign empty = 1; + assign out_data = 0; + assign full = 0; end else begin - always @(posedge clk) begin - if (reset) begin - wr_ctr_r <= 0; - end else begin - if (writing) - wr_ctr_r <= wr_ctr_r + 1; - end - end - always @(posedge clk) begin - if (reset) begin - size_r <= 0; - empty_r <= 1; - full_r <= 0; - end else begin - if (writing && !reading) begin - size_r <= size_r + 1; - empty_r <= 0; - if (size_r == SIZE-1) - full_r <= 1; - end else if (reading && !writing) begin - size_r <= size_r - 1; - if (size_r == 1) - empty_r <= 1; - full_r <= 0; - end - end - end - - always @(posedge clk) begin - if (reset) begin - rd_ptr_r <= 0; - rd_next_ptr_r <= 1; - bypass_r <= 0; - end else begin - if (reading) begin - if (SIZE == 2) begin - rd_ptr_r <= rd_next_ptr_r; - rd_next_ptr_r <= ~rd_next_ptr_r; - end else if (SIZE > 2) begin - rd_ptr_r <= rd_next_ptr_r; - rd_next_ptr_r <= rd_ptr_r + 2; + reg[DATAW-1:0] data[SIZE-1:0], curr_r, head_r; + reg[$clog2(SIZE+1)-1:0] size_r; + reg[$clog2(SIZE)-1:0] wr_ctr_r; + reg[$clog2(SIZE)-1:0] rd_ptr_r, rd_next_ptr_r; + reg empty_r, full_r, bypass_r; + wire reading, writing; + + assign reading = pop && !empty; + assign writing = push && !full; + + if (SIZE == 1) begin + always @(posedge clk) begin + if (reset) begin + size_r <= 0; + end else begin + if (writing && !reading) begin + size_r <= 1; + end else if (reading && !writing) begin + size_r <= 0; + end + + if (writing) begin + head_r <= in_data; end end + end - if (!(!reading && bypass_r)) begin - bypass_r <= writing && (empty_r || (1 == size_r && reading)); - curr_r <= in_data; - end - head_r <= data[reading ? rd_next_ptr_r : rd_ptr_r]; + assign out_data = head_r; + assign empty = (size_r == 0); + assign full = (size_r != 0) && !pop; + end else begin + always @(posedge clk) begin + if (reset) begin + wr_ctr_r <= 0; + end else begin + if (writing) + wr_ctr_r <= wr_ctr_r + 1; + end end + + always @(posedge clk) begin + if (reset) begin + size_r <= 0; + empty_r <= 1; + full_r <= 0; + end else begin + if (writing && !reading) begin + size_r <= size_r + 1; + empty_r <= 0; + if (size_r == SIZE-1) + full_r <= 1; + end else if (reading && !writing) begin + size_r <= size_r - 1; + if (size_r == 1) + empty_r <= 1; + full_r <= 0; + end + end + end + + always @(posedge clk) begin + if (reset) begin + rd_ptr_r <= 0; + rd_next_ptr_r <= 1; + bypass_r <= 0; + end else begin + if (reading) begin + if (SIZE == 2) begin + rd_ptr_r <= rd_next_ptr_r; + rd_next_ptr_r <= ~rd_next_ptr_r; + end else if (SIZE > 2) begin + rd_ptr_r <= rd_next_ptr_r; + rd_next_ptr_r <= rd_ptr_r + 2; + end + end + + if (!(!reading && bypass_r)) begin + bypass_r <= writing && (empty_r || (1 == size_r && reading)); + curr_r <= in_data; + end + head_r <= data[reading ? rd_next_ptr_r : rd_ptr_r]; + end + end + + assign out_data = bypass_r ? curr_r : head_r; + assign empty = empty_r; + assign full = full_r; end - assign out_data = bypass_r ? curr_r : head_r; - assign empty = empty_r; - assign full = full_r; end + + endmodule \ No newline at end of file diff --git a/rtl/Vortex.v b/rtl/Vortex.v index 78ffa535..cdfa50c2 100644 --- a/rtl/Vortex.v +++ b/rtl/Vortex.v @@ -2,13 +2,6 @@ `include "VX_cache_config.v" module Vortex - /*#( - parameter CACHE_SIZE = 4096, // Bytes - parameter CACHE_WAYS = 2, - parameter CACHE_BLOCK = 128, // Bytes - parameter CACHE_BANKS = 8, - parameter NUM_WORDS_PER_BLOCK = 4 - )*/ ( input wire clk, input wire reset, @@ -24,14 +17,14 @@ module Vortex output wire dram_req_read, output wire [31:0] dram_req_addr, output wire [31:0] dram_req_size, - output wire [31:0] dram_req_data[`BANK_LINE_SIZE_RNG], + output wire [31:0] dram_req_data[`DBANK_LINE_SIZE_RNG], output wire [31:0] dram_expected_lat, // DRAM Dcache Res output wire dram_fill_accept, input wire dram_fill_rsp, input wire [31:0] dram_fill_rsp_addr, - input wire [31:0] dram_fill_rsp_data[`BANK_LINE_SIZE_RNG], + input wire [31:0] dram_fill_rsp_data[`DBANK_LINE_SIZE_RNG], // Req I Mem @@ -68,11 +61,11 @@ module Vortex // Dcache Interface - VX_gpu_dcache_res_inter VX_dcache_rsp(); - VX_gpu_dcache_req_inter VX_dcache_req(); + VX_gpu_dcache_res_inter #(.NUMBER_REQUESTS(`DNUMBER_REQUESTS)) VX_dcache_rsp(); + VX_gpu_dcache_req_inter #(.NUMBER_REQUESTS(`DNUMBER_REQUESTS)) VX_dcache_req(); - VX_gpu_dcache_dram_req_inter VX_gpu_dcache_dram_req(); - VX_gpu_dcache_dram_res_inter VX_gpu_dcache_dram_res(); + VX_gpu_dcache_dram_req_inter #(.BANK_LINE_SIZE_WORDS(`DBANK_LINE_SIZE_WORDS)) VX_gpu_dcache_dram_req(); + VX_gpu_dcache_dram_res_inter #(.BANK_LINE_SIZE_WORDS(`DBANK_LINE_SIZE_WORDS)) VX_gpu_dcache_dram_res(); assign VX_gpu_dcache_dram_res.dram_fill_rsp = dram_fill_rsp; @@ -83,12 +76,12 @@ module Vortex assign dram_req_read = VX_gpu_dcache_dram_req.dram_req_read; assign dram_req_addr = VX_gpu_dcache_dram_req.dram_req_addr; assign dram_req_size = VX_gpu_dcache_dram_req.dram_req_size; - assign dram_expected_lat = `SIMULATED_DRAM_LATENCY_CYCLES; + assign dram_expected_lat = `DSIMULATED_DRAM_LATENCY_CYCLES; assign dram_fill_accept = VX_gpu_dcache_dram_req.dram_fill_accept; genvar wordy; generate - for (wordy = 0; wordy < `BANK_LINE_SIZE_WORDS; wordy=wordy+1) begin + for (wordy = 0; wordy < `DBANK_LINE_SIZE_WORDS; wordy=wordy+1) begin assign VX_gpu_dcache_dram_res.dram_fill_rsp_data[wordy] = dram_fill_rsp_data[wordy]; assign dram_req_data[wordy] = VX_gpu_dcache_dram_req.dram_req_data[wordy]; end diff --git a/rtl/interfaces/VX_gpu_dcache_dram_req_inter.v b/rtl/interfaces/VX_gpu_dcache_dram_req_inter.v index ccc58dc6..c088b553 100644 --- a/rtl/interfaces/VX_gpu_dcache_dram_req_inter.v +++ b/rtl/interfaces/VX_gpu_dcache_dram_req_inter.v @@ -6,7 +6,11 @@ `define VX_GPU_DRAM_DCACHE_REQ -interface VX_gpu_dcache_dram_req_inter (); +interface VX_gpu_dcache_dram_req_inter + #( + parameter BANK_LINE_SIZE_WORDS = 2 + ) + (); // DRAM Request wire dram_req; @@ -14,7 +18,7 @@ interface VX_gpu_dcache_dram_req_inter (); wire dram_req_read; wire [31:0] dram_req_addr; wire [31:0] dram_req_size; - wire [`BANK_LINE_SIZE_RNG][31:0] dram_req_data; + wire [BANK_LINE_SIZE_WORDS-1:0][31:0] dram_req_data; // Snoop wire dram_because_of_snp; diff --git a/rtl/interfaces/VX_gpu_dcache_dram_res_inter.v b/rtl/interfaces/VX_gpu_dcache_dram_res_inter.v index 24ba4dc1..a6bd0ff8 100644 --- a/rtl/interfaces/VX_gpu_dcache_dram_res_inter.v +++ b/rtl/interfaces/VX_gpu_dcache_dram_res_inter.v @@ -7,11 +7,15 @@ `define VX_GPU_DRAM_DCACHE_RES -interface VX_gpu_dcache_dram_res_inter (); +interface VX_gpu_dcache_dram_res_inter + #( + parameter BANK_LINE_SIZE_WORDS = 2 + ) + (); // DRAM Rsponse wire dram_fill_rsp; wire [31:0] dram_fill_rsp_addr; - wire [`BANK_LINE_SIZE_RNG][31:0] dram_fill_rsp_data; + wire [BANK_LINE_SIZE_WORDS-1:0][31:0] dram_fill_rsp_data; endinterface diff --git a/rtl/interfaces/VX_gpu_dcache_req_inter.v b/rtl/interfaces/VX_gpu_dcache_req_inter.v index 50ac04e7..003ea4c1 100644 --- a/rtl/interfaces/VX_gpu_dcache_req_inter.v +++ b/rtl/interfaces/VX_gpu_dcache_req_inter.v @@ -6,12 +6,16 @@ `define VX_GPU_DCACHE_REQ -interface VX_gpu_dcache_req_inter (); +interface VX_gpu_dcache_req_inter + #( + parameter NUMBER_REQUESTS = 32 + ) + (); // Core Request - wire [`NUMBER_REQUESTS-1:0] core_req_valid; - wire [`NUMBER_REQUESTS-1:0][31:0] core_req_addr; - wire [`NUMBER_REQUESTS-1:0][31:0] core_req_writedata; + wire [NUMBER_REQUESTS-1:0] core_req_valid; + wire [NUMBER_REQUESTS-1:0][31:0] core_req_addr; + wire [NUMBER_REQUESTS-1:0][31:0] core_req_writedata; wire [2:0] core_req_mem_read; wire [2:0] core_req_mem_write; wire [4:0] core_req_rd; diff --git a/rtl/interfaces/VX_gpu_dcache_res_inter.v b/rtl/interfaces/VX_gpu_dcache_res_inter.v index 2b5cbbbd..bd32e801 100644 --- a/rtl/interfaces/VX_gpu_dcache_res_inter.v +++ b/rtl/interfaces/VX_gpu_dcache_res_inter.v @@ -6,14 +6,18 @@ `define VX_GPU_DCACHE_RES -interface VX_gpu_dcache_res_inter (); +interface VX_gpu_dcache_res_inter + #( + parameter NUMBER_REQUESTS = 32 + ) + (); // Cache WB - wire [`NUMBER_REQUESTS-1:0] core_wb_valid; + wire [NUMBER_REQUESTS-1:0] core_wb_valid; wire [4:0] core_wb_req_rd; wire [1:0] core_wb_req_wb; wire [`NW_M1:0] core_wb_warp_num; - wire [`NUMBER_REQUESTS-1:0][31:0] core_wb_readdata; + wire [NUMBER_REQUESTS-1:0][31:0] core_wb_readdata; // Cache Full wire delay_req;