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opae fixes

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This commit is contained in:
Blaise Tine
2020-05-06 21:14:53 -07:00
parent 59cc0d5be9
commit de9fc68ccc
14 changed files with 249 additions and 170 deletions
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12
hw/rtl/VX_define.vh
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@@ -52,6 +52,16 @@
///////////////////////////////////////////////////////////////////////////////
`define BYTE_EN_NO 3'h7
`define BYTE_EN_LB 3'h0
`define BYTE_EN_LH 3'h1
`define BYTE_EN_LW 3'h2
`define BYTE_EN_HB 3'h4
`define BYTE_EN_HH 3'h5
`define BYTE_EN_BITS 3
///////////////////////////////////////////////////////////////////////////////
`define INST_R 7'd051
`define INST_L 7'd003
`define INST_ALU 7'd019
@@ -62,7 +72,7 @@
`define INST_JAL 7'd111
`define INST_JALR 7'd103
`define INST_SYS 7'd115
`define INST_GPGPU 7'h06b
`define INST_GPGPU 7'd107
`define RS2_IMMED 1
`define RS2_REG 0

2
hw/rtl/VX_dram_arb.v
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@@ -1,4 +1,4 @@
`include "VX_define.vh"
`include "VX_cache_config.vh"
module VX_dram_arb #(
parameter BANK_LINE_SIZE = 1,

32
hw/rtl/VX_warp.v
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@@ -19,26 +19,16 @@ module VX_warp (
output wire[`NUM_THREADS-1:0] valid
);
reg [31:0] real_PC;
logic [31:0] temp_PC;
logic [31:0] use_PC;
reg [`NUM_THREADS-1:0] valid_t;
reg [`NUM_THREADS-1:0] valid_zero;
integer i;
initial begin
real_PC = 0;
for (i = 1; i < `NUM_THREADS; i=i+1) begin
valid_t[i] = 0; // Thread 1 active
valid_zero[i] = 0;
end
valid_t = 1;
valid_zero[0] = 0;
end
reg [31:0] real_PC;
reg [31:0] temp_PC;
reg [31:0] use_PC;
always @(posedge clk) begin
if (remove) begin
valid_t <= valid_zero;
if (reset) begin
valid_t <= {{(`NUM_THREADS-1){1'b0}},1'b1}; // Thread 1 active
end else if (remove) begin
valid_t <= 0;
end else if (change_mask) begin
valid_t <= thread_mask;
end
@@ -46,7 +36,7 @@ module VX_warp (
genvar i;
generate
for (i = 0; i < `NUM_THREADS; i = i+1) begin : valid_assign
for (i = 0; i < `NUM_THREADS; i++) begin : valid_assign
assign valid[i] = change_mask ? thread_mask[i] : stall ? 1'b0 : valid_t[i];
end
endgenerate
@@ -54,8 +44,7 @@ module VX_warp (
always @(*) begin
if (jal == 1'b1) begin
temp_PC = jal_dest;
// $display("LINKING TO %h", temp_PC);
end else if (branch_dir == 1'b1) begin
end else if (branch_dir) begin
temp_PC = branch_dest;
end else begin
temp_PC = real_PC;
@@ -68,8 +57,7 @@ module VX_warp (
always @(posedge clk) begin
if (reset) begin
real_PC <= 0;
end else if (wspawn == 1'b1) begin
// $display("Inside warp ***** Spawn @ %H",wspawn_pc);
end else if (wspawn) begin
real_PC <= wspawn_pc;
end else if (!stall) begin
real_PC <= use_PC + 32'h4;

8
hw/rtl/cache/VX_cache_config.vh vendored
View File

@@ -3,14 +3,6 @@
`include "VX_define.vh"
`define BYTE_EN_NO 3'h7
`define BYTE_EN_LB 3'h0
`define BYTE_EN_LH 3'h1
`define BYTE_EN_LW 3'h2
`define BYTE_EN_HB 3'h4
`define BYTE_EN_HH 3'h5
`define BYTE_EN_BITS 3
// data tid tag read write base addr
`define MRVQ_METADATA_WIDTH (`WORD_WIDTH + `REQS_BITS + CORE_TAG_WIDTH + `BYTE_EN_BITS + `BYTE_EN_BITS + `BASE_ADDR_BITS)

7
hw/rtl/cache/VX_cache_core_rsp_merge.v vendored
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@@ -53,9 +53,9 @@ module VX_cache_core_rsp_merge #(
output wire [NUM_BANKS-1:0] per_bank_core_rsp_pop,
// Core Writeback
output reg [NUM_REQUESTS-1:0] core_rsp_valid,
output reg [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] core_rsp_data,
output reg [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] core_rsp_tag,
output reg [NUM_REQUESTS-1:0] core_rsp_valid,
output reg [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] core_rsp_data,
output reg [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] core_rsp_tag,
input wire core_rsp_ready
);
@@ -81,7 +81,6 @@ module VX_cache_core_rsp_merge #(
always @(*) begin
core_rsp_valid = 0;
core_rsp_data = 0;
core_rsp_tag = 0;
for (i = 0; i < NUM_BANKS; i = i + 1) begin
if (found_bank
&& per_bank_core_rsp_valid[i]

2
hw/rtl/libs/VX_divide.v
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@@ -66,7 +66,7 @@ module VX_divide #(
reg [WIDTHD-1:0] denom_pipe [0:PIPELINE-1];
genvar i;
for (i = 0; i < PIPELINE-1; i = i+1) begin : pipe_stages
for (i = 0; i < PIPELINE-1; i++) begin : pipe_stages
always @(posedge clock or posedge aclr) begin
if (aclr) begin
numer_pipe[i+1] <= 0;

2
hw/rtl/libs/VX_mult.v
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@@ -84,7 +84,7 @@ module VX_mult #(
reg [WIDTHB-1:0] datab_pipe [0:PIPELINE-1];
genvar i;
for (i = 0; i < PIPELINE-1; i = i+1) begin : pipe_stages
for (i = 0; i < PIPELINE-1; i++) begin : pipe_stages
always @(posedge clock or posedge aclr) begin
if (aclr) begin
dataa_pipe[i+1] <= 0;