opae fixes
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@@ -66,7 +66,7 @@ module VX_divide #(
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reg [WIDTHD-1:0] denom_pipe [0:PIPELINE-1];
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genvar i;
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for (i = 0; i < PIPELINE-1; i = i+1) begin : pipe_stages
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for (i = 0; i < PIPELINE-1; i++) begin : pipe_stages
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always @(posedge clock or posedge aclr) begin
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if (aclr) begin
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numer_pipe[i+1] <= 0;
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@@ -84,7 +84,7 @@ module VX_mult #(
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reg [WIDTHB-1:0] datab_pipe [0:PIPELINE-1];
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genvar i;
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for (i = 0; i < PIPELINE-1; i = i+1) begin : pipe_stages
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for (i = 0; i < PIPELINE-1; i++) begin : pipe_stages
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always @(posedge clock or posedge aclr) begin
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if (aclr) begin
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dataa_pipe[i+1] <= 0;
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