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pipeline refactoring

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This commit is contained in:
Blaise Tine
2020-07-20 09:38:54 -04:00
parent 577a5791dc
commit e2100e9e87
14 changed files with 182 additions and 268 deletions
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35
hw/rtl/VX_writeback.v
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@@ -8,7 +8,6 @@ module VX_writeback #(
// inputs
VX_commit_if alu_commit_if,
VX_commit_if branch_commit_if,
VX_commit_if lsu_commit_if,
VX_commit_if mul_commit_if,
VX_commit_if csr_commit_if,
@@ -17,7 +16,6 @@ module VX_writeback #(
VX_wb_if writeback_if
);
wire br_valid = (| branch_commit_if.valid) && (branch_commit_if.wb != `WB_NO);
wire lsu_valid = (| lsu_commit_if.valid) && (lsu_commit_if.wb != `WB_NO);
wire mul_valid = (| mul_commit_if.valid) && (mul_commit_if.wb != `WB_NO);
wire alu_valid = (| alu_commit_if.valid) && (alu_commit_if.wb != `WB_NO);
@@ -25,30 +23,25 @@ module VX_writeback #(
VX_wb_if writeback_tmp_if();
assign writeback_tmp_if.valid = br_valid ? branch_commit_if.valid :
lsu_valid ? lsu_commit_if.valid :
assign writeback_tmp_if.valid = lsu_valid ? lsu_commit_if.valid :
mul_valid ? mul_commit_if.valid :
alu_valid ? alu_commit_if.valid :
csr_valid ? csr_commit_if.valid :
0;
assign writeback_tmp_if.warp_num = br_valid ? branch_commit_if.warp_num :
lsu_valid ? lsu_commit_if.warp_num :
assign writeback_tmp_if.warp_num = lsu_valid ? lsu_commit_if.warp_num :
mul_valid ? mul_commit_if.warp_num :
alu_valid ? alu_commit_if.warp_num :
csr_valid ? csr_commit_if.warp_num :
csr_valid ? csr_commit_if.warp_num :
0;
assign writeback_tmp_if.data = br_valid ? branch_commit_if.data :
lsu_valid ? lsu_commit_if.data :
assign writeback_tmp_if.data = lsu_valid ? lsu_commit_if.data :
mul_valid ? mul_commit_if.data :
alu_valid ? alu_commit_if.data :
csr_valid ? csr_commit_if.data :
0;
assign writeback_tmp_if.rd = br_valid ? branch_commit_if.rd :
lsu_valid ? lsu_commit_if.rd :
assign writeback_tmp_if.rd = lsu_valid ? lsu_commit_if.rd :
mul_valid ? mul_commit_if.rd :
alu_valid ? alu_commit_if.rd :
csr_valid ? csr_commit_if.rd :
@@ -67,11 +60,10 @@ module VX_writeback #(
.out ({writeback_if.valid, writeback_if.warp_num, writeback_if.rd, writeback_if.data})
);
assign branch_commit_if.ready = !stall;
assign lsu_commit_if.ready = !stall && !br_valid;
assign mul_commit_if.ready = !stall && !br_valid && !lsu_valid;
assign alu_commit_if.ready = !stall && !br_valid && !lsu_valid && !mul_valid;
assign csr_commit_if.ready = !stall && !br_valid && !lsu_valid && !mul_valid && !alu_valid;
assign lsu_commit_if.ready = !stall;
assign mul_commit_if.ready = !stall && !lsu_valid;
assign alu_commit_if.ready = !stall && !lsu_valid && !mul_valid;
assign csr_commit_if.ready = !stall && !lsu_valid && !mul_valid && !alu_valid;
// special workaround to control RISC-V benchmarks termination on Verilator
reg [31:0] last_data_wb /* verilator public */;
@@ -81,11 +73,4 @@ module VX_writeback #(
end
end
endmodule
endmodule