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New Warp Scheduler + VCD Enable

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This commit is contained in:
felsabbagh3
2019-09-15 00:12:41 -04:00
parent fb3bc60189
commit e67310acfb
66 changed files with 568 additions and 12973 deletions
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1
.gitignore vendored
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@@ -1,3 +1,4 @@
./rtl/obj_dir/
./rtl/obj_dir/*.vcd
./rtl/.*
.*

BIN
kernel/vortex_test.elf
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Binary file not shown.

5
kernel/vx_main.c
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@@ -34,16 +34,17 @@ void print_matrix(unsigned * z)
int main()
{
// vx_print_hex(11);
initialize_mats();
// // matrix multiplication
// matrix multiplication
// vx_sq_mat_mult(x, y, z, MAT_DIM);
// vx_print_str("\n\nMatrix multiplication\n");
// print_matrix(z);
print_matrix(x);
// // matrix addition
// vx_mat_add(x, y, z, NUM_ROWS, NUM_COLS);
// vx_print_str("\n\nMatrix Addition\n");

10
rtl/Makefile
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@@ -2,10 +2,18 @@ all: RUNFILE
VERILATOR:
echo "#define VCD_OFF" > tb_debug.h
verilator --compiler gcc -Wall -cc Vortex.v -I. -Iinterfaces/ -Ipipe_regs/ --exe test_bench.cpp -CFLAGS -std=c++11 -O3
compdebug:
echo "#define VCD_OUTPUT" > tb_debug.h
verilator --compiler gcc -Wall --trace -cc Vortex.v -I. -Iinterfaces/ -Ipipe_regs/ --exe test_bench.cpp -CFLAGS -std=c++11 -O3
RUNFILE: VERILATOR
(cd obj_dir && make -j -f VVortex.mk)
debug: compdebug
(cd obj_dir && make -j -f VVortex.mk)
clean:
rm ./obj_dir/*
rm obj_dir/*

24
rtl/VX_back_end.v
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@@ -44,12 +44,12 @@ wire[31:0] execute_jal_dest;
VX_mw_wb_inter VX_mw_wb();
VX_inst_mem_wb_inter VX_mem_wb();
VX_mem_req_inter VX_exe_mem_req();
VX_mem_req_inter VX_mem_req();
VX_inst_mem_wb_inter VX_mem_wb();
VX_execute vx_execute(
.VX_bckE_req (VX_bckE_req),
@@ -99,13 +99,21 @@ VX_memory vx_memory(
.VX_dcache_req (VX_dcache_req)
);
VX_m_w_reg vx_m_w_reg(
.clk (clk),
.reset (reset),
.in_freeze (total_freeze),
.VX_mem_wb (VX_mem_wb),
.VX_mw_wb (VX_mw_wb)
);
// VX_m_w_reg vx_m_w_reg(
// .clk (clk),
// .reset (reset),
// .in_freeze (total_freeze),
// .VX_mem_wb (VX_mem_wb),
// .VX_mw_wb (VX_mw_wb)
// );
assign VX_mw_wb.alu_result = VX_mem_wb.alu_result;
assign VX_mw_wb.mem_result = VX_mem_wb.mem_result;
assign VX_mw_wb.rd = VX_mem_wb.rd;
assign VX_mw_wb.wb = VX_mem_wb.wb;
assign VX_mw_wb.PC_next = VX_mem_wb.PC_next;
assign VX_mw_wb.valid = VX_mem_wb.valid;
assign VX_mw_wb.warp_num = VX_mem_wb.warp_num;
VX_writeback vx_writeback(

169
rtl/VX_better_warp_scheduler.v Normal file
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@@ -0,0 +1,169 @@
`include "VX_define.v"
typedef struct packed
{
logic[31:0] pc;
logic[`NT_M1:0] thread_mask;
} warp_meta_t;
typedef struct packed
{
logic[`NW-1:0] valid;
logic[`NW-1:0] visible;
logic[`NW-1:0] stalled;
warp_meta_t[`NW-1:0] warp_data;
} warps_meta_t;
module VX_better_warp_scheduler (
input wire clk, // Clock
input wire stall,
// Wspawn
input wire wspawn,
input wire[31:0] wsapwn_pc,
// CTM
input wire ctm,
input wire[`NT_M1:0] ctm_mask,
input wire[`NW_M1:0] ctm_warp_num,
// WHALT
input wire whalt,
input wire[`NW_M1:0] whalt_warp_num,
// WSTALL
input wire wstall,
input wire[`NW_M1:0] wstall_warp_num,
// JAL
input wire jal,
input wire[31:0] jal_dest,
input wire[`NW_M1:0] jal_warp_num,
// Branch
input wire branch_valid,
input wire branch_dir,
input wire[31:0] branch_dest,
input wire[`NW_M1:0] branch_warp_num,
output wire[`NT_M1:0] thread_mask,
output wire[`NW_M1:0] warp_num,
output wire[31:0] warp_pc,
output wire out_ebreak
);
warps_meta_t warps_meta;
initial begin
warps_meta.valid[0] = 1;
warps_meta.warp_data[0].thread_mask = 1;
end
always @(posedge clk) begin
$display("JAL %d DI %h",jal, jal_dest);
if (external_stall) begin
// Wsapwning warps
if (wspawn && found_wspawn) begin
warps_meta.warp_data[warp_to_wsapwn].pc <= wsapwn_pc;
warps_meta.warp_data[warp_to_wsapwn].thread_mask <= 1;
warps_meta.valid[warp_to_wsapwn] <= 1;
end
// Halting warps
if (whalt) begin
warps_meta.valid[whalt_warp_num] <= 0;
warps_meta.visible[whalt_warp_num] <= 0;
end
// Changing thread masks
if (ctm) begin
warps_meta.warp_data[ctm_warp_num].thread_mask <= ctm_mask;
end
// Stalling the scheduling of warps
if (wstall) begin
warps_meta.stalled[wstall_warp_num] <= 1;
warps_meta.visible[wstall_warp_num] <= 0;
end
// Jal
if (jal) begin
$display("UPDATING PC JAL: %h", jal_dest);
warps_meta.warp_data[jal_warp_num].pc <= jal_dest;
warps_meta.stalled[jal_warp_num] <= 0;
end
// Branch
if (branch_valid) begin
if (branch_dir) warps_meta.warp_data[branch_warp_num].pc <= branch_dest;
warps_meta.stalled[branch_warp_num] <= 0;
end
end else if (real_schedule) begin
// Refilling active warps
if (warps_meta.visible == 0) begin
warps_meta.visible <= warps_meta.valid & (~warps_meta.stalled);
end
// Don't change state if stall
warps_meta.visible[warp_to_schedule] <= 0;
warps_meta.warp_data[warp_to_schedule].pc <= warp_pc;
end else begin
// Refilling active warps
if (warps_meta.visible == 0) begin
warps_meta.visible <= warps_meta.valid & (~warps_meta.stalled);
end
end
end
wire external_stall = stall || wspawn || ctm || whalt || wstall || jal || branch_valid;
wire real_schedule = schedule && !warps_meta.stalled[warp_to_schedule];
assign warp_pc = warps_meta.warp_data[warp_to_schedule].pc + 4;
assign thread_mask = (external_stall || !real_schedule) ? 0 : warps_meta.warp_data[warp_to_schedule].thread_mask;
assign warp_num = warp_to_schedule;
// Choosing a warp to schedule
wire[`NW_M1:0] warp_to_schedule;
wire schedule;
VX_priority_encoder choose_schedule(
.valids(warps_meta.visible),
.index (warp_to_schedule),
.found (schedule)
);
// Choosing a warp to wsapwn
wire[`NW_M1:0] warp_to_wsapwn;
wire found_wspawn;
VX_priority_encoder choose_wsapwn(
.valids(~warps_meta.valid),
.index (warp_to_wsapwn),
.found (found_wspawn)
);
assign out_ebreak = (warps_meta.valid == 0);
endmodule

4
rtl/VX_csr_handler.v
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@@ -53,9 +53,7 @@ module VX_csr_handler (
end
end
always @(negedge clk) begin
data_read <= csr[decode_csr_address];
end
assign data_read = csr[decode_csr_address];
assign read_cycle = decode_csr_address == 12'hC00;

4
rtl/VX_decode.v
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@@ -301,6 +301,7 @@ module VX_decode(
wire is_ebreak;
// assign is_ebreak = is_e_inst;
assign is_ebreak = (curr_opcode == `SYS_INST) && (jal_sys_jal && in_valid[0]);
@@ -340,6 +341,7 @@ module VX_decode(
case(curr_opcode)
`B_INST:
begin
// $display("BRANCH IN DECODE");
temp_branch_stall = 1'b1 && in_valid[0];
case(func3)
3'h0: temp_branch_type = `BEQ;
@@ -379,7 +381,7 @@ module VX_decode(
end
assign VX_frE_to_bckE_req.branch_type = temp_branch_type;
assign out_branch_stall = temp_branch_stall;
assign out_branch_stall = temp_branch_stall && in_valid[0];
always @(*) begin
// ALU OP

2
rtl/VX_define.v
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@@ -4,7 +4,7 @@
`define NT_M1 (`NT-1)
// NW_M1 is actually log2(NW)
`define NW_M1 3
`define NW_M1 (3-1)
`define NW 8
// Uncomment the below line if NW=1
// `define ONLY

1
rtl/VX_execute.v
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@@ -76,7 +76,6 @@ module VX_execute (
assign out_branch_stall = ((in_branch_type != `NO_BRANCH) || in_jal ) ? `STALL : `NO_STALL;

196
rtl/VX_fetch.v
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@@ -3,7 +3,6 @@
module VX_fetch (
input wire clk,
input wire reset,
input wire in_memory_delay,
input wire in_branch_stall,
input wire in_fwd_stall,
@@ -21,169 +20,68 @@ module VX_fetch (
VX_warp_ctl_inter VX_warp_ctl
);
wire in_change_mask = VX_warp_ctl.change_mask;
wire in_wspawn = VX_warp_ctl.wspawn;
wire[31:0] in_wspawn_pc = VX_warp_ctl.wspawn_pc;
wire in_ebreak = VX_warp_ctl.ebreak;
wire[`NW_M1:0] in_decode_warp_num = VX_warp_ctl.warp_num;
// Inputs
wire in_freeze = out_delay || in_memory_delay;
// wire in_thread_mask[`NT_M1:0];
// genvar ind;
// for (ind = 0; ind <= `NT_M1; ind = ind + 1) assign in_thread_mask[ind] = VX_warp_ctl.thread_mask[ind];
// Locals
wire pipe_stall;
wire warp_stall;
assign pipe_stall = in_gpr_stall || in_fwd_stall || in_freeze;
reg stall;
reg[31:0] out_PC;
assign warp_stall = in_branch_stall || (in_branch_stall_exe && 0);
reg[`NW_M1:0] warp_num;
reg[`NW_M1:0] warp_state;
reg[`NW_M1:0] warp_count;
// reg[31:0] num_ecalls;
initial begin
warp_num = 0;
warp_state = 0;
// num_ecalls = 0;
warp_count = 1;
end
// always @(posedge clk) begin
// if (in_ebreak) begin
// num_ecalls <= num_ecalls + 1;
// $display("--------> New num_ecalls = %h", num_ecalls+1);
// end
// end
wire add_warp = in_wspawn && !in_ebreak && !in_gpr_stall;
wire remove_warp = in_ebreak && !in_wspawn && !in_gpr_stall;
wire[`NW_M1:0] new_warp_state;
wire[`NW_M1:0] new_warp_count;
assign new_warp_count = add_warp ? (warp_count + 1) : ((remove_warp ) ? (warp_count - 1) : (warp_count ));
assign new_warp_state = add_warp ? (warp_state + 1) : ((remove_warp && (warp_count == 3)) ? (0 ) : ( warp_state ));
wire[`NW_M1:0] new_warp_num ;
assign new_warp_num = (reset || (warp_num >= warp_state) || remove_warp || add_warp) ? 0 : (warp_num + 1);
always @(posedge clk or posedge reset) begin
warp_num <= new_warp_num;
warp_state <= new_warp_state;
warp_count <= new_warp_count;
end
// always @(posedge clk or posedge reset) begin
// if (reset || (warp_num >= warp_state) || remove_warp || add_warp) begin
// warp_num <= 0;
// end else begin
// warp_num <= warp_num + 1;
// end
// if (add_warp) begin
// warp_state <= warp_state + 1;
// warp_count <= warp_count + 1;
// // $display("Adding a new warp %h", warp_state+1);
// end else if (remove_warp) begin // No removing, just invalidating
// warp_count <= warp_count - 1;
// if (warp_count == 2) begin
// warp_state <= 0;
// end
// end
// end
assign out_ebreak = (in_decode_warp_num == 0) && in_ebreak;
assign stall = in_gpr_stall || in_branch_stall || in_fwd_stall || in_branch_stall_exe || in_freeze;
assign out_which_wspawn = (warp_state+1);
`ifdef ONLY
`else
wire[`NW-1:0][31:0] warp_glob_pc;
wire[`NW-1:0][`NT_M1:0] warp_glob_valid;
genvar cur_warp;
generate
for (cur_warp = 0; cur_warp < `NW; cur_warp = cur_warp + 1)
begin
wire warp_zero_change_mask = in_change_mask && (in_decode_warp_num == cur_warp);
wire warp_zero_jal = VX_jal_rsp.jal && (VX_jal_rsp.jal_warp_num == cur_warp);
wire warp_zero_branch = VX_branch_rsp.branch_dir && (VX_branch_rsp.branch_warp_num == cur_warp);
wire warp_zero_stall = stall || (warp_num != cur_warp);
wire warp_zero_wspawn = (cur_warp == 0) ? 0 : (in_wspawn && ((warp_state+1) == cur_warp));
wire[31:0] warp_zero_wspawn_pc = in_wspawn_pc;
wire warp_zero_remove = remove_warp && (in_decode_warp_num == cur_warp);
VX_warp VX_Warp(
wire[`NT_M1:0] thread_mask;
wire[`NW_M1:0] warp_num;
wire[31:0] warp_pc;
VX_warp_scheduler warp_scheduler(
.clk (clk),
.reset (reset),
.stall (warp_zero_stall),
.remove (warp_zero_remove),
.in_thread_mask(VX_warp_ctl.thread_mask),
.in_change_mask(warp_zero_change_mask),
.in_jal (warp_zero_jal),
.in_jal_dest (VX_jal_rsp.jal_dest),
.in_branch_dir (warp_zero_branch),
.in_branch_dest(VX_branch_rsp.branch_dest),
.in_wspawn (warp_zero_wspawn),
.in_wspawn_pc (warp_zero_wspawn_pc),
.out_PC (warp_glob_pc[cur_warp]),
.out_valid (warp_glob_valid[cur_warp])
.stall (pipe_stall),
// Wspawn
.wspawn (VX_warp_ctl.wspawn),
.wsapwn_pc (VX_warp_ctl.wspawn_pc),
// CTM
.ctm (VX_warp_ctl.change_mask),
.ctm_mask (VX_warp_ctl.thread_mask),
.ctm_warp_num (VX_warp_ctl.warp_num),
// WHALT
.whalt (VX_warp_ctl.ebreak),
.whalt_warp_num (VX_warp_ctl.warp_num),
// Wstall
.wstall (warp_stall),
.wstall_warp_num(VX_warp_ctl.warp_num),
// JAL
.jal (VX_jal_rsp.jal),
.jal_dest (VX_jal_rsp.jal_dest),
.jal_warp_num (VX_jal_rsp.jal_warp_num),
// Branch
.branch_valid (VX_branch_rsp.valid_branch),
.branch_dir (VX_branch_rsp.branch_dir),
.branch_dest (VX_branch_rsp.branch_dest),
.branch_warp_num(VX_branch_rsp.branch_warp_num),
// Outputs
.thread_mask (thread_mask),
.warp_num (warp_num),
.warp_pc (warp_pc),
.out_ebreak (out_ebreak)
);
end
endgenerate
reg[31:0] out_PC_var;
reg[`NT_M1:0] out_valid_var;
always @(*) begin : help
integer g;
integer h;
for (g = 0; g < `NW; g = g + 1)
begin
if (warp_num == g[`NW_M1:0])
begin
out_PC_var = warp_glob_pc[g][31:0];
for (h = 0; h < `NT; h = h + 1) out_valid_var[h] = warp_glob_valid[g][h];
end
end
end
assign out_PC = out_PC_var;
`endif
assign icache_request.pc_address = out_PC;
assign out_delay = 0;
assign out_which_wspawn = 0;
assign icache_request.pc_address = warp_pc;
assign fe_inst_meta_fd.warp_num = warp_num;
assign fe_inst_meta_fd.valid = thread_mask;
genvar index;
for (index = 0; index <= `NT_M1; index = index + 1) assign fe_inst_meta_fd.valid[index] = out_valid_var[index];
// assign fe_inst_meta_fd.instruction = (pipe_stall || warp_stall) ? 32'b0 : icache_response.instruction;;
assign fe_inst_meta_fd.instruction = (thread_mask == 0) ? 32'0 : icache_response.instruction;;
assign fe_inst_meta_fd.inst_pc = warp_pc;
assign fe_inst_meta_fd.instruction = (stall) ? 32'b0 : icache_response.instruction;;
assign fe_inst_meta_fd.inst_pc = out_PC;
// always @(*) begin
// $display("fetch: icache_request: %x", out_PC);
// end
endmodule

4
rtl/VX_forwarding.v
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@@ -111,7 +111,7 @@ module VX_forwarding (
(!src1_mem_fwd));
assign out_src1_fwd = src1_exe_fwd || src1_mem_fwd || src1_wb_fwd; // COMMENT
assign out_src1_fwd = src1_exe_fwd || src1_mem_fwd || (src1_wb_fwd && 0);
@@ -137,7 +137,7 @@ module VX_forwarding (
(in_writeback_warp_num == in_decode_warp_num);
assign out_src2_fwd = src2_exe_fwd || src2_mem_fwd || src2_wb_fwd; // COMMENT
assign out_src2_fwd = src2_exe_fwd || src2_mem_fwd || (src2_wb_fwd && 0);

1
rtl/VX_front_end.v
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@@ -46,7 +46,6 @@ wire total_freeze = memory_delay || fetch_delay;
VX_fetch vx_fetch(
.clk (clk),
.reset (reset),
.in_memory_delay (memory_delay),
.in_branch_stall (decode_branch_stall),
.in_fwd_stall (forwarding_fwd_stall),

1
rtl/VX_memory.v
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@@ -69,6 +69,7 @@ module VX_memory (
endcase // in_branch_type
end
assign VX_branch_rsp.valid_branch = (VX_mem_req.branch_type != `NO_BRANCH) && (|VX_mem_req.valid);
assign VX_branch_rsp.branch_dir = temp_branch_dir;
assign VX_branch_rsp.branch_warp_num = VX_mem_req.warp_num;

17
rtl/VX_one_counter.v Normal file
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@@ -0,0 +1,17 @@
module VX_one_counter (
input wire[`NW-1:0] valids,
output reg[`NW_M1:0] ones_found
);
integer i;
always @(*) begin
ones_found = 0;
for (i = `NW-1; i >= 0; i = i - 1) begin
if (valids[i]) begin
ones_found = ones_found + 1;
end
end
end
endmodule

20
rtl/VX_priority_encoder.v Normal file
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@@ -0,0 +1,20 @@
module VX_priority_encoder (
input wire[`NW-1:0] valids,
output reg[`NW_M1:0] index,
output reg found
);
integer i;
always @(*) begin
index = 0;
found = 0;
for (i = `NW-1; i >= 0; i = i - 1) begin
if (valids[i]) begin
index = i[`NW_M1:0];
found = 1;
end
end
end
endmodule

28
rtl/VX_register_file.v
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@@ -23,12 +23,17 @@ module VX_register_file (
wire write_enable;
// reg[5:0] i;
// always @(posedge clk) begin
// for (i = 0; i < 32; i++) begin
// $display("%d: %h",i, registers[i[4:0]]);
// end
// end
reg[5:0] i;
always @(posedge clk) begin
$display("*************");
if (write_enable && in_wb_warp)
$display("writing: %d = %h",in_rd, in_data);
for (i = 0; i < 32; i++) begin
if (registers[i[4:0]] != 0)
$display("%d: %h",i, registers[i[4:0]]);
end
end
// always @(*) begin
// $display("TID: %d: %h",10,registers[10]);
@@ -49,9 +54,14 @@ module VX_register_file (
end
end
always @(negedge clk) begin
out_src1_data <= registers[in_src1];
out_src2_data <= registers[in_src2];
// always @(negedge clk) begin
assign out_src1_data = registers[in_src1];
assign out_src2_data = registers[in_src2];
// end
always @(*) begin
$display("Reading Data 1: %d = %h",in_src1, out_src1_data);
$display("Reading Data 2: %d = %h",in_src2, out_src2_data);
end

176
rtl/VX_warp_scheduler.v Normal file
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@@ -0,0 +1,176 @@
`include "VX_define.v"
module VX_warp_scheduler (
input wire clk, // Clock
input wire stall,
// Wspawn
input wire wspawn,
input wire[31:0] wsapwn_pc,
// CTM
input wire ctm,
input wire[`NT_M1:0] ctm_mask,
input wire[`NW_M1:0] ctm_warp_num,
// WHALT
input wire whalt,
input wire[`NW_M1:0] whalt_warp_num,
// WSTALL
input wire wstall,
input wire[`NW_M1:0] wstall_warp_num,
// JAL
input wire jal,
input wire[31:0] jal_dest,
input wire[`NW_M1:0] jal_warp_num,
// Branch
input wire branch_valid,
input wire branch_dir,
input wire[31:0] branch_dest,
input wire[`NW_M1:0] branch_warp_num,
output wire[`NT_M1:0] thread_mask,
output wire[`NW_M1:0] warp_num,
output wire[31:0] warp_pc,
output wire out_ebreak
);
reg[`NW-1:0] warp_active;
reg[`NW-1:0] warp_stalled;
reg[`NW-1:0] visible_active;
wire[`NW-1:0] use_active;
reg[`NT_M1:0] thread_masks[`NW-1:0];
reg[31:0] warp_pcs[`NW-1:0];
reg[1:0] start;
initial begin
warp_pcs[0] = (32'h80000000 - 4);
start = 0;
warp_active[0] = 1; // Activating first warp
visible_active[0] = 1; // Activating first warp
thread_masks[0][0] = 1; // Activating first thread in first warp
end
always @(posedge clk) begin
// Wsapwning warps
if (wspawn && found_wspawn) begin
warp_pcs[warp_to_wsapwn] <= wsapwn_pc;
warp_active[warp_to_wsapwn] <= 1;
visible_active[warp_to_wsapwn] <= 1;
end
// Halting warps
if (whalt) begin
warp_active[whalt_warp_num] <= 0;
visible_active[whalt_warp_num] <= 0;
end
// Changing thread masks
if (ctm) begin
thread_masks[ctm_warp_num] <= ctm_mask;
end
// Stalling the scheduling of warps
if (wstall) begin
warp_stalled[wstall_warp_num] <= 1;
visible_active[wstall_warp_num] <= 0;
end
// Refilling active warps
if ((visible_active == 0) && !(stall || wstall || hazard)) begin
// if ((num_active <= 1) && !(globa)) begin
visible_active <= warp_active & (~warp_stalled);
end
// First cycle
if (start <= 2) begin
start <= 1;
visible_active <= warp_active & (~warp_stalled);
end
// Don't change state if stall
if (!global_stall && real_schedule && (thread_mask != 0)) begin
visible_active[warp_to_schedule] <= 0;
warp_pcs[warp_to_schedule] <= new_pc;
end
// Jal
if (jal) begin
warp_pcs[jal_warp_num] <= jal_dest;
warp_stalled[jal_warp_num] <= 0;
end
// Branch
if (branch_valid) begin
if (branch_dir) warp_pcs[branch_warp_num] <= branch_dest;
warp_stalled[branch_warp_num] <= 0;
end
end
// wire should_stall = stall || (jal && (warp_to_schedule == jal_warp_num)) || (branch_dir && (warp_to_schedule == branch_warp_num));
wire should_jal = (jal && (warp_to_schedule == jal_warp_num));
wire should_bra = (branch_dir && (warp_to_schedule == branch_warp_num));
wire hazard = (should_jal || should_bra) && schedule;
wire real_schedule = schedule && !warp_stalled[warp_to_schedule];
wire global_stall = (stall || wstall || hazard || !real_schedule);
assign warp_pc = warp_pcs[warp_to_schedule];
assign thread_mask = (global_stall) ? 0 : thread_masks[warp_to_schedule];
assign warp_num = warp_to_schedule;
wire[31:0] new_pc = warp_pc + 4;
assign use_active = (num_active <= 1) ? (warp_active & (~warp_stalled)) : visible_active;
// Choosing a warp to schedule
wire[`NW_M1:0] warp_to_schedule;
wire schedule;
VX_priority_encoder choose_schedule(
.valids(use_active),
.index (warp_to_schedule),
.found (schedule)
);
// Choosing a warp to wsapwn
wire[`NW_M1:0] warp_to_wsapwn;
wire found_wspawn;
VX_priority_encoder choose_wsapwn(
.valids(~warp_active),
.index (warp_to_wsapwn),
.found (found_wspawn)
);
// Valid counter
/* verilator lint_off UNUSED */
wire[`NW_M1:0] num_active;
/* verilator lint_on UNUSED */
VX_one_counter valid_counter(
.valids(visible_active),
.ones_found(num_active)
);
assign out_ebreak = (warp_active == 0);
endmodule

21
rtl/byte_enabled_simple_dual_port_ram.v
View File

@@ -11,8 +11,17 @@ module byte_enabled_simple_dual_port_ram
output reg[`NT_M1:0][31:0] q1, q2
);
// integer regi;
// integer threadi;
// Thread Byte Bit
logic [`NT_M1:0][3:0][7:0] GPR[31:0];
integer ini;
initial begin
for (ini = 0; ini < 32; ini = ini + 1) GPR[ini] = 0;
end
always_ff@(posedge clk) begin
if(we) begin
integer thread_ind;
@@ -23,10 +32,20 @@ module byte_enabled_simple_dual_port_ram
if(be[thread_ind]) GPR[waddr][thread_ind][3] <= wdata[thread_ind][31:24];
end
end
end
// $display("^^^^^^^^^^^^^^^^^^^^^^^");
// for (regi = 0; regi <= 31; regi = regi + 1) begin
// for (threadi = 0; threadi <= `NT_M1; threadi = threadi + 1) begin
// if (GPR[regi][threadi] != 0) $display("$%d: %h",regi, GPR[regi][threadi]);
// end
// end
end
assign q1 = GPR[raddr1];
assign q2 = GPR[raddr2];
// assign q1 = (raddr1 == waddr && (we)) ? wdata : GPR[raddr1];
// assign q2 = (raddr2 == waddr && (we)) ? wdata : GPR[raddr2];
endmodule

2
rtl/interfaces/VX_branch_response_inter.v
View File

@@ -6,7 +6,7 @@
`define VX_BRANCH_RSP
interface VX_branch_response_inter ();
wire valid_branch;
wire branch_dir;
wire[31:0] branch_dest;
wire[`NW_M1:0] branch_warp_num;

BIN
rtl/obj_dir/VVortex
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Binary file not shown.

11375
rtl/obj_dir/VVortex.cpp
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File diff suppressed because it is too large Load Diff

282
rtl/obj_dir/VVortex.h
View File

@@ -1,282 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Primary design header
//
// This header should be included by all source files instantiating the design.
// The class here is then constructed to instantiate the design.
// See the Verilator manual for examples.
#ifndef _VVortex_H_
#define _VVortex_H_
#include "verilated.h"
class VVortex__Syms;
class VVortex_VX_dcache_response_inter;
class VVortex_VX_dcache_request_inter;
class VVortex_VX_frE_to_bckE_req_inter;
class VVortex_VX_wb_inter;
class VVortex_VX_branch_response_inter;
class VVortex_VX_warp_ctl_inter;
class VVortex_VX_inst_meta_inter;
class VVortex_VX_mem_req_inter;
class VVortex_VX_inst_mem_wb_inter;
//----------
VL_MODULE(VVortex) {
public:
// CELLS
// Public to allow access to /*verilator_public*/ items;
// otherwise the application code can consider these internals.
VVortex_VX_dcache_response_inter* __PVT__Vortex__DOT__VX_dcache_rsp;
VVortex_VX_dcache_request_inter* __PVT__Vortex__DOT__VX_dcache_req;
VVortex_VX_frE_to_bckE_req_inter* __PVT__Vortex__DOT__VX_bckE_req;
VVortex_VX_wb_inter* __PVT__Vortex__DOT__VX_writeback_inter;
VVortex_VX_branch_response_inter* __PVT__Vortex__DOT__VX_branch_rsp;
VVortex_VX_warp_ctl_inter* __PVT__Vortex__DOT__vx_front_end__DOT__VX_warp_ctl;
VVortex_VX_inst_meta_inter* __PVT__Vortex__DOT__vx_front_end__DOT__fe_inst_meta_fd;
VVortex_VX_frE_to_bckE_req_inter* __PVT__Vortex__DOT__vx_front_end__DOT__VX_frE_to_bckE_req;
VVortex_VX_inst_meta_inter* __PVT__Vortex__DOT__vx_front_end__DOT__fd_inst_meta_de;
VVortex_VX_mem_req_inter* __PVT__Vortex__DOT__vx_back_end__DOT__VX_exe_mem_req;
VVortex_VX_mem_req_inter* __PVT__Vortex__DOT__vx_back_end__DOT__VX_mem_req;
VVortex_VX_inst_mem_wb_inter* __PVT__Vortex__DOT__vx_back_end__DOT__VX_mem_wb;
// PORTS
// The application code writes and reads these signals to
// propagate new values into/out from the Verilated model.
// Begin mtask footprint all:
VL_IN8(clk,0,0);
VL_IN8(reset,0,0);
VL_OUT8(out_cache_driver_in_mem_read,2,0);
VL_OUT8(out_cache_driver_in_mem_write,2,0);
VL_OUT8(out_ebreak,0,0);
VL_IN(icache_response_instruction,31,0);
VL_OUT(icache_request_pc_address,31,0);
VL_IN(in_cache_driver_out_data[4],31,0);
VL_OUT(out_cache_driver_in_address[4],31,0);
VL_OUT8(out_cache_driver_in_valid[4],0,0);
VL_OUT(out_cache_driver_in_data[4],31,0);
// LOCAL SIGNALS
// Internals; generally not touched by application code
// Anonymous structures to workaround compiler member-count bugs
struct {
// Begin mtask footprint all:
VL_SIG8(Vortex__DOT__execute_branch_stall,0,0);
VL_SIG8(Vortex__DOT__forwarding_fwd_stall,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__stall,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__warp_num,3,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__warp_state,3,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__warp_count,3,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__add_warp,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__remove_warp,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__new_warp_state,3,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__new_warp_count,3,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__new_warp_num,3,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__warp_glob_valid,31,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__out_valid_var,3,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__warp_zero_change_mask,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__warp_zero_stall,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__warp_zero_change_mask,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__warp_zero_stall,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__warp_zero_change_mask,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__warp_zero_stall,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__warp_zero_change_mask,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__warp_zero_stall,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__warp_zero_change_mask,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__warp_zero_stall,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__warp_zero_change_mask,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__warp_zero_stall,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__warp_zero_change_mask,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__warp_zero_stall,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__warp_zero_change_mask,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__warp_zero_stall,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__VX_Warp__DOT__valid,3,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__VX_Warp__DOT__valid_zero,3,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__VX_Warp__DOT__valid,3,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__VX_Warp__DOT__valid_zero,3,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__VX_Warp__DOT__valid,3,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__VX_Warp__DOT__valid_zero,3,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__VX_Warp__DOT__valid,3,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__VX_Warp__DOT__valid_zero,3,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__VX_Warp__DOT__valid,3,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__VX_Warp__DOT__valid_zero,3,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__VX_Warp__DOT__valid,3,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__VX_Warp__DOT__valid_zero,3,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__VX_Warp__DOT__valid,3,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__VX_Warp__DOT__valid_zero,3,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__VX_Warp__DOT__valid,3,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__VX_Warp__DOT__valid_zero,3,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__is_itype,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__is_csr,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__is_jalrs,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__is_jmprt,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__is_wspawn,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__jal_sys_jal,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__mul_alu,4,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__jalrs_thread_mask,3,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__jmprt_thread_mask,3,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__temp_jal,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__is_ebreak,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__temp_branch_type,2,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__temp_branch_stall,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__temp_final_alu,4,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__write_enable,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__write_enable,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__write_enable,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__write_enable,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__write_enable,0,0);
};
struct {
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__write_enable,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__write_enable,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__write_enable,0,0);
VL_SIG8(Vortex__DOT__vx_back_end__DOT__vx_memory__DOT__temp_branch_dir,0,0);
VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd,0,0);
VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd,0,0);
VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd,0,0);
VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd,0,0);
VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd,0,0);
VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src2_wb_fwd,0,0);
VL_SIG16(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__alu_tempp,11,0);
VL_SIGW(Vortex__DOT__vx_csr_handler__DOT__csr,12299,0,385);
VL_SIG16(Vortex__DOT__vx_csr_handler__DOT__decode_csr_address,11,0);
VL_SIG16(Vortex__DOT__vx_csr_handler__DOT__data_read,11,0);
VL_SIG(Vortex__DOT__csr_decode_csr_data,31,0);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__warp_glob_pc,255,0,8);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__out_PC_var,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__VX_Warp__DOT__real_PC,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__VX_Warp__DOT__temp_PC,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__VX_Warp__DOT__real_PC,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__VX_Warp__DOT__temp_PC,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__VX_Warp__DOT__real_PC,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__VX_Warp__DOT__temp_PC,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__VX_Warp__DOT__real_PC,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__VX_Warp__DOT__temp_PC,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__VX_Warp__DOT__real_PC,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__VX_Warp__DOT__temp_PC,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__VX_Warp__DOT__real_PC,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__VX_Warp__DOT__temp_PC,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__VX_Warp__DOT__real_PC,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__VX_Warp__DOT__temp_PC,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__VX_Warp__DOT__real_PC,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__VX_Warp__DOT__temp_PC,31,0);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value,71,0,3);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__temp_jal_offset,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__temp_itype_immed,31,0);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data,1023,0,32);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data,1023,0,32);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__jal_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_d_e_reg__DOT__d_e_reg__DOT__value,489,0,16);
VL_SIG(Vortex__DOT__vx_back_end__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2,31,0);
VL_SIG(Vortex__DOT__vx_back_end__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2,31,0);
VL_SIG(Vortex__DOT__vx_back_end__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2,31,0);
VL_SIG(Vortex__DOT__vx_back_end__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2,31,0);
VL_SIGW(Vortex__DOT__vx_back_end__DOT__vx_e_m_reg__DOT__f_d_reg__DOT__value,463,0,15);
VL_SIGW(Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value,302,0,10);
VL_SIGW(Vortex__DOT__vx_back_end__DOT__vx_writeback__DOT__out_pc_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next,127,0,4);
VL_SIGW(Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next,127,0,4);
VL_SIGW(Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next,127,0,4);
VL_SIG64(Vortex__DOT__vx_back_end__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__mult_signed_result,63,0);
VL_SIG64(Vortex__DOT__vx_back_end__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__mult_signed_result,63,0);
VL_SIG64(Vortex__DOT__vx_back_end__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__mult_signed_result,63,0);
VL_SIG64(Vortex__DOT__vx_back_end__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__mult_signed_result,63,0);
VL_SIG64(Vortex__DOT__vx_csr_handler__DOT__cycle,63,0);
VL_SIG64(Vortex__DOT__vx_csr_handler__DOT__instret,63,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__in_valid[4],0,0);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR[32],127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR[32],127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR[32],127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR[32],127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR[32],127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR[32],127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR[32],127,0,4);
};
struct {
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR[32],127,0,4);
};
// LOCAL VARIABLES
// Internals; generally not touched by application code
// Begin mtask footprint all:
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__0__KET____DOT__VX_Warp__out_valid,3,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__1__KET____DOT__VX_Warp__out_valid,3,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__2__KET____DOT__VX_Warp__out_valid,3,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__3__KET____DOT__VX_Warp__out_valid,3,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__4__KET____DOT__VX_Warp__out_valid,3,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__5__KET____DOT__VX_Warp__out_valid,3,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__6__KET____DOT__VX_Warp__out_valid,3,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__7__KET____DOT__VX_Warp__out_valid,3,0);
VL_SIG8(__Vtableidx1,2,0);
VL_SIG8(__Vclklast__TOP__clk,0,0);
VL_SIG8(__Vclklast__TOP__reset,0,0);
VL_SIG16(Vortex__DOT__vx_csr_handler__DOT____Vlvbound1,11,0);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT____Vcellout__vx_grp_wrapper__out_b_reg_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT____Vcellout__vx_grp_wrapper__out_a_reg_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_d_e_reg__DOT____Vcellinp__d_e_reg__in,489,0,16);
VL_SIG(Vortex__DOT__vx_back_end__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_alu__out_alu_result,31,0);
VL_SIG(Vortex__DOT__vx_back_end__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_alu__out_alu_result,31,0);
VL_SIG(Vortex__DOT__vx_back_end__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_alu__out_alu_result,31,0);
VL_SIG(Vortex__DOT__vx_back_end__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_alu__out_alu_result,31,0);
VL_SIGW(Vortex__DOT__vx_back_end__DOT__vx_e_m_reg__DOT____Vcellinp__f_d_reg__in,463,0,15);
static VL_ST_SIG8(__Vtable1_Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__mul_alu[8],4,0);
// INTERNAL VARIABLES
// Internals; generally not touched by application code
VVortex__Syms* __VlSymsp; // Symbol table
// PARAMETERS
// Parameters marked /*verilator public*/ for use by application code
// CONSTRUCTORS
private:
VL_UNCOPYABLE(VVortex); ///< Copying not allowed
public:
/// Construct the model; called by application code
/// The special name may be used to make a wrapper with a
/// single model invisible with respect to DPI scope names.
VVortex(const char* name="TOP");
/// Destroy the model; called (often implicitly) by application code
~VVortex();
// API METHODS
/// Evaluate the model. Application must call when inputs change.
void eval();
/// Simulation complete, run final blocks. Application must call on completion.
void final();
// INTERNAL METHODS
private:
static void _eval_initial_loop(VVortex__Syms* __restrict vlSymsp);
public:
void __Vconfigure(VVortex__Syms* symsp, bool first);
private:
static QData _change_request(VVortex__Syms* __restrict vlSymsp);
public:
static void _combo__TOP__10(VVortex__Syms* __restrict vlSymsp);
static void _combo__TOP__12(VVortex__Syms* __restrict vlSymsp);
static void _combo__TOP__3(VVortex__Syms* __restrict vlSymsp);
private:
void _ctor_var_reset() VL_ATTR_COLD;
public:
static void _eval(VVortex__Syms* __restrict vlSymsp);
private:
#ifdef VL_DEBUG
void _eval_debug_assertions();
#endif // VL_DEBUG
public:
static void _eval_initial(VVortex__Syms* __restrict vlSymsp) VL_ATTR_COLD;
static void _eval_settle(VVortex__Syms* __restrict vlSymsp) VL_ATTR_COLD;
static void _initial__TOP__6(VVortex__Syms* __restrict vlSymsp) VL_ATTR_COLD;
static void _multiclk__TOP__11(VVortex__Syms* __restrict vlSymsp);
static void _multiclk__TOP__8(VVortex__Syms* __restrict vlSymsp);
static void _sequent__TOP__2(VVortex__Syms* __restrict vlSymsp);
static void _sequent__TOP__4(VVortex__Syms* __restrict vlSymsp);
static void _sequent__TOP__5(VVortex__Syms* __restrict vlSymsp);
static void _sequent__TOP__7(VVortex__Syms* __restrict vlSymsp);
static void _settle__TOP__1(VVortex__Syms* __restrict vlSymsp) VL_ATTR_COLD;
static void _settle__TOP__9(VVortex__Syms* __restrict vlSymsp) VL_ATTR_COLD;
} VL_ATTR_ALIGNED(128);
#endif // guard

67
rtl/obj_dir/VVortex.mk
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@@ -1,67 +0,0 @@
# Verilated -*- Makefile -*-
# DESCRIPTION: Verilator output: Makefile for building Verilated archive or executable
#
# Execute this makefile from the object directory:
# make -f VVortex.mk
default: VVortex
### Constants...
# Perl executable (from $PERL)
PERL = perl
# Path to Verilator kit (from $VERILATOR_ROOT)
VERILATOR_ROOT = /usr/local/share/verilator
# SystemC include directory with systemc.h (from $SYSTEMC_INCLUDE)
SYSTEMC_INCLUDE ?=
# SystemC library directory with libsystemc.a (from $SYSTEMC_LIBDIR)
SYSTEMC_LIBDIR ?=
### Switches...
# SystemC output mode? 0/1 (from --sc)
VM_SC = 0
# Legacy or SystemC output mode? 0/1 (from --sc)
VM_SP_OR_SC = $(VM_SC)
# Deprecated
VM_PCLI = 1
# Deprecated: SystemC architecture to find link library path (from $SYSTEMC_ARCH)
VM_SC_TARGET_ARCH = linux
### Vars...
# Design prefix (from --prefix)
VM_PREFIX = VVortex
# Module prefix (from --prefix)
VM_MODPREFIX = VVortex
# User CFLAGS (from -CFLAGS on Verilator command line)
VM_USER_CFLAGS = \
-std=c++11 \
# User LDLIBS (from -LDFLAGS on Verilator command line)
VM_USER_LDLIBS = \
# User .cpp files (from .cpp's on Verilator command line)
VM_USER_CLASSES = \
test_bench \
# User .cpp directories (from .cpp's on Verilator command line)
VM_USER_DIR = \
. \
### Default rules...
# Include list of all generated classes
include VVortex_classes.mk
# Include global rules
include $(VERILATOR_ROOT)/include/verilated.mk
### Executable rules... (from --exe)
VPATH += $(VM_USER_DIR)
test_bench.o: test_bench.cpp
$(OBJCACHE) $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $<
### Link rules... (from --exe)
VVortex: $(VK_USER_OBJS) $(VK_GLOBAL_OBJS) $(VM_PREFIX)__ALL.a
$(LINK) $(LDFLAGS) $^ $(LOADLIBES) $(LDLIBS) -o $@ $(LIBS) $(SC_LIBS)
# Verilated -*- Makefile -*-

36
rtl/obj_dir/VVortex_VX_branch_response_inter.cpp
View File

@@ -1,36 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design implementation internals
// See VVortex.h for the primary calling header
#include "VVortex_VX_branch_response_inter.h"
#include "VVortex__Syms.h"
//--------------------
// STATIC VARIABLES
//--------------------
VL_CTOR_IMP(VVortex_VX_branch_response_inter) {
// Reset internal values
// Reset structure values
_ctor_var_reset();
}
void VVortex_VX_branch_response_inter::__Vconfigure(VVortex__Syms* vlSymsp, bool first) {
if (0 && first) {} // Prevent unused
this->__VlSymsp = vlSymsp;
}
VVortex_VX_branch_response_inter::~VVortex_VX_branch_response_inter() {
}
//--------------------
// Internal Methods
void VVortex_VX_branch_response_inter::_ctor_var_reset() {
VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex_VX_branch_response_inter::_ctor_var_reset\n"); );
// Body
branch_dest = VL_RAND_RESET_I(32);
}

47
rtl/obj_dir/VVortex_VX_branch_response_inter.h
View File

@@ -1,47 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design internal header
// See VVortex.h for the primary calling header
#ifndef _VVortex_VX_branch_response_inter_H_
#define _VVortex_VX_branch_response_inter_H_
#include "verilated.h"
class VVortex__Syms;
//----------
VL_MODULE(VVortex_VX_branch_response_inter) {
public:
// PORTS
// LOCAL SIGNALS
// Begin mtask footprint all:
VL_SIG(branch_dest,31,0);
// LOCAL VARIABLES
// INTERNAL VARIABLES
private:
VVortex__Syms* __VlSymsp; // Symbol table
public:
// PARAMETERS
// CONSTRUCTORS
private:
VL_UNCOPYABLE(VVortex_VX_branch_response_inter); ///< Copying not allowed
public:
VVortex_VX_branch_response_inter(const char* name="TOP");
~VVortex_VX_branch_response_inter();
// API METHODS
// INTERNAL METHODS
void __Vconfigure(VVortex__Syms* symsp, bool first);
private:
void _ctor_var_reset() VL_ATTR_COLD;
} VL_ATTR_ALIGNED(128);
#endif // guard

44
rtl/obj_dir/VVortex_VX_dcache_request_inter.cpp
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@@ -1,44 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design implementation internals
// See VVortex.h for the primary calling header
#include "VVortex_VX_dcache_request_inter.h"
#include "VVortex__Syms.h"
//--------------------
// STATIC VARIABLES
//--------------------
VL_CTOR_IMP(VVortex_VX_dcache_request_inter) {
// Reset internal values
// Reset structure values
_ctor_var_reset();
}
void VVortex_VX_dcache_request_inter::__Vconfigure(VVortex__Syms* vlSymsp, bool first) {
if (0 && first) {} // Prevent unused
this->__VlSymsp = vlSymsp;
}
VVortex_VX_dcache_request_inter::~VVortex_VX_dcache_request_inter() {
}
//--------------------
// Internal Methods
void VVortex_VX_dcache_request_inter::_ctor_var_reset() {
VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex_VX_dcache_request_inter::_ctor_var_reset\n"); );
// Body
{ int __Vi0=0; for (; __Vi0<4; ++__Vi0) {
out_cache_driver_in_address[__Vi0] = VL_RAND_RESET_I(32);
}}
{ int __Vi0=0; for (; __Vi0<4; ++__Vi0) {
out_cache_driver_in_valid[__Vi0] = VL_RAND_RESET_I(1);
}}
{ int __Vi0=0; for (; __Vi0<4; ++__Vi0) {
out_cache_driver_in_data[__Vi0] = VL_RAND_RESET_I(32);
}}
}

49
rtl/obj_dir/VVortex_VX_dcache_request_inter.h
View File

@@ -1,49 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design internal header
// See VVortex.h for the primary calling header
#ifndef _VVortex_VX_dcache_request_inter_H_
#define _VVortex_VX_dcache_request_inter_H_
#include "verilated.h"
class VVortex__Syms;
//----------
VL_MODULE(VVortex_VX_dcache_request_inter) {
public:
// PORTS
// LOCAL SIGNALS
// Begin mtask footprint all:
VL_SIG(out_cache_driver_in_address[4],31,0);
VL_SIG8(out_cache_driver_in_valid[4],0,0);
VL_SIG(out_cache_driver_in_data[4],31,0);
// LOCAL VARIABLES
// INTERNAL VARIABLES
private:
VVortex__Syms* __VlSymsp; // Symbol table
public:
// PARAMETERS
// CONSTRUCTORS
private:
VL_UNCOPYABLE(VVortex_VX_dcache_request_inter); ///< Copying not allowed
public:
VVortex_VX_dcache_request_inter(const char* name="TOP");
~VVortex_VX_dcache_request_inter();
// API METHODS
// INTERNAL METHODS
void __Vconfigure(VVortex__Syms* symsp, bool first);
private:
void _ctor_var_reset() VL_ATTR_COLD;
} VL_ATTR_ALIGNED(128);
#endif // guard

38
rtl/obj_dir/VVortex_VX_dcache_response_inter.cpp
View File

@@ -1,38 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design implementation internals
// See VVortex.h for the primary calling header
#include "VVortex_VX_dcache_response_inter.h"
#include "VVortex__Syms.h"
//--------------------
// STATIC VARIABLES
//--------------------
VL_CTOR_IMP(VVortex_VX_dcache_response_inter) {
// Reset internal values
// Reset structure values
_ctor_var_reset();
}
void VVortex_VX_dcache_response_inter::__Vconfigure(VVortex__Syms* vlSymsp, bool first) {
if (0 && first) {} // Prevent unused
this->__VlSymsp = vlSymsp;
}
VVortex_VX_dcache_response_inter::~VVortex_VX_dcache_response_inter() {
}
//--------------------
// Internal Methods
void VVortex_VX_dcache_response_inter::_ctor_var_reset() {
VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex_VX_dcache_response_inter::_ctor_var_reset\n"); );
// Body
{ int __Vi0=0; for (; __Vi0<4; ++__Vi0) {
in_cache_driver_out_data[__Vi0] = VL_RAND_RESET_I(32);
}}
}

47
rtl/obj_dir/VVortex_VX_dcache_response_inter.h
View File

@@ -1,47 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design internal header
// See VVortex.h for the primary calling header
#ifndef _VVortex_VX_dcache_response_inter_H_
#define _VVortex_VX_dcache_response_inter_H_
#include "verilated.h"
class VVortex__Syms;
//----------
VL_MODULE(VVortex_VX_dcache_response_inter) {
public:
// PORTS
// LOCAL SIGNALS
// Begin mtask footprint all:
VL_SIG(in_cache_driver_out_data[4],31,0);
// LOCAL VARIABLES
// INTERNAL VARIABLES
private:
VVortex__Syms* __VlSymsp; // Symbol table
public:
// PARAMETERS
// CONSTRUCTORS
private:
VL_UNCOPYABLE(VVortex_VX_dcache_response_inter); ///< Copying not allowed
public:
VVortex_VX_dcache_response_inter(const char* name="TOP");
~VVortex_VX_dcache_response_inter();
// API METHODS
// INTERNAL METHODS
void __Vconfigure(VVortex__Syms* symsp, bool first);
private:
void _ctor_var_reset() VL_ATTR_COLD;
} VL_ATTR_ALIGNED(128);
#endif // guard

36
rtl/obj_dir/VVortex_VX_frE_to_bckE_req_inter.cpp
View File

@@ -1,36 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design implementation internals
// See VVortex.h for the primary calling header
#include "VVortex_VX_frE_to_bckE_req_inter.h"
#include "VVortex__Syms.h"
//--------------------
// STATIC VARIABLES
//--------------------
VL_CTOR_IMP(VVortex_VX_frE_to_bckE_req_inter) {
// Reset internal values
// Reset structure values
_ctor_var_reset();
}
void VVortex_VX_frE_to_bckE_req_inter::__Vconfigure(VVortex__Syms* vlSymsp, bool first) {
if (0 && first) {} // Prevent unused
this->__VlSymsp = vlSymsp;
}
VVortex_VX_frE_to_bckE_req_inter::~VVortex_VX_frE_to_bckE_req_inter() {
}
//--------------------
// Internal Methods
void VVortex_VX_frE_to_bckE_req_inter::_ctor_var_reset() {
VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex_VX_frE_to_bckE_req_inter::_ctor_var_reset\n"); );
// Body
csr_address = VL_RAND_RESET_I(12);
}

47
rtl/obj_dir/VVortex_VX_frE_to_bckE_req_inter.h
View File

@@ -1,47 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design internal header
// See VVortex.h for the primary calling header
#ifndef _VVortex_VX_frE_to_bckE_req_inter_H_
#define _VVortex_VX_frE_to_bckE_req_inter_H_
#include "verilated.h"
class VVortex__Syms;
//----------
VL_MODULE(VVortex_VX_frE_to_bckE_req_inter) {
public:
// PORTS
// LOCAL SIGNALS
// Begin mtask footprint all:
VL_SIG16(csr_address,11,0);
// LOCAL VARIABLES
// INTERNAL VARIABLES
private:
VVortex__Syms* __VlSymsp; // Symbol table
public:
// PARAMETERS
// CONSTRUCTORS
private:
VL_UNCOPYABLE(VVortex_VX_frE_to_bckE_req_inter); ///< Copying not allowed
public:
VVortex_VX_frE_to_bckE_req_inter(const char* name="TOP");
~VVortex_VX_frE_to_bckE_req_inter();
// API METHODS
// INTERNAL METHODS
void __Vconfigure(VVortex__Syms* symsp, bool first);
private:
void _ctor_var_reset() VL_ATTR_COLD;
} VL_ATTR_ALIGNED(128);
#endif // guard

36
rtl/obj_dir/VVortex_VX_inst_mem_wb_inter.cpp
View File

@@ -1,36 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design implementation internals
// See VVortex.h for the primary calling header
#include "VVortex_VX_inst_mem_wb_inter.h"
#include "VVortex__Syms.h"
//--------------------
// STATIC VARIABLES
//--------------------
VL_CTOR_IMP(VVortex_VX_inst_mem_wb_inter) {
// Reset internal values
// Reset structure values
_ctor_var_reset();
}
void VVortex_VX_inst_mem_wb_inter::__Vconfigure(VVortex__Syms* vlSymsp, bool first) {
if (0 && first) {} // Prevent unused
this->__VlSymsp = vlSymsp;
}
VVortex_VX_inst_mem_wb_inter::~VVortex_VX_inst_mem_wb_inter() {
}
//--------------------
// Internal Methods
void VVortex_VX_inst_mem_wb_inter::_ctor_var_reset() {
VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex_VX_inst_mem_wb_inter::_ctor_var_reset\n"); );
// Body
VL_RAND_RESET_W(128,mem_result);
}

47
rtl/obj_dir/VVortex_VX_inst_mem_wb_inter.h
View File

@@ -1,47 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design internal header
// See VVortex.h for the primary calling header
#ifndef _VVortex_VX_inst_mem_wb_inter_H_
#define _VVortex_VX_inst_mem_wb_inter_H_
#include "verilated.h"
class VVortex__Syms;
//----------
VL_MODULE(VVortex_VX_inst_mem_wb_inter) {
public:
// PORTS
// LOCAL SIGNALS
// Begin mtask footprint all:
VL_SIGW(mem_result,127,0,4);
// LOCAL VARIABLES
// INTERNAL VARIABLES
private:
VVortex__Syms* __VlSymsp; // Symbol table
public:
// PARAMETERS
// CONSTRUCTORS
private:
VL_UNCOPYABLE(VVortex_VX_inst_mem_wb_inter); ///< Copying not allowed
public:
VVortex_VX_inst_mem_wb_inter(const char* name="TOP");
~VVortex_VX_inst_mem_wb_inter();
// API METHODS
// INTERNAL METHODS
void __Vconfigure(VVortex__Syms* symsp, bool first);
private:
void _ctor_var_reset() VL_ATTR_COLD;
} VL_ATTR_ALIGNED(128);
#endif // guard

36
rtl/obj_dir/VVortex_VX_inst_meta_inter.cpp
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@@ -1,36 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design implementation internals
// See VVortex.h for the primary calling header
#include "VVortex_VX_inst_meta_inter.h"
#include "VVortex__Syms.h"
//--------------------
// STATIC VARIABLES
//--------------------
VL_CTOR_IMP(VVortex_VX_inst_meta_inter) {
// Reset internal values
// Reset structure values
_ctor_var_reset();
}
void VVortex_VX_inst_meta_inter::__Vconfigure(VVortex__Syms* vlSymsp, bool first) {
if (0 && first) {} // Prevent unused
this->__VlSymsp = vlSymsp;
}
VVortex_VX_inst_meta_inter::~VVortex_VX_inst_meta_inter() {
}
//--------------------
// Internal Methods
void VVortex_VX_inst_meta_inter::_ctor_var_reset() {
VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex_VX_inst_meta_inter::_ctor_var_reset\n"); );
// Body
valid = VL_RAND_RESET_I(4);
}

47
rtl/obj_dir/VVortex_VX_inst_meta_inter.h
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@@ -1,47 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design internal header
// See VVortex.h for the primary calling header
#ifndef _VVortex_VX_inst_meta_inter_H_
#define _VVortex_VX_inst_meta_inter_H_
#include "verilated.h"
class VVortex__Syms;
//----------
VL_MODULE(VVortex_VX_inst_meta_inter) {
public:
// PORTS
// LOCAL SIGNALS
// Begin mtask footprint all:
VL_SIG8(valid,3,0);
// LOCAL VARIABLES
// INTERNAL VARIABLES
private:
VVortex__Syms* __VlSymsp; // Symbol table
public:
// PARAMETERS
// CONSTRUCTORS
private:
VL_UNCOPYABLE(VVortex_VX_inst_meta_inter); ///< Copying not allowed
public:
VVortex_VX_inst_meta_inter(const char* name="TOP");
~VVortex_VX_inst_meta_inter();
// API METHODS
// INTERNAL METHODS
void __Vconfigure(VVortex__Syms* symsp, bool first);
private:
void _ctor_var_reset() VL_ATTR_COLD;
} VL_ATTR_ALIGNED(128);
#endif // guard

37
rtl/obj_dir/VVortex_VX_mem_req_inter.cpp
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@@ -1,37 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design implementation internals
// See VVortex.h for the primary calling header
#include "VVortex_VX_mem_req_inter.h"
#include "VVortex__Syms.h"
//--------------------
// STATIC VARIABLES
//--------------------
VL_CTOR_IMP(VVortex_VX_mem_req_inter) {
// Reset internal values
// Reset structure values
_ctor_var_reset();
}
void VVortex_VX_mem_req_inter::__Vconfigure(VVortex__Syms* vlSymsp, bool first) {
if (0 && first) {} // Prevent unused
this->__VlSymsp = vlSymsp;
}
VVortex_VX_mem_req_inter::~VVortex_VX_mem_req_inter() {
}
//--------------------
// Internal Methods
void VVortex_VX_mem_req_inter::_ctor_var_reset() {
VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex_VX_mem_req_inter::_ctor_var_reset\n"); );
// Body
VL_RAND_RESET_W(128,alu_result);
wb = VL_RAND_RESET_I(2);
}

48
rtl/obj_dir/VVortex_VX_mem_req_inter.h
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@@ -1,48 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design internal header
// See VVortex.h for the primary calling header
#ifndef _VVortex_VX_mem_req_inter_H_
#define _VVortex_VX_mem_req_inter_H_
#include "verilated.h"
class VVortex__Syms;
//----------
VL_MODULE(VVortex_VX_mem_req_inter) {
public:
// PORTS
// LOCAL SIGNALS
// Begin mtask footprint all:
VL_SIG8(wb,1,0);
VL_SIGW(alu_result,127,0,4);
// LOCAL VARIABLES
// INTERNAL VARIABLES
private:
VVortex__Syms* __VlSymsp; // Symbol table
public:
// PARAMETERS
// CONSTRUCTORS
private:
VL_UNCOPYABLE(VVortex_VX_mem_req_inter); ///< Copying not allowed
public:
VVortex_VX_mem_req_inter(const char* name="TOP");
~VVortex_VX_mem_req_inter();
// API METHODS
// INTERNAL METHODS
void __Vconfigure(VVortex__Syms* symsp, bool first);
private:
void _ctor_var_reset() VL_ATTR_COLD;
} VL_ATTR_ALIGNED(128);
#endif // guard

37
rtl/obj_dir/VVortex_VX_warp_ctl_inter.cpp
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@@ -1,37 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design implementation internals
// See VVortex.h for the primary calling header
#include "VVortex_VX_warp_ctl_inter.h"
#include "VVortex__Syms.h"
//--------------------
// STATIC VARIABLES
//--------------------
VL_CTOR_IMP(VVortex_VX_warp_ctl_inter) {
// Reset internal values
// Reset structure values
_ctor_var_reset();
}
void VVortex_VX_warp_ctl_inter::__Vconfigure(VVortex__Syms* vlSymsp, bool first) {
if (0 && first) {} // Prevent unused
this->__VlSymsp = vlSymsp;
}
VVortex_VX_warp_ctl_inter::~VVortex_VX_warp_ctl_inter() {
}
//--------------------
// Internal Methods
void VVortex_VX_warp_ctl_inter::_ctor_var_reset() {
VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex_VX_warp_ctl_inter::_ctor_var_reset\n"); );
// Body
change_mask = VL_RAND_RESET_I(1);
thread_mask = VL_RAND_RESET_I(4);
}

48
rtl/obj_dir/VVortex_VX_warp_ctl_inter.h
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@@ -1,48 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design internal header
// See VVortex.h for the primary calling header
#ifndef _VVortex_VX_warp_ctl_inter_H_
#define _VVortex_VX_warp_ctl_inter_H_
#include "verilated.h"
class VVortex__Syms;
//----------
VL_MODULE(VVortex_VX_warp_ctl_inter) {
public:
// PORTS
// LOCAL SIGNALS
// Begin mtask footprint all:
VL_SIG8(change_mask,0,0);
VL_SIG8(thread_mask,3,0);
// LOCAL VARIABLES
// INTERNAL VARIABLES
private:
VVortex__Syms* __VlSymsp; // Symbol table
public:
// PARAMETERS
// CONSTRUCTORS
private:
VL_UNCOPYABLE(VVortex_VX_warp_ctl_inter); ///< Copying not allowed
public:
VVortex_VX_warp_ctl_inter(const char* name="TOP");
~VVortex_VX_warp_ctl_inter();
// API METHODS
// INTERNAL METHODS
void __Vconfigure(VVortex__Syms* symsp, bool first);
private:
void _ctor_var_reset() VL_ATTR_COLD;
} VL_ATTR_ALIGNED(128);
#endif // guard

36
rtl/obj_dir/VVortex_VX_wb_inter.cpp
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@@ -1,36 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design implementation internals
// See VVortex.h for the primary calling header
#include "VVortex_VX_wb_inter.h"
#include "VVortex__Syms.h"
//--------------------
// STATIC VARIABLES
//--------------------
VL_CTOR_IMP(VVortex_VX_wb_inter) {
// Reset internal values
// Reset structure values
_ctor_var_reset();
}
void VVortex_VX_wb_inter::__Vconfigure(VVortex__Syms* vlSymsp, bool first) {
if (0 && first) {} // Prevent unused
this->__VlSymsp = vlSymsp;
}
VVortex_VX_wb_inter::~VVortex_VX_wb_inter() {
}
//--------------------
// Internal Methods
void VVortex_VX_wb_inter::_ctor_var_reset() {
VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex_VX_wb_inter::_ctor_var_reset\n"); );
// Body
VL_RAND_RESET_W(128,write_data);
}

47
rtl/obj_dir/VVortex_VX_wb_inter.h
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@@ -1,47 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design internal header
// See VVortex.h for the primary calling header
#ifndef _VVortex_VX_wb_inter_H_
#define _VVortex_VX_wb_inter_H_
#include "verilated.h"
class VVortex__Syms;
//----------
VL_MODULE(VVortex_VX_wb_inter) {
public:
// PORTS
// LOCAL SIGNALS
// Begin mtask footprint all:
VL_SIGW(write_data,127,0,4);
// LOCAL VARIABLES
// INTERNAL VARIABLES
private:
VVortex__Syms* __VlSymsp; // Symbol table
public:
// PARAMETERS
// CONSTRUCTORS
private:
VL_UNCOPYABLE(VVortex_VX_wb_inter); ///< Copying not allowed
public:
VVortex_VX_wb_inter(const char* name="TOP");
~VVortex_VX_wb_inter();
// API METHODS
// INTERNAL METHODS
void __Vconfigure(VVortex__Syms* symsp, bool first);
private:
void _ctor_var_reset() VL_ATTR_COLD;
} VL_ATTR_ALIGNED(128);
#endif // guard

BIN
rtl/obj_dir/VVortex__ALL.a
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12
rtl/obj_dir/VVortex__ALLcls.cpp
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@@ -1,12 +0,0 @@
// DESCRIPTION: Generated by verilator_includer via makefile
#define VL_INCLUDE_OPT include
#include "VVortex.cpp"
#include "VVortex_VX_dcache_response_inter.cpp"
#include "VVortex_VX_dcache_request_inter.cpp"
#include "VVortex_VX_frE_to_bckE_req_inter.cpp"
#include "VVortex_VX_branch_response_inter.cpp"
#include "VVortex_VX_warp_ctl_inter.cpp"
#include "VVortex_VX_inst_meta_inter.cpp"
#include "VVortex_VX_mem_req_inter.cpp"
#include "VVortex_VX_inst_mem_wb_inter.cpp"
#include "VVortex_VX_wb_inter.cpp"

12
rtl/obj_dir/VVortex__ALLcls.d
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@@ -1,12 +0,0 @@
VVortex__ALLcls.o: VVortex__ALLcls.cpp VVortex.cpp VVortex.h \
/usr/local/share/verilator/include/verilated.h \
/usr/local/share/verilator/include/verilatedos.h VVortex__Syms.h \
VVortex_VX_dcache_response_inter.h VVortex_VX_dcache_request_inter.h \
VVortex_VX_frE_to_bckE_req_inter.h VVortex_VX_branch_response_inter.h \
VVortex_VX_warp_ctl_inter.h VVortex_VX_inst_meta_inter.h \
VVortex_VX_mem_req_inter.h VVortex_VX_inst_mem_wb_inter.h \
VVortex_VX_wb_inter.h VVortex_VX_dcache_response_inter.cpp \
VVortex_VX_dcache_request_inter.cpp VVortex_VX_frE_to_bckE_req_inter.cpp \
VVortex_VX_branch_response_inter.cpp VVortex_VX_warp_ctl_inter.cpp \
VVortex_VX_inst_meta_inter.cpp VVortex_VX_mem_req_inter.cpp \
VVortex_VX_inst_mem_wb_inter.cpp VVortex_VX_wb_inter.cpp

BIN
rtl/obj_dir/VVortex__ALLcls.o
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3
rtl/obj_dir/VVortex__ALLsup.cpp
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@@ -1,3 +0,0 @@
// DESCRIPTION: Generated by verilator_includer via makefile
#define VL_INCLUDE_OPT include
#include "VVortex__Syms.cpp"

8
rtl/obj_dir/VVortex__ALLsup.d
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@@ -1,8 +0,0 @@
VVortex__ALLsup.o: VVortex__ALLsup.cpp VVortex__Syms.cpp VVortex__Syms.h \
/usr/local/share/verilator/include/verilated.h \
/usr/local/share/verilator/include/verilatedos.h VVortex.h \
VVortex_VX_dcache_response_inter.h VVortex_VX_dcache_request_inter.h \
VVortex_VX_frE_to_bckE_req_inter.h VVortex_VX_branch_response_inter.h \
VVortex_VX_warp_ctl_inter.h VVortex_VX_inst_meta_inter.h \
VVortex_VX_mem_req_inter.h VVortex_VX_inst_mem_wb_inter.h \
VVortex_VX_wb_inter.h

BIN
rtl/obj_dir/VVortex__ALLsup.o
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55
rtl/obj_dir/VVortex__Syms.cpp
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@@ -1,55 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Symbol table implementation internals
#include "VVortex__Syms.h"
#include "VVortex.h"
#include "VVortex_VX_dcache_response_inter.h"
#include "VVortex_VX_dcache_request_inter.h"
#include "VVortex_VX_frE_to_bckE_req_inter.h"
#include "VVortex_VX_branch_response_inter.h"
#include "VVortex_VX_warp_ctl_inter.h"
#include "VVortex_VX_inst_meta_inter.h"
#include "VVortex_VX_mem_req_inter.h"
#include "VVortex_VX_inst_mem_wb_inter.h"
#include "VVortex_VX_wb_inter.h"
// FUNCTIONS
VVortex__Syms::VVortex__Syms(VVortex* topp, const char* namep)
// Setup locals
: __Vm_namep(namep)
, __Vm_didInit(false)
// Setup submodule names
, TOP__Vortex__DOT__VX_branch_rsp (Verilated::catName(topp->name(),"Vortex.VX_branch_rsp"))
, TOP__Vortex__DOT__VX_dcache_req (Verilated::catName(topp->name(),"Vortex.VX_dcache_req"))
, TOP__Vortex__DOT__VX_dcache_rsp (Verilated::catName(topp->name(),"Vortex.VX_dcache_rsp"))
, TOP__Vortex__DOT__VX_writeback_inter (Verilated::catName(topp->name(),"Vortex.VX_writeback_inter"))
, TOP__Vortex__DOT__vx_back_end__DOT__VX_exe_mem_req (Verilated::catName(topp->name(),"Vortex.vx_back_end.VX_exe_mem_req"))
, TOP__Vortex__DOT__vx_back_end__DOT__VX_mem_wb (Verilated::catName(topp->name(),"Vortex.vx_back_end.VX_mem_wb"))
, TOP__Vortex__DOT__vx_front_end__DOT__VX_frE_to_bckE_req (Verilated::catName(topp->name(),"Vortex.vx_front_end.VX_frE_to_bckE_req"))
, TOP__Vortex__DOT__vx_front_end__DOT__VX_warp_ctl (Verilated::catName(topp->name(),"Vortex.vx_front_end.VX_warp_ctl"))
, TOP__Vortex__DOT__vx_front_end__DOT__fe_inst_meta_fd (Verilated::catName(topp->name(),"Vortex.vx_front_end.fe_inst_meta_fd"))
{
// Pointer to top level
TOPp = topp;
// Setup each module's pointers to their submodules
TOPp->__PVT__Vortex__DOT__VX_branch_rsp = &TOP__Vortex__DOT__VX_branch_rsp;
TOPp->__PVT__Vortex__DOT__VX_dcache_req = &TOP__Vortex__DOT__VX_dcache_req;
TOPp->__PVT__Vortex__DOT__VX_dcache_rsp = &TOP__Vortex__DOT__VX_dcache_rsp;
TOPp->__PVT__Vortex__DOT__VX_writeback_inter = &TOP__Vortex__DOT__VX_writeback_inter;
TOPp->__PVT__Vortex__DOT__vx_back_end__DOT__VX_exe_mem_req = &TOP__Vortex__DOT__vx_back_end__DOT__VX_exe_mem_req;
TOPp->__PVT__Vortex__DOT__vx_back_end__DOT__VX_mem_wb = &TOP__Vortex__DOT__vx_back_end__DOT__VX_mem_wb;
TOPp->__PVT__Vortex__DOT__vx_front_end__DOT__VX_frE_to_bckE_req = &TOP__Vortex__DOT__vx_front_end__DOT__VX_frE_to_bckE_req;
TOPp->__PVT__Vortex__DOT__vx_front_end__DOT__VX_warp_ctl = &TOP__Vortex__DOT__vx_front_end__DOT__VX_warp_ctl;
TOPp->__PVT__Vortex__DOT__vx_front_end__DOT__fe_inst_meta_fd = &TOP__Vortex__DOT__vx_front_end__DOT__fe_inst_meta_fd;
// Setup each module's pointer back to symbol table (for public functions)
TOPp->__Vconfigure(this, true);
TOP__Vortex__DOT__VX_branch_rsp.__Vconfigure(this, true);
TOP__Vortex__DOT__VX_dcache_req.__Vconfigure(this, true);
TOP__Vortex__DOT__VX_dcache_rsp.__Vconfigure(this, true);
TOP__Vortex__DOT__VX_writeback_inter.__Vconfigure(this, true);
TOP__Vortex__DOT__vx_back_end__DOT__VX_exe_mem_req.__Vconfigure(this, true);
TOP__Vortex__DOT__vx_back_end__DOT__VX_mem_wb.__Vconfigure(this, true);
TOP__Vortex__DOT__vx_front_end__DOT__VX_frE_to_bckE_req.__Vconfigure(this, true);
TOP__Vortex__DOT__vx_front_end__DOT__VX_warp_ctl.__Vconfigure(this, true);
TOP__Vortex__DOT__vx_front_end__DOT__fe_inst_meta_fd.__Vconfigure(this, true);
}

53
rtl/obj_dir/VVortex__Syms.h
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@@ -1,53 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Symbol table internal header
//
// Internal details; most calling programs do not need this header,
// unless using verilator public meta comments.
#ifndef _VVortex__Syms_H_
#define _VVortex__Syms_H_
#include "verilated.h"
// INCLUDE MODULE CLASSES
#include "VVortex.h"
#include "VVortex_VX_dcache_response_inter.h"
#include "VVortex_VX_dcache_request_inter.h"
#include "VVortex_VX_frE_to_bckE_req_inter.h"
#include "VVortex_VX_branch_response_inter.h"
#include "VVortex_VX_warp_ctl_inter.h"
#include "VVortex_VX_inst_meta_inter.h"
#include "VVortex_VX_mem_req_inter.h"
#include "VVortex_VX_inst_mem_wb_inter.h"
#include "VVortex_VX_wb_inter.h"
// SYMS CLASS
class VVortex__Syms : public VerilatedSyms {
public:
// LOCAL STATE
const char* __Vm_namep;
bool __Vm_didInit;
// SUBCELL STATE
VVortex* TOPp;
VVortex_VX_branch_response_inter TOP__Vortex__DOT__VX_branch_rsp;
VVortex_VX_dcache_request_inter TOP__Vortex__DOT__VX_dcache_req;
VVortex_VX_dcache_response_inter TOP__Vortex__DOT__VX_dcache_rsp;
VVortex_VX_wb_inter TOP__Vortex__DOT__VX_writeback_inter;
VVortex_VX_mem_req_inter TOP__Vortex__DOT__vx_back_end__DOT__VX_exe_mem_req;
VVortex_VX_inst_mem_wb_inter TOP__Vortex__DOT__vx_back_end__DOT__VX_mem_wb;
VVortex_VX_frE_to_bckE_req_inter TOP__Vortex__DOT__vx_front_end__DOT__VX_frE_to_bckE_req;
VVortex_VX_warp_ctl_inter TOP__Vortex__DOT__vx_front_end__DOT__VX_warp_ctl;
VVortex_VX_inst_meta_inter TOP__Vortex__DOT__vx_front_end__DOT__fe_inst_meta_fd;
// CREATORS
VVortex__Syms(VVortex* topp, const char* namep);
~VVortex__Syms() {}
// METHODS
inline const char* name() { return __Vm_namep; }
} VL_ATTR_ALIGNED(64);
#endif // guard

1
rtl/obj_dir/VVortex__ver.d
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@@ -1 +0,0 @@
obj_dir/VVortex.cpp obj_dir/VVortex.h obj_dir/VVortex.mk obj_dir/VVortex_VX_branch_response_inter.cpp obj_dir/VVortex_VX_branch_response_inter.h obj_dir/VVortex_VX_dcache_request_inter.cpp obj_dir/VVortex_VX_dcache_request_inter.h obj_dir/VVortex_VX_dcache_response_inter.cpp obj_dir/VVortex_VX_dcache_response_inter.h obj_dir/VVortex_VX_frE_to_bckE_req_inter.cpp obj_dir/VVortex_VX_frE_to_bckE_req_inter.h obj_dir/VVortex_VX_inst_mem_wb_inter.cpp obj_dir/VVortex_VX_inst_mem_wb_inter.h obj_dir/VVortex_VX_inst_meta_inter.cpp obj_dir/VVortex_VX_inst_meta_inter.h obj_dir/VVortex_VX_mem_req_inter.cpp obj_dir/VVortex_VX_mem_req_inter.h obj_dir/VVortex_VX_warp_ctl_inter.cpp obj_dir/VVortex_VX_warp_ctl_inter.h obj_dir/VVortex_VX_wb_inter.cpp obj_dir/VVortex_VX_wb_inter.h obj_dir/VVortex__Syms.cpp obj_dir/VVortex__Syms.h obj_dir/VVortex__ver.d obj_dir/VVortex_classes.mk : /usr/local/bin/verilator_bin /usr/local/bin/verilator_bin VX_alu.v VX_back_end.v VX_csr_handler.v VX_decode.v VX_define.v VX_execute.v VX_fetch.v VX_forwarding.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_memory.v VX_warp.v VX_writeback.v Vortex.v byte_enabled_simple_dual_port_ram.v interfaces//../VX_define.v interfaces//VX_branch_response_inter.v interfaces//VX_csr_write_request_inter.v interfaces//VX_dcache_request_inter.v interfaces//VX_dcache_response_inter.v interfaces//VX_forward_exe_inter.v interfaces//VX_forward_mem_inter.v interfaces//VX_forward_reqeust_inter.v interfaces//VX_forward_response_inter.v interfaces//VX_forward_wb_inter.v interfaces//VX_frE_to_bckE_req_inter.v interfaces//VX_gpr_clone_inter.v interfaces//VX_gpr_jal_inter.v interfaces//VX_gpr_read_inter.v interfaces//VX_gpr_wspawn_inter.v interfaces//VX_icache_request_inter.v interfaces//VX_icache_response_inter.v interfaces//VX_inst_mem_wb_inter.v interfaces//VX_inst_meta_inter.v interfaces//VX_jal_response_inter.v interfaces//VX_mem_req_inter.v interfaces//VX_mw_wb_inter.v interfaces//VX_warp_ctl_inter.v interfaces//VX_wb_inter.v pipe_regs//VX_d_e_reg.v pipe_regs//VX_e_m_reg.v pipe_regs//VX_f_d_reg.v pipe_regs//VX_m_w_reg.v

74
rtl/obj_dir/VVortex__verFiles.dat
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@@ -1,74 +0,0 @@
# DESCRIPTION: Verilator output: Timestamp data for --skip-identical. Delete at will.
C "--compiler gcc -Wall -cc Vortex.v -I. -Iinterfaces/ -Ipipe_regs/ --exe test_bench.cpp -CFLAGS -std=c++11 -O3"
S 6746612 12892413243 1567548409 0 1567548409 0 "/usr/local/bin/verilator_bin"
S 2785 897406 1568177864 0 1568177864 0 "VX_alu.v"
S 2767 897407 1568177864 0 1568177864 0 "VX_back_end.v"
S 1836 897410 1568177864 0 1568177864 0 "VX_csr_handler.v"
S 12137 897855 1568180188 0 1568180188 0 "VX_decode.v"
S 1676 897412 1568177866 0 1568177866 0 "VX_define.v"
S 3835 897413 1568177866 0 1568177866 0 "VX_execute.v"
S 5559 897862 1568179536 0 1568179536 0 "VX_fetch.v"
S 6148 897415 1568177866 0 1568177866 0 "VX_forwarding.v"
S 2701 897416 1568177866 0 1568177866 0 "VX_front_end.v"
S 399 897417 1568177866 0 1568177866 0 "VX_generic_register.v"
S 2222 900429 1568225464 0 1568225464 0 "VX_gpr.v"
S 5323 897420 1568177866 0 1568177866 0 "VX_gpr_wrapper.v"
S 2584 897421 1568177866 0 1568177866 0 "VX_memory.v"
S 1901 899072 1568179744 0 1568179744 0 "VX_warp.v"
S 1597 897426 1568177868 0 1568177868 0 "VX_writeback.v"
S 4390 900095 1568217580 0 1568217580 0 "Vortex.v"
S 834 900358 1568227970 0 1568227970 0 "byte_enabled_simple_dual_port_ram.v"
S 1676 897412 1568177866 0 1568177866 0 "interfaces//../VX_define.v"
S 227 897429 1568177888 0 1568177888 0 "interfaces//VX_branch_response_inter.v"
S 212 897430 1568177888 0 1568177888 0 "interfaces//VX_csr_write_request_inter.v"
S 373 897431 1568177888 0 1568177888 0 "interfaces//VX_dcache_request_inter.v"
S 186 897432 1568177888 0 1568177888 0 "interfaces//VX_dcache_response_inter.v"
S 282 897434 1568177888 0 1568177888 0 "interfaces//VX_forward_exe_inter.v"
S 327 897435 1568177888 0 1568177888 0 "interfaces//VX_forward_mem_inter.v"
S 204 897436 1568177888 0 1568177888 0 "interfaces//VX_forward_reqeust_inter.v"
S 273 897437 1568177888 0 1568177888 0 "interfaces//VX_forward_response_inter.v"
S 313 897438 1568177888 0 1568177888 0 "interfaces//VX_forward_wb_inter.v"
S 833 897439 1568177888 0 1568177888 0 "interfaces//VX_frE_to_bckE_req_inter.v"
S 253 897441 1568177888 0 1568177888 0 "interfaces//VX_gpr_clone_inter.v"
S 173 897442 1568177888 0 1568177888 0 "interfaces//VX_gpr_jal_inter.v"
S 193 897443 1568177888 0 1568177888 0 "interfaces//VX_gpr_read_inter.v"
S 293 897444 1568177888 0 1568177888 0 "interfaces//VX_gpr_wspawn_inter.v"
S 159 897445 1568177890 0 1568177890 0 "interfaces//VX_icache_request_inter.v"
S 194 897446 1568177890 0 1568177890 0 "interfaces//VX_icache_response_inter.v"
S 366 897447 1568177890 0 1568177890 0 "interfaces//VX_inst_mem_wb_inter.v"
S 237 897448 1568177890 0 1568177890 0 "interfaces//VX_inst_meta_inter.v"
S 205 897449 1568177890 0 1568177890 0 "interfaces//VX_jal_response_inter.v"
S 557 897450 1568177890 0 1568177890 0 "interfaces//VX_mem_req_inter.v"
S 348 897451 1568177890 0 1568177890 0 "interfaces//VX_mw_wb_inter.v"
S 297 897452 1568177890 0 1568177890 0 "interfaces//VX_warp_ctl_inter.v"
S 273 897453 1568177890 0 1568177890 0 "interfaces//VX_wb_inter.v"
T 947185 900346 1568227976 0 1568227976 0 "obj_dir/VVortex.cpp"
T 20294 900344 1568227976 0 1568227976 0 "obj_dir/VVortex.h"
T 1791 900898 1568227976 0 1568227976 0 "obj_dir/VVortex.mk"
T 914 900886 1568227976 0 1568227976 0 "obj_dir/VVortex_VX_branch_response_inter.cpp"
T 1029 900885 1568227976 0 1568227976 0 "obj_dir/VVortex_VX_branch_response_inter.h"
T 1210 900882 1568227976 0 1568227976 0 "obj_dir/VVortex_VX_dcache_request_inter.cpp"
T 1135 900855 1568227976 0 1568227976 0 "obj_dir/VVortex_VX_dcache_request_inter.h"
T 988 900793 1568227976 0 1568227976 0 "obj_dir/VVortex_VX_dcache_response_inter.cpp"
T 1045 900782 1568227976 0 1568227976 0 "obj_dir/VVortex_VX_dcache_response_inter.h"
T 914 900884 1568227976 0 1568227976 0 "obj_dir/VVortex_VX_frE_to_bckE_req_inter.cpp"
T 1031 900883 1568227976 0 1568227976 0 "obj_dir/VVortex_VX_frE_to_bckE_req_inter.h"
T 884 900894 1568227976 0 1568227976 0 "obj_dir/VVortex_VX_inst_mem_wb_inter.cpp"
T 1008 900893 1568227976 0 1568227976 0 "obj_dir/VVortex_VX_inst_mem_wb_inter.h"
T 865 900890 1568227976 0 1568227976 0 "obj_dir/VVortex_VX_inst_meta_inter.cpp"
T 987 900889 1568227976 0 1568227976 0 "obj_dir/VVortex_VX_inst_meta_inter.h"
T 885 900892 1568227976 0 1568227976 0 "obj_dir/VVortex_VX_mem_req_inter.cpp"
T 1005 900891 1568227976 0 1568227976 0 "obj_dir/VVortex_VX_mem_req_inter.h"
T 902 900888 1568227976 0 1568227976 0 "obj_dir/VVortex_VX_warp_ctl_inter.cpp"
T 1017 900887 1568227976 0 1568227976 0 "obj_dir/VVortex_VX_warp_ctl_inter.h"
T 825 900896 1568227976 0 1568227976 0 "obj_dir/VVortex_VX_wb_inter.cpp"
T 954 900895 1568227976 0 1568227976 0 "obj_dir/VVortex_VX_wb_inter.h"
T 3499 900343 1568227976 0 1568227976 0 "obj_dir/VVortex__Syms.cpp"
T 1855 900342 1568227976 0 1568227976 0 "obj_dir/VVortex__Syms.h"
T 2113 900899 1568227976 0 1568227976 0 "obj_dir/VVortex__ver.d"
T 0 0 1568227976 0 1568227976 0 "obj_dir/VVortex__verFiles.dat"
T 1530 900897 1568227976 0 1568227976 0 "obj_dir/VVortex_classes.mk"
S 1884 897454 1568177900 0 1568177900 0 "pipe_regs//VX_d_e_reg.v"
S 1538 897455 1568177900 0 1568177900 0 "pipe_regs//VX_e_m_reg.v"
S 751 897456 1568177900 0 1568177900 0 "pipe_regs//VX_f_d_reg.v"
S 688 897457 1568177900 0 1568177900 0 "pipe_regs//VX_m_w_reg.v"

49
rtl/obj_dir/VVortex_classes.mk
View File

@@ -1,49 +0,0 @@
# Verilated -*- Makefile -*-
# DESCRIPTION: Verilator output: Make include file with class lists
#
# This file lists generated Verilated files, for including in higher level makefiles.
# See VVortex.mk for the caller.
### Switches...
# Coverage output mode? 0/1 (from --coverage)
VM_COVERAGE = 0
# Threaded output mode? 0/1/N threads (from --threads)
VM_THREADS = 0
# Tracing output mode? 0/1 (from --trace)
VM_TRACE = 0
# Tracing threadeds output mode? 0/1 (from --trace-fst-thread)
VM_TRACE_THREADED = 0
### Object file lists...
# Generated module classes, fast-path, compile with highest optimization
VM_CLASSES_FAST += \
VVortex \
VVortex_VX_dcache_response_inter \
VVortex_VX_dcache_request_inter \
VVortex_VX_frE_to_bckE_req_inter \
VVortex_VX_branch_response_inter \
VVortex_VX_warp_ctl_inter \
VVortex_VX_inst_meta_inter \
VVortex_VX_mem_req_inter \
VVortex_VX_inst_mem_wb_inter \
VVortex_VX_wb_inter \
# Generated module classes, non-fast-path, compile with low/medium optimization
VM_CLASSES_SLOW += \
# Generated support classes, fast-path, compile with highest optimization
VM_SUPPORT_FAST += \
# Generated support classes, non-fast-path, compile with low/medium optimization
VM_SUPPORT_SLOW += \
VVortex__Syms \
# Global classes, need linked once per executable, fast-path, compile with highest optimization
VM_GLOBAL_FAST += \
verilated \
# Global classes, need linked once per executable, non-fast-path, compile with low/medium optimization
VM_GLOBAL_SLOW += \
# Verilated -*- Makefile -*-

3
rtl/obj_dir/test_bench.d
View File

@@ -1,3 +0,0 @@
test_bench.o: ../test_bench.cpp ../test_bench.h ../VX_define.h ../ram.h \
VVortex.h /usr/local/share/verilator/include/verilated.h \
/usr/local/share/verilator/include/verilatedos.h

BIN
rtl/obj_dir/test_bench.o
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Binary file not shown.

8
rtl/obj_dir/verilated.d
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@@ -1,8 +0,0 @@
verilated.o: /usr/local/share/verilator/include/verilated.cpp \
/usr/local/share/verilator/include/verilatedos.h \
/usr/local/share/verilator/include/verilated_imp.h \
/usr/local/share/verilator/include/verilated.h \
/usr/local/share/verilator/include/verilated_heavy.h \
/usr/local/share/verilator/include/verilated_syms.h \
/usr/local/share/verilator/include/verilated_sym_props.h \
/usr/local/share/verilator/include/verilated_config.h

BIN
rtl/obj_dir/verilated.o
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Binary file not shown.

2
rtl/pipe_regs/VX_d_e_reg.v
View File

@@ -20,7 +20,7 @@ module VX_d_e_reg (
wire flush = (in_fwd_stall == `STALL) || (in_branch_stall == `STALL) || (in_gpr_stall == `STALL);
VX_generic_register #(.N(490)) d_e_reg
VX_generic_register #(.N(489)) d_e_reg
(
.clk (clk),
.reset(reset),

8
rtl/pipe_regs/VX_e_m_reg.v
View File

@@ -27,14 +27,18 @@ module VX_e_m_reg (
wire flush = 0;
wire stall = in_freeze;
VX_generic_register #(.N(464)) f_d_reg
wire temp_out_jal;
assign out_jal = temp_out_jal && VX_mem_req.valid[0];
VX_generic_register #(.N(463)) f_d_reg
(
.clk (clk),
.reset(reset),
.stall(stall),
.flush(flush),
.in ({in_csr_address , in_is_csr , in_csr_result , in_jal , in_jal_dest , VX_exe_mem_req.alu_result, VX_exe_mem_req.mem_read, VX_exe_mem_req.mem_write, VX_exe_mem_req.rd, VX_exe_mem_req.wb, VX_exe_mem_req.rs1, VX_exe_mem_req.rs2, VX_exe_mem_req.rd2, VX_exe_mem_req.PC_next, VX_exe_mem_req.curr_PC, VX_exe_mem_req.branch_offset, VX_exe_mem_req.branch_type, VX_exe_mem_req.valid, VX_exe_mem_req.warp_num}),
.out ({out_csr_address, out_is_csr, out_csr_result, out_jal, out_jal_dest, VX_mem_req.alu_result , VX_mem_req.mem_read , VX_mem_req.mem_write , VX_mem_req.rd , VX_mem_req.wb , VX_mem_req.rs1 , VX_mem_req.rs2 , VX_mem_req.rd2 , VX_mem_req.PC_next , VX_mem_req.curr_PC , VX_mem_req.branch_offset , VX_mem_req.branch_type , VX_mem_req.valid , VX_mem_req.warp_num})
.out ({out_csr_address, out_is_csr, out_csr_result, temp_out_jal, out_jal_dest, VX_mem_req.alu_result , VX_mem_req.mem_read , VX_mem_req.mem_write , VX_mem_req.rd , VX_mem_req.wb , VX_mem_req.rs1 , VX_mem_req.rs2 , VX_mem_req.rd2 , VX_mem_req.PC_next , VX_mem_req.curr_PC , VX_mem_req.branch_offset , VX_mem_req.branch_type , VX_mem_req.valid , VX_mem_req.warp_num})
);
endmodule // VX_e_m_reg

2
rtl/pipe_regs/VX_f_d_reg.v
View File

@@ -17,7 +17,7 @@ module VX_f_d_reg (
VX_generic_register #(.N(72)) f_d_reg
VX_generic_register #(.N(71)) f_d_reg
(
.clk (clk),
.reset(reset),

2
rtl/ram.h
View File

@@ -166,7 +166,6 @@ void loadHexImpl(std::string path,RAM* mem) {
//Preload 0x0 <-> 0x80000000 jumps
((uint32_t*)mem->get(0))[1] = 0xf1401073;
// ((uint32_t*)mem->get(0))[1] = 0xf1401073;
((uint32_t*)mem->get(0))[2] = 0x30101073;
((uint32_t*)mem->get(0))[3] = 0x800000b7;
@@ -202,7 +201,6 @@ void loadHexImpl(std::string path,RAM* mem) {
unsigned add = nextAddr + i;
*(mem->get(add)) = hToI(line + 9 + i * 2, 2);
// std::cout << "Address: " << std::hex <<(add) << "\tValue: " << std::hex << hToI(line + 9 + i * 2, 2) << std::endl;
}
break;
case 2:

8
rtl/results.txt
View File

@@ -1,7 +1,7 @@
# Dynamic Instructions: 47217
# of total cycles: 47224
# Dynamic Instructions: 53327
# of total cycles: 53341
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.00015
# time to simulate: 2.22904e-314 milliseconds
# CPI: 1.00026
# time to simulate: 2.12472e-314 milliseconds
# GRADE: Failed on test: 4294967295

1
rtl/tb_debug.h Normal file
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@@ -0,0 +1 @@
#define VCD_OFF

7
rtl/test_bench.cpp
View File

@@ -7,8 +7,8 @@ int main(int argc, char **argv)
Verilated::commandArgs(argc, argv);
Verilated::traceEverOn(true);
Vortex v;
// bool passed = true;
// std::string tests[NUM_TESTS] = {
@@ -61,8 +61,10 @@ int main(int argc, char **argv)
// };
// for (int ii = 0; ii < NUM_TESTS; ii++)
// // for (int ii = 0; ii < NUM_TESTS - 1; ii++)
// // for (int ii = 5; ii < 6; ii++)
// {
// std::cout << "TESTING: " << tests[ii] << '\n';
// Vortex v;
// bool curr = v.simulate(tests[ii]);
// if ( curr) std::cerr << GREEN << "Test Passed: " << tests[ii] << std::endl;
@@ -77,6 +79,7 @@ int main(int argc, char **argv)
// char testing[] = "../../emulator/riscv_tests/rv32ui-p-sw.hex";
Vortex v;
char testing[] = "../../kernel/vortex_test.hex";
bool curr = v.simulate(testing);

50
rtl/test_bench.h
View File

@@ -15,7 +15,11 @@
#include "VVortex.h"
#include "verilated.h"
#include "tb_debug.h"
#ifdef VCD_OUTPUT
#include <verilated_vcd_c.h>
#endif
class Vortex
{
@@ -53,6 +57,9 @@ class Vortex
int debug_end_wait;
int debug_debugAddr;
double stats_sim_time;
#ifdef VCD_OUTPUT
VerilatedVcdC *m_trace;
#endif
};
@@ -63,11 +70,19 @@ Vortex::Vortex() : start_pc(0), curr_cycle(0), stop(true), unit_test(true), stat
debug_wait_num(0), debug_inst_num(0), debug_end_wait(0), debug_debugAddr(0)
{
this->vortex = new VVortex;
#ifdef VCD_OUTPUT
this->m_trace = new VerilatedVcdC;
this->vortex->trace(m_trace, 99);
this->m_trace->open("trace.vcd");
#endif
this->results.open("../results.txt");
}
Vortex::~Vortex()
{
#ifdef VCD_OUTPUT
m_trace->close();
#endif
this->results.close();
delete this->vortex;
}
@@ -140,6 +155,8 @@ bool Vortex::ibus_driver()
ram.getWord(new_PC, &curr_inst);
vortex->icache_response_instruction = curr_inst;
// std::cout << std::hex << "IReq: " << vortex->icache_request_pc_address << "\tResp: " << curr_inst << "\n";
// printf("\n\n---------------------------------------------\n(%x) Inst: %x\n", new_PC, curr_inst);
// printf("\n");
////////////////////// IBUS //////////////////////
@@ -307,11 +324,10 @@ bool Vortex::simulate(std::string file_to_simulate)
// auto start_time = clock();
vortex->clk = 0;
vortex->reset = 1;
vortex->eval();
// vortex->reset = 1;
vortex->reset = 0;
// vortex->reset = 0;
unsigned curr_inst;
unsigned new_PC;
@@ -350,30 +366,38 @@ bool Vortex::simulate(std::string file_to_simulate)
bool cont = false;
// for (int i = 0; i < 500; i++)
vortex->clk = 0;
vortex->eval();
// unsigned cycles;
counter = 0;
this->stats_total_cycles = 10;
while (this->stop && ((counter < 5)))
// while (this->stats_total_cycles < 10)
{
// std::cout << "Counter: " << counter << "\n";
// std::cout << "************* Cycle: " << (this->stats_total_cycles) << "\n";
istop = ibus_driver();
// dstop = !dbus_driver();
vortex->clk = 1;
vortex->eval();
#ifdef VCD_OUTPUT
m_trace->dump(2*this->stats_total_cycles);
#endif
istop = ibus_driver();
dstop = !dbus_driver();
vortex->clk = 0;
vortex->eval();
#ifdef VCD_OUTPUT
m_trace->dump((2*this->stats_total_cycles)+1);
#endif
// stop = istop && dstop;
stop = vortex->out_ebreak;
if (stop || cont)
// if (istop)
{
cont = true;
counter++;
@@ -387,8 +411,12 @@ bool Vortex::simulate(std::string file_to_simulate)
std::cerr << "New Total Cycles: " << (this->stats_total_cycles) << "\n";
uint32_t status;
ram.getWord(0, &status);
int status = (unsigned int) vortex->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR[28][0] & 0xf;
// std::cout << "Something: " << result << '\n';
// uint32_t status;
// ram.getWord(0, &status);
this->print_stats();