diff --git a/driver/rtlsim/Makefile b/driver/rtlsim/Makefile index a9dc78b7..2ae9becb 100644 --- a/driver/rtlsim/Makefile +++ b/driver/rtlsim/Makefile @@ -29,7 +29,7 @@ CFLAGS += -DUSE_RTLSIM $(CONFIGS) LDFLAGS += -shared -pthread # LDFLAGS += -dynamiclib -pthread -TOP = Vortex_Socket +TOP = Vortex SRCS = vortex.cpp ../common/vx_utils.cpp ../../hw/simulate/simulator.cpp diff --git a/hw/opae/sources.txt b/hw/opae/sources.txt index e71c2d79..6058a31a 100644 --- a/hw/opae/sources.txt +++ b/hw/opae/sources.txt @@ -49,9 +49,7 @@ QI:vortex_afu.qsf ../rtl/interfaces/VX_cache_snp_rsp_if.v ../rtl/interfaces/VX_csr_req_if.v ../rtl/interfaces/VX_exec_unit_req_if.v -../rtl/interfaces/VX_frE_to_bckE_req_if.v -../rtl/interfaces/VX_gpr_data_if.v -../rtl/interfaces/VX_gpr_jal_if.v +../rtl/interfaces/VX_backend_req_if.v ../rtl/interfaces/VX_gpr_read_if.v ../rtl/interfaces/VX_gpu_inst_req_if.v ../rtl/interfaces/VX_inst_meta_if.v @@ -92,12 +90,10 @@ QI:vortex_afu.qsf ../rtl/VX_csr_pipe.v ../rtl/VX_csr_data.v ../rtl/VX_warp_sched.v -../rtl/VX_gpr.v ../rtl/VX_gpr_ram.v ../rtl/VX_gpr_stage.v ../rtl/VX_alu_unit.v ../rtl/VX_lsu_unit.v -../rtl/VX_lsu_addr_gen.v ../rtl/VX_decode.v ../rtl/VX_inst_multiplex.v ../rtl/VX_dcache_arb.v diff --git a/hw/rtl/VX_back_end.v b/hw/rtl/VX_back_end.v index b188e3a8..f16abc46 100644 --- a/hw/rtl/VX_back_end.v +++ b/hw/rtl/VX_back_end.v @@ -16,7 +16,7 @@ module VX_back_end #( VX_jal_rsp_if jal_rsp_if, VX_branch_rsp_if branch_rsp_if, - VX_frE_to_bckE_req_if bckE_req_if, + VX_backend_req_if bckE_req_if, VX_wb_if writeback_if, VX_warp_ctl_if warp_ctl_if, diff --git a/hw/rtl/VX_decode.v b/hw/rtl/VX_decode.v index ad4d823e..0c8d4410 100644 --- a/hw/rtl/VX_decode.v +++ b/hw/rtl/VX_decode.v @@ -3,12 +3,12 @@ module VX_decode( // Fetch Inputs - VX_inst_meta_if fd_inst_meta_de, + VX_inst_meta_if fd_inst_meta_de, // Outputs - VX_frE_to_bckE_req_if frE_to_bckE_req_if, - VX_wstall_if wstall_if, - VX_join_if join_if + VX_backend_req_if frE_to_bckE_req_if, + VX_wstall_if wstall_if, + VX_join_if join_if ); wire in_valid = (| fd_inst_meta_de.valid); wire[31:0] in_instruction = fd_inst_meta_de.instruction; diff --git a/hw/rtl/VX_front_end.v b/hw/rtl/VX_front_end.v index a6e7922b..9d17227c 100644 --- a/hw/rtl/VX_front_end.v +++ b/hw/rtl/VX_front_end.v @@ -5,28 +5,28 @@ module VX_front_end #( ) ( `SCOPE_SIGNALS_ISTAGE_IO - input wire clk, - input wire reset, + input wire clk, + input wire reset, - input wire schedule_delay, + input wire schedule_delay, - VX_warp_ctl_if warp_ctl_if, + VX_warp_ctl_if warp_ctl_if, - VX_cache_core_rsp_if icache_rsp_if, - VX_cache_core_req_if icache_req_if, + VX_cache_core_rsp_if icache_rsp_if, + VX_cache_core_req_if icache_req_if, - VX_jal_rsp_if jal_rsp_if, - VX_branch_rsp_if branch_rsp_if, + VX_jal_rsp_if jal_rsp_if, + VX_branch_rsp_if branch_rsp_if, - VX_frE_to_bckE_req_if bckE_req_if, - output wire busy + VX_backend_req_if bckE_req_if, + output wire busy ); VX_inst_meta_if fe_inst_meta_fi(); VX_inst_meta_if fe_inst_meta_fi2(); VX_inst_meta_if fe_inst_meta_id(); - VX_frE_to_bckE_req_if frE_to_bckE_req_if(); + VX_backend_req_if frE_to_bckE_req_if(); VX_inst_meta_if fd_inst_meta_de(); wire total_freeze = schedule_delay; diff --git a/hw/rtl/VX_gpr.v b/hw/rtl/VX_gpr.v deleted file mode 100644 index 6953bde5..00000000 --- a/hw/rtl/VX_gpr.v +++ /dev/null @@ -1,149 +0,0 @@ -`include "VX_define.vh" - -module VX_gpr ( - input wire clk, - input wire reset, - input wire write_ce, - VX_gpr_read_if gpr_read_if, - VX_wb_if writeback_if, - - output wire [`NUM_THREADS-1:0][`NUM_GPRS-1:0] a_reg_data, - output wire [`NUM_THREADS-1:0][`NUM_GPRS-1:0] b_reg_data -); - wire [`NUM_THREADS-1:0][`NUM_GPRS-1:0] a_reg_data_unqual; - wire [`NUM_THREADS-1:0][`NUM_GPRS-1:0] b_reg_data_unqual; - - assign a_reg_data = (gpr_read_if.rs1 != 0) ? a_reg_data_unqual : 0; - assign b_reg_data = (gpr_read_if.rs2 != 0) ? b_reg_data_unqual : 0; - - wire [`NUM_THREADS-1:0] write_enable = writeback_if.valid & {`NUM_THREADS{write_ce && (writeback_if.wb != 0)}}; - - `ifndef ASIC - - VX_gpr_ram gpr_ram ( - .clk (clk), - .reset (reset), - .waddr (writeback_if.rd), - .raddr1 (gpr_read_if.rs1), - .raddr2 (gpr_read_if.rs2), - .we (write_enable), - .wdata (writeback_if.data), - .q1 (a_reg_data_unqual), - .q2 (b_reg_data_unqual) - ); - - `else - - wire going_to_write = write_enable & (| writeback_if.wb_valid); - wire [`NUM_THREADS-1:0][`NUM_GPRS-1:0] write_bit_mask; - - genvar i; - for (i = 0; i < `NUM_THREADS; i++) begin - wire local_write = write_enable & writeback_if.wb_valid[i]; - assign write_bit_mask[i] = {`NUM_GPRS{~local_write}}; - end - - wire cenb = 0; - wire cena_1 = 0; - wire cena_2 = 0; - - wire [`NUM_THREADS-1:0][`NUM_GPRS-1:0] tmp_a; - wire [`NUM_THREADS-1:0][`NUM_GPRS-1:0] tmp_b; - - `ifndef SYN - genvar j; - for (i = 0; i < `NUM_THREADS; i++) begin - for (j = 0; j < `NUM_GPRS; j++) begin - assign a_reg_data_unqual[i][j] = ((tmp_a[i][j] === 1'dx) || cena_1) ? 1'b0 : tmp_a[i][j]; - assign b_reg_data_unqual[i][j] = ((tmp_b[i][j] === 1'dx) || cena_2) ? 1'b0 : tmp_b[i][j]; - end - end - `else - assign a_reg_data_unqual = tmp_a; - assign b_reg_data_unqual = tmp_b; - `endif - - wire [`NUM_THREADS-1:0][`NUM_GPRS-1:0] to_write = writeback_if.write_data; - - for (i = 0; i < 'NT; i=i+4) - begin - `IGNORE_WARNINGS_BEGIN - rf2_32x128_wm1 first_ram ( - .CENYA(), - .AYA(), - .CENYB(), - .WENYB(), - .AYB(), - .QA(tmp_a[(i+3):(i)]), - .SOA(), - .SOB(), - .CLKA(clk), - .CENA(cena_1), - .AA(gpr_read_if.rs1[(i+3):(i)]), - .CLKB(clk), - .CENB(cenb), - .WENB(write_bit_mask[(i+3):(i)]), - .AB(writeback_if.rd[(i+3):(i)]), - .DB(to_write[(i+3):(i)]), - .EMAA(3'b011), - .EMASA(1'b0), - .EMAB(3'b011), - .TENA(1'b1), - .TCENA(1'b0), - .TAA(5'b0), - .TENB(1'b1), - .TCENB(1'b0), - .TWENB(128'b0), - .TAB(5'b0), - .TDB(128'b0), - .RET1N(1'b1), - .SIA(2'b0), - .SEA(1'b0), - .DFTRAMBYP(1'b0), - .SIB(2'b0), - .SEB(1'b0), - .COLLDISN(1'b1) - ); - - rf2_`NUM_GPRSx128_wm1 second_ram ( - .CENYA(), - .AYA(), - .CENYB(), - .WENYB(), - .AYB(), - .QA(tmp_b[(i+3):(i)]), - .SOA(), - .SOB(), - .CLKA(clk), - .CENA(cena_2), - .AA(gpr_read_if.rs2[(i+3):(i)]), - .CLKB(clk), - .CENB(cenb), - .WENB(write_bit_mask[(i+3):(i)]), - .AB(writeback_if.rd[(i+3):(i)]), - .DB(to_write[(i+3):(i)]), - .EMAA(3'b011), - .EMASA(1'b0), - .EMAB(3'b011), - .TENA(1'b1), - .TCENA(1'b0), - .TAA(5'b0), - .TENB(1'b1), - .TCENB(1'b0), - .TWENB(128'b0), - .TAB(5'b0), - .TDB(128'b0), - .RET1N(1'b1), - .SIA(2'b0), - .SEA(1'b0), - .DFTRAMBYP(1'b0), - .SIB(2'b0), - .SEB(1'b0), - .COLLDISN(1'b1) - ); - `IGNORE_WARNINGS_END - end - - `endif - -endmodule diff --git a/hw/rtl/VX_gpr_ram.v b/hw/rtl/VX_gpr_ram.v index 4b2e5d01..5af56488 100644 --- a/hw/rtl/VX_gpr_ram.v +++ b/hw/rtl/VX_gpr_ram.v @@ -1,31 +1,153 @@ `include "VX_define.vh" module VX_gpr_ram ( - input wire clk, - input wire reset, - input wire [4:0] waddr, - input wire [4:0] raddr1, - input wire [4:0] raddr2, - input wire [`NUM_THREADS-1:0] we, - input wire [`NUM_THREADS-1:0][31:0] wdata, - output reg [`NUM_THREADS-1:0][31:0] q1, - output reg [`NUM_THREADS-1:0][31:0] q2 + input wire clk, + input wire reset, + input wire write_ce, + VX_gpr_read_if gpr_read_if, + VX_wb_if writeback_if, + + output wire [`NUM_THREADS-1:0][`NUM_GPRS-1:0] a_reg_data, + output wire [`NUM_THREADS-1:0][`NUM_GPRS-1:0] b_reg_data ); - reg [`NUM_THREADS-1:0][31:0] ram[31:0]; + wire [`NUM_THREADS-1:0][`NUM_GPRS-1:0] a_reg_data_unqual; + wire [`NUM_THREADS-1:0][`NUM_GPRS-1:0] b_reg_data_unqual; - `UNUSED_VAR(reset) + assign a_reg_data = (gpr_read_if.rs1 != 0) ? a_reg_data_unqual : 0; + assign b_reg_data = (gpr_read_if.rs2 != 0) ? b_reg_data_unqual : 0; - genvar i; - - for (i = 0; i < `NUM_THREADS; i++) begin - always @(posedge clk) begin - if (we[i]) begin - ram[waddr][i] <= wdata[i]; + wire [`NUM_THREADS-1:0] write_enable = writeback_if.valid & {`NUM_THREADS{write_ce && (writeback_if.wb != 0)}}; + + `ifndef ASIC + + reg [`NUM_THREADS-1:0][31:0] ram[31:0]; + + `UNUSED_VAR(reset) + + genvar i; + for (i = 0; i < `NUM_THREADS; i++) begin + always @(posedge clk) begin + if (write_enable[i]) begin + ram[writeback_if.rd][i] <= writeback_if.data[i]; + end end end - end - - assign q1 = ram[raddr1]; - assign q2 = ram[raddr2]; + + assign a_reg_data_unqual = ram[gpr_read_if.rs1]; + assign b_reg_data_unqual = ram[gpr_read_if.rs2]; + + `else + + wire going_to_write = write_enable & (| writeback_if.wb_valid); + wire [`NUM_THREADS-1:0][`NUM_GPRS-1:0] write_bit_mask; + + genvar i; + for (i = 0; i < `NUM_THREADS; i++) begin + wire local_write = write_enable & writeback_if.wb_valid[i]; + assign write_bit_mask[i] = {`NUM_GPRS{~local_write}}; + end + + wire cenb = 0; + wire cena_1 = 0; + wire cena_2 = 0; + + wire [`NUM_THREADS-1:0][`NUM_GPRS-1:0] tmp_a; + wire [`NUM_THREADS-1:0][`NUM_GPRS-1:0] tmp_b; + + `ifndef SYN + genvar j; + for (i = 0; i < `NUM_THREADS; i++) begin + for (j = 0; j < `NUM_GPRS; j++) begin + assign a_reg_data_unqual[i][j] = ((tmp_a[i][j] === 1'dx) || cena_1) ? 1'b0 : tmp_a[i][j]; + assign b_reg_data_unqual[i][j] = ((tmp_b[i][j] === 1'dx) || cena_2) ? 1'b0 : tmp_b[i][j]; + end + end + `else + assign a_reg_data_unqual = tmp_a; + assign b_reg_data_unqual = tmp_b; + `endif + + wire [`NUM_THREADS-1:0][`NUM_GPRS-1:0] to_write = writeback_if.write_data; + + for (i = 0; i < 'NT; i=i+4) + begin + `IGNORE_WARNINGS_BEGIN + rf2_32x128_wm1 first_ram ( + .CENYA(), + .AYA(), + .CENYB(), + .WENYB(), + .AYB(), + .QA(tmp_a[(i+3):(i)]), + .SOA(), + .SOB(), + .CLKA(clk), + .CENA(cena_1), + .AA(gpr_read_if.rs1[(i+3):(i)]), + .CLKB(clk), + .CENB(cenb), + .WENB(write_bit_mask[(i+3):(i)]), + .AB(writeback_if.rd[(i+3):(i)]), + .DB(to_write[(i+3):(i)]), + .EMAA(3'b011), + .EMASA(1'b0), + .EMAB(3'b011), + .TENA(1'b1), + .TCENA(1'b0), + .TAA(5'b0), + .TENB(1'b1), + .TCENB(1'b0), + .TWENB(128'b0), + .TAB(5'b0), + .TDB(128'b0), + .RET1N(1'b1), + .SIA(2'b0), + .SEA(1'b0), + .DFTRAMBYP(1'b0), + .SIB(2'b0), + .SEB(1'b0), + .COLLDISN(1'b1) + ); + + rf2_`NUM_GPRSx128_wm1 second_ram ( + .CENYA(), + .AYA(), + .CENYB(), + .WENYB(), + .AYB(), + .QA(tmp_b[(i+3):(i)]), + .SOA(), + .SOB(), + .CLKA(clk), + .CENA(cena_2), + .AA(gpr_read_if.rs2[(i+3):(i)]), + .CLKB(clk), + .CENB(cenb), + .WENB(write_bit_mask[(i+3):(i)]), + .AB(writeback_if.rd[(i+3):(i)]), + .DB(to_write[(i+3):(i)]), + .EMAA(3'b011), + .EMASA(1'b0), + .EMAB(3'b011), + .TENA(1'b1), + .TCENA(1'b0), + .TAA(5'b0), + .TENB(1'b1), + .TCENB(1'b0), + .TWENB(128'b0), + .TAB(5'b0), + .TDB(128'b0), + .RET1N(1'b1), + .SIA(2'b0), + .SEA(1'b0), + .DFTRAMBYP(1'b0), + .SIB(2'b0), + .SEB(1'b0), + .COLLDISN(1'b1) + ); + `IGNORE_WARNINGS_END + end + + `endif endmodule diff --git a/hw/rtl/VX_gpr_stage.v b/hw/rtl/VX_gpr_stage.v index 13694d19..67c52a52 100644 --- a/hw/rtl/VX_gpr_stage.v +++ b/hw/rtl/VX_gpr_stage.v @@ -11,7 +11,7 @@ module VX_gpr_stage ( output wire gpr_stage_delay, // decodee inputs - VX_frE_to_bckE_req_if bckE_req_if, + VX_backend_req_if bckE_req_if, // WriteBack inputs VX_wb_if writeback_if, @@ -36,26 +36,18 @@ module VX_gpr_stage ( assign gpr_read_if.warp_num = bckE_req_if.warp_num; `ifndef ASIC - VX_gpr_jal_if gpr_jal_if(); - assign gpr_jal_if.is_jal = bckE_req_if.is_jal; - assign gpr_jal_if.curr_PC = bckE_req_if.curr_PC; + assign gpr_read_if.is_jal = bckE_req_if.is_jal; + assign gpr_read_if.curr_PC = bckE_req_if.curr_PC; `else - VX_gpr_jal_if gpr_jal_if(); - assign gpr_jal_if.is_jal = exec_unit_req_if.is_jal; - assign gpr_jal_if.curr_PC = exec_unit_req_if.curr_PC; + assign gpr_read_if.is_jal = exec_unit_req_if.is_jal; + assign gpr_read_if.curr_PC = exec_unit_req_if.curr_PC; `endif - VX_gpr_data_if gpr_datf_if(); - VX_gpr_wrapper grp_wrapper ( .clk (clk), .reset (reset), .writeback_if (writeback_if), - .gpr_read_if (gpr_read_if), - .gpr_jal_if (gpr_jal_if), - - .a_reg_data (gpr_datf_if.a_reg_data), - .b_reg_data (gpr_datf_if.b_reg_data) + .gpr_read_if (gpr_read_if) ); // Outputs @@ -66,7 +58,7 @@ module VX_gpr_stage ( VX_inst_multiplex inst_mult( .bckE_req_if (bckE_req_if), - .gpr_data_if (gpr_datf_if), + .gpr_read_if (gpr_read_if), .exec_unit_req_if (exec_unit_req_temp_if), .lsu_req_if (lsu_req_temp_if), .gpu_inst_req_if (gpu_inst_req_temp_if), diff --git a/hw/rtl/VX_gpr_wrapper.v b/hw/rtl/VX_gpr_wrapper.v index 3da77564..fe71f064 100644 --- a/hw/rtl/VX_gpr_wrapper.v +++ b/hw/rtl/VX_gpr_wrapper.v @@ -2,13 +2,9 @@ module VX_gpr_wrapper ( input wire clk, - input wire reset, - VX_gpr_read_if gpr_read_if, - VX_wb_if writeback_if, - VX_gpr_jal_if gpr_jal_if, - - output wire [`NUM_THREADS-1:0][31:0] a_reg_data, - output wire [`NUM_THREADS-1:0][31:0] b_reg_data + input wire reset, + VX_wb_if writeback_if, + VX_gpr_read_if gpr_read_if ); wire [`NUM_WARPS-1:0][`NUM_THREADS-1:0][31:0] tmp_a_reg_data; wire [`NUM_WARPS-1:0][`NUM_THREADS-1:0][31:0] tmp_b_reg_data; @@ -17,13 +13,13 @@ module VX_gpr_wrapper ( genvar i; generate for (i = 0; i < `NUM_THREADS; i++) begin : jal_data_assign - assign jal_data[i] = gpr_jal_if.curr_PC; + assign jal_data[i] = gpr_read_if.curr_PC; end endgenerate `ifndef ASIC - assign a_reg_data = (gpr_jal_if.is_jal ? jal_data : (tmp_a_reg_data[gpr_read_if.warp_num])); - assign b_reg_data = (tmp_b_reg_data[gpr_read_if.warp_num]); + assign gpr_read_if.a_reg_data = gpr_read_if.is_jal ? jal_data : tmp_a_reg_data[gpr_read_if.warp_num]; + assign gpr_read_if.b_reg_data = tmp_b_reg_data[gpr_read_if.warp_num]; `else wire [`NW_BITS-1:0] old_warp_num; @@ -39,15 +35,15 @@ module VX_gpr_wrapper ( .out (old_warp_num) ); - assign a_reg_data = (gpr_jal_if.is_jal ? jal_data : (tmp_a_reg_data[old_warp_num])); - assign b_reg_data = (tmp_b_reg_data[old_warp_num]); + assign gpr_read_if.a_reg_data = gpr_jal_if.is_jal ? jal_data : tmp_a_reg_data[old_warp_num]; + assign gpr_read_if.b_reg_data = tmp_b_reg_data[old_warp_num]; `endif generate for (i = 0; i < `NUM_WARPS; i++) begin : warp_gprs wire write_ce = (i == writeback_if.warp_num); - VX_gpr gpr( + VX_gpr_ram gpr_ram( .clk (clk), .reset (reset), .write_ce (write_ce), diff --git a/hw/rtl/VX_inst_multiplex.v b/hw/rtl/VX_inst_multiplex.v index b13e8c2f..57cf3387 100644 --- a/hw/rtl/VX_inst_multiplex.v +++ b/hw/rtl/VX_inst_multiplex.v @@ -2,8 +2,8 @@ module VX_inst_multiplex ( // Inputs - VX_frE_to_bckE_req_if bckE_req_if, - VX_gpr_data_if gpr_data_if, + VX_backend_req_if bckE_req_if, + VX_gpr_read_if gpr_read_if, // Outputs VX_exec_unit_req_if exec_unit_req_if, @@ -33,8 +33,8 @@ module VX_inst_multiplex ( // LSU Unit assign lsu_req_if.valid = bckE_req_if.valid & is_mem_mask; assign lsu_req_if.warp_num = bckE_req_if.warp_num; - assign lsu_req_if.base_address = gpr_data_if.a_reg_data; - assign lsu_req_if.store_data = gpr_data_if.b_reg_data; + assign lsu_req_if.base_address = gpr_read_if.a_reg_data; + assign lsu_req_if.store_data = gpr_read_if.b_reg_data; assign lsu_req_if.offset = bckE_req_if.itype_immed; @@ -51,8 +51,8 @@ module VX_inst_multiplex ( assign exec_unit_req_if.next_PC = bckE_req_if.next_PC; assign exec_unit_req_if.rd = bckE_req_if.rd; assign exec_unit_req_if.wb = bckE_req_if.wb; - assign exec_unit_req_if.a_reg_data = gpr_data_if.a_reg_data; - assign exec_unit_req_if.b_reg_data = gpr_data_if.b_reg_data; + assign exec_unit_req_if.a_reg_data = gpr_read_if.a_reg_data; + assign exec_unit_req_if.b_reg_data = gpr_read_if.b_reg_data; assign exec_unit_req_if.alu_op = bckE_req_if.alu_op; assign exec_unit_req_if.rs1 = bckE_req_if.rs1; assign exec_unit_req_if.rs2 = bckE_req_if.rs2; @@ -72,8 +72,8 @@ module VX_inst_multiplex ( assign gpu_inst_req_if.is_tmc = bckE_req_if.is_tmc; assign gpu_inst_req_if.is_split = bckE_req_if.is_split; assign gpu_inst_req_if.is_barrier = bckE_req_if.is_barrier; - assign gpu_inst_req_if.a_reg_data = gpr_data_if.a_reg_data; - assign gpu_inst_req_if.rd2 = gpr_data_if.b_reg_data[0]; + assign gpu_inst_req_if.a_reg_data = gpr_read_if.a_reg_data; + assign gpu_inst_req_if.rd2 = gpr_read_if.b_reg_data[0]; assign gpu_inst_req_if.next_PC = bckE_req_if.next_PC; // CSR Req diff --git a/hw/rtl/VX_lsu_addr_gen.v b/hw/rtl/VX_lsu_addr_gen.v deleted file mode 100644 index 267cbdfb..00000000 --- a/hw/rtl/VX_lsu_addr_gen.v +++ /dev/null @@ -1,15 +0,0 @@ -`include "VX_define.vh" - -module VX_lsu_addr_gen ( - input wire[`NUM_THREADS-1:0][31:0] base_address, - input wire[31:0] offset, - output wire[`NUM_THREADS-1:0][31:0] address -); - genvar i; - generate - for (i = 0; i < `NUM_THREADS; i++) begin : addresses - assign address[i] = base_address[i] + offset; - end - endgenerate - -endmodule \ No newline at end of file diff --git a/hw/rtl/VX_lsu_unit.v b/hw/rtl/VX_lsu_unit.v index 4dcd15df..9800b5f8 100644 --- a/hw/rtl/VX_lsu_unit.v +++ b/hw/rtl/VX_lsu_unit.v @@ -20,14 +20,6 @@ module VX_lsu_unit #( output wire delay ); - // Generate Addresses - wire[`NUM_THREADS-1:0][31:0] address; - VX_lsu_addr_gen VX_lsu_addr_gen ( - .base_address (lsu_req_if.base_address), - .offset (lsu_req_if.offset), - .address (address) - ); - wire[`NUM_THREADS-1:0][31:0] use_address; wire[`NUM_THREADS-1:0][31:0] use_store_data; wire[`NUM_THREADS-1:0] use_valid; @@ -40,6 +32,12 @@ module VX_lsu_unit #( genvar i; + // Generate Full Addresses + wire[`NUM_THREADS-1:0][31:0] full_address; + for (i = 0; i < `NUM_THREADS; i++) begin + assign full_address[i] = lsu_req_if.base_address[i] + lsu_req_if.offset; + end + VX_generic_register #( .N(45 + `NW_BITS-1 + 1 + `NUM_THREADS*65) ) lsu_buffer ( @@ -47,7 +45,7 @@ module VX_lsu_unit #( .reset (reset), .stall (delay), .flush (1'b0), - .in ({address , lsu_req_if.store_data, lsu_req_if.valid, lsu_req_if.mem_read, lsu_req_if.mem_write, lsu_req_if.rd, lsu_req_if.warp_num, lsu_req_if.wb, lsu_req_if.curr_PC}), + .in ({full_address,lsu_req_if.store_data, lsu_req_if.valid, lsu_req_if.mem_read, lsu_req_if.mem_write, lsu_req_if.rd, lsu_req_if.warp_num, lsu_req_if.wb, lsu_req_if.curr_PC}), .out ({use_address, use_store_data , use_valid , use_mem_read , use_mem_write , use_rd , use_warp_num , use_wb , use_pc }) ); diff --git a/hw/rtl/VX_pipeline.v b/hw/rtl/VX_pipeline.v index 282a38ff..2a5271c9 100644 --- a/hw/rtl/VX_pipeline.v +++ b/hw/rtl/VX_pipeline.v @@ -87,15 +87,15 @@ module VX_pipeline #( ) core_icache_rsp_if(); // Front-end to Back-end - VX_frE_to_bckE_req_if bckE_req_if(); + VX_backend_req_if bckE_req_if(); // Back-end to Front-end - VX_wb_if writeback_if(); - VX_branch_rsp_if branch_rsp_if(); - VX_jal_rsp_if jal_rsp_if(); + VX_wb_if writeback_if(); + VX_branch_rsp_if branch_rsp_if(); + VX_jal_rsp_if jal_rsp_if(); // Warp controls - VX_warp_ctl_if warp_ctl_if(); + VX_warp_ctl_if warp_ctl_if(); VX_front_end #( .CORE_ID(CORE_ID) diff --git a/hw/rtl/VX_scheduler.v b/hw/rtl/VX_scheduler.v index 4dcc45ca..d3d97a35 100644 --- a/hw/rtl/VX_scheduler.v +++ b/hw/rtl/VX_scheduler.v @@ -1,17 +1,17 @@ `include "VX_define.vh" module VX_scheduler ( - input wire clk, - input wire reset, - input wire memory_delay, - input wire exec_delay, - input wire gpr_stage_delay, + input wire clk, + input wire reset, + input wire memory_delay, + input wire exec_delay, + input wire gpr_stage_delay, - VX_frE_to_bckE_req_if bckE_req_if, - VX_wb_if writeback_if, + VX_backend_req_if bckE_req_if, + VX_wb_if writeback_if, - output wire schedule_delay, - output wire is_empty + output wire schedule_delay, + output wire is_empty ); localparam CTVW = `CLOG2(`NUM_WARPS * 32 + 1); diff --git a/hw/rtl/interfaces/VX_frE_to_bckE_req_if.v b/hw/rtl/interfaces/VX_backend_req_if.v similarity index 97% rename from hw/rtl/interfaces/VX_frE_to_bckE_req_if.v rename to hw/rtl/interfaces/VX_backend_req_if.v index 420dd47c..31ab83a8 100644 --- a/hw/rtl/interfaces/VX_frE_to_bckE_req_if.v +++ b/hw/rtl/interfaces/VX_backend_req_if.v @@ -3,7 +3,7 @@ `include "VX_define.vh" -interface VX_frE_to_bckE_req_if (); +interface VX_backend_req_if (); wire [11:0] csr_address; wire is_csr; diff --git a/hw/rtl/interfaces/VX_gpr_data_if.v b/hw/rtl/interfaces/VX_gpr_data_if.v deleted file mode 100644 index 11d2c611..00000000 --- a/hw/rtl/interfaces/VX_gpr_data_if.v +++ /dev/null @@ -1,14 +0,0 @@ - -`ifndef VX_GPR_DATA_IF -`define VX_GPR_DATA_IF - -`include "VX_define.vh" - -interface VX_gpr_data_if (); - - wire [`NUM_THREADS-1:0][31:0] a_reg_data; - wire [`NUM_THREADS-1:0][31:0] b_reg_data; - -endinterface - -`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_gpr_jal_if.v b/hw/rtl/interfaces/VX_gpr_jal_if.v deleted file mode 100644 index d4d001e8..00000000 --- a/hw/rtl/interfaces/VX_gpr_jal_if.v +++ /dev/null @@ -1,13 +0,0 @@ -`ifndef VX_GPR_JAL_IF -`define VX_GPR_JAL_IF - -`include "VX_define.vh" - -interface VX_gpr_jal_if (); - - wire is_jal; - wire[31:0] curr_PC; - -endinterface - -`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_gpr_read_if.v b/hw/rtl/interfaces/VX_gpr_read_if.v index 01bc227d..5673c319 100644 --- a/hw/rtl/interfaces/VX_gpr_read_if.v +++ b/hw/rtl/interfaces/VX_gpr_read_if.v @@ -8,6 +8,11 @@ interface VX_gpr_read_if (); wire [4:0] rs1; wire [4:0] rs2; wire [`NW_BITS-1:0] warp_num; + wire is_jal; + wire[31:0] curr_PC; + + wire [`NUM_THREADS-1:0][31:0] a_reg_data; + wire [`NUM_THREADS-1:0][31:0] b_reg_data; endinterface diff --git a/hw/rtl/libs/VX_indexable_queue.v b/hw/rtl/libs/VX_indexable_queue.v index f18e067e..64c3fe9b 100644 --- a/hw/rtl/libs/VX_indexable_queue.v +++ b/hw/rtl/libs/VX_indexable_queue.v @@ -31,8 +31,6 @@ module VX_indexable_queue #( assign enqueue = push && ~full; assign dequeue = ~empty && ~valid[rd_a]; // auto-remove when head is invalid - integer i; - always @(posedge clk) begin if (reset) begin rd_ptr <= 0; diff --git a/hw/rtl/pipe_regs/VX_d_e_reg.v b/hw/rtl/pipe_regs/VX_d_e_reg.v index 01b90aa8..35139f4d 100644 --- a/hw/rtl/pipe_regs/VX_d_e_reg.v +++ b/hw/rtl/pipe_regs/VX_d_e_reg.v @@ -1,12 +1,12 @@ `include "VX_define.vh" module VX_d_e_reg ( - input wire clk, - input wire reset, - input wire branch_stall, - input wire freeze, - VX_frE_to_bckE_req_if frE_to_bckE_req_if, - VX_frE_to_bckE_req_if bckE_req_if + input wire clk, + input wire reset, + input wire branch_stall, + input wire freeze, + VX_backend_req_if frE_to_bckE_req_if, + VX_backend_req_if bckE_req_if ); wire stall = freeze; diff --git a/hw/simulate/Makefile b/hw/simulate/Makefile index 16ecbdc0..c8bd3ffa 100644 --- a/hw/simulate/Makefile +++ b/hw/simulate/Makefile @@ -33,59 +33,59 @@ DBG += -DDBG_CORE_REQ_INFO THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))') gen-s: - verilator $(VF) -DNDEBUG -cc Vortex_Socket.v -CFLAGS '$(CF) -DNDEBUG' + verilator $(VF) -DNDEBUG -cc Vortex.v -CFLAGS '$(CF) -DNDEBUG' gen-sd: - verilator $(VF) -cc Vortex_Socket.v -CFLAGS '$(CF) -g -O0 $(DBG)' --trace $(DBG) + verilator $(VF) -cc Vortex.v -CFLAGS '$(CF) -g -O0 $(DBG)' --trace $(DBG) gen-st: - verilator $(VF) -DNDEBUG -cc Vortex_Socket.v -CFLAGS '$(CF) -DNDEBUG -O2' --threads $(THREADS) + verilator $(VF) -DNDEBUG -cc Vortex.v -CFLAGS '$(CF) -DNDEBUG -O2' --threads $(THREADS) gen-m: - verilator $(VF) -DNDEBUG -cc Vortex_Socket.v $(MULTICORE) -CFLAGS '$(CF) -DNDEBUG $(MULTICORE)' + verilator $(VF) -DNDEBUG -cc Vortex.v $(MULTICORE) -CFLAGS '$(CF) -DNDEBUG $(MULTICORE)' gen-md: - verilator $(VF) -cc Vortex_Socket.v $(MULTICORE) -CFLAGS '$(CF) -g -O0 $(DBG) $(MULTICORE)' --trace $(DBG) + verilator $(VF) -cc Vortex.v $(MULTICORE) -CFLAGS '$(CF) -g -O0 $(DBG) $(MULTICORE)' --trace $(DBG) gen-mt: - verilator $(VF) -DNDEBUG -cc Vortex_Socket.v $(MULTICORE) -CFLAGS '$(CF) -DNDEBUG -O2 $(MULTICORE)' --threads $(THREADS) + verilator $(VF) -DNDEBUG -cc Vortex.v $(MULTICORE) -CFLAGS '$(CF) -DNDEBUG -O2 $(MULTICORE)' --threads $(THREADS) build-s: gen-s - (cd obj_dir && make -j -f VVortex_Socket.mk) + (cd obj_dir && make -j -f VVortex.mk) build-sd: gen-sd - (cd obj_dir && make -j -f VVortex_Socket.mk) + (cd obj_dir && make -j -f VVortex.mk) build-st: gen-st - (cd obj_dir && make -j -f VVortex_Socket.mk) + (cd obj_dir && make -j -f VVortex.mk) build-m: gen-m - (cd obj_dir && make -j -f VVortex_Socket.mk) + (cd obj_dir && make -j -f VVortex.mk) build-md: gen-md - (cd obj_dir && make -j -f VVortex_Socket.mk) + (cd obj_dir && make -j -f VVortex.mk) build-mt: gen-mt - (cd obj_dir && make -j -f VVortex_Socket.mk) + (cd obj_dir && make -j -f VVortex.mk) run: run-s run-s: build-s - (cd obj_dir && ./VVortex_Socket) + (cd obj_dir && ./VVortex) run-sd: build-sd - (cd obj_dir && ./VVortex_Socket) + (cd obj_dir && ./VVortex) run-st: build-st - (cd obj_dir && ./VVortex_Socket) + (cd obj_dir && ./VVortex) run-m: build-m - (cd obj_dir && ./VVortex_Socket) + (cd obj_dir && ./VVortex) run-md: build-md - (cd obj_dir && ./VVortex_Socket) + (cd obj_dir && ./VVortex) run-mt: build-mt - (cd obj_dir && ./VVortex_Socket) + (cd obj_dir && ./VVortex) clean: rm -rf obj_dir \ No newline at end of file