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Modified RV32F instructions to support 64-bit register file and added RV64F ISA extension

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This commit is contained in:
Santosh Raghav Srivatsan
2021-12-06 18:55:13 -05:00
parent 30a0d34151
commit e6eda67d0c
21 changed files with 459 additions and 316 deletions
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16
sim/simX/warp.cpp
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@@ -14,8 +14,8 @@ Warp::Warp(Core *core, Word id)
: id_(id)
, core_(core) {
// simx64
iRegFile_.resize(core_->arch().num_threads(), std::vector<Word>(core_->arch().num_regs(), 0));
fRegFile_.resize(core_->arch().num_threads(), std::vector<Word>(core_->arch().num_regs(), 0));
iRegFile_.resize(core_->arch().num_threads(), std::vector<DoubleWord>(core_->arch().num_regs(), 0));
fRegFile_.resize(core_->arch().num_threads(), std::vector<DoubleWord>(core_->arch().num_regs(), 0));
vRegFile_.resize(core_->arch().num_regs(), std::vector<Byte>(core_->arch().vsize(), 0));
this->clear();
}
@@ -36,7 +36,7 @@ void Warp::step(Pipeline *pipeline) {
/* Fetch and decode. */
HalfWord fetched = core_->icache_fetch(PC_);
Word fetched = core_->icache_fetch(PC_);
auto instr = core_->decoder().decode(fetched, PC_);
// Update pipeline
@@ -86,10 +86,12 @@ void Warp::step(Pipeline *pipeline) {
D(4, "Register state:");
for (int i = 0; i < core_->arch().num_regs(); ++i) {
DPN(4, " %r" << std::setfill('0') << std::setw(2) << std::dec << i << ':');
for (int j = 0; j < core_->arch().num_threads(); ++j) {
// simx64
DPN(4, ' ' << std::setfill('0') << std::setw(16) << std::hex << iRegFile_[j][i] << std::setfill(' ') << ' ');
}
// for (int j = 0; j < core_->arch().num_threads(); ++j) {
// // simx64
// DPN(4, ' ' << std::setfill('0') << std::setw(16) << std::hex << iRegFile_[j][i] << std::setfill(' ') << ' ');
// }
DPN(4, ' ' << std::setfill('0') << std::setw(16) << std::hex << iRegFile_[0][i] << std::setfill(' ') << ' ');
DPN(4, ' ' << std::setfill('0') << std::setw(16) << std::hex << fRegFile_[0][i] << std::setfill(' ') << ' ');
DPN(4, std::endl);
}
}