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Fix issues quartus synthesis issues

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wgulian3
2020-02-18 13:24:18 -05:00
parent d71f8fcc73
commit e76d05f7ce
6 changed files with 15 additions and 10 deletions
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1
rtl/quartus/project.tcl
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@@ -70,6 +70,7 @@ set_global_assignment -name VERILOG_FILE ../shared_memory/VX_shared_memory_block
set_global_assignment -name VERILOG_FILE ../shared_memory/VX_shared_memory.v
set_global_assignment -name VERILOG_FILE ../shared_memory/VX_priority_encoder_sm.v
set_global_assignment -name VERILOG_FILE ../shared_memory/VX_bank_valids.v
set_global_assignment -name VERILOG_FILE ../compat/VX_divide.v
set_global_assignment -name VERILOG_FILE ../VX_alu.v
set_global_assignment -name VERILOG_FILE ../VX_back_end.v
set_global_assignment -name VERILOG_FILE ../VX_context.v

3
rtl/quartus/vortex.sdc
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@@ -4,3 +4,6 @@ create_clock -name {clk} -period "400 MHz" -waveform { 0.0 1.0 } [get_ports {clk
derive_pll_clocks -create_base_clocks
derive_clock_uncertainty